KR20030040993A - Multi-chip package semiconductor memory device - Google Patents

Abstract

PURPOSE: A multichip package semiconductor memory device is provided to be capable of performing a package test using a test infra for a single chip package test. CONSTITUTION: A multichip package semiconductor memory device includes two semiconductor memory chips(200,300) having the same configuration and eight data pins(DQ0-DQ7). One memory chip(200) includes a memory cell array(210) for storing data, data pins(DQ0-DQ3), a write circuit(220) for receiving data via the data pins(DQ0-DQ3) to write the received data in the memory cell array(210), a read circuit(230) for reading out data from the memory cell array(210) to transfer the read data via the data pins(DQ0-DQ3), and an inverter(260) for receiving a multichip package test control signal(Scon) to output an inverted version of the multichip package test control signal.

Description

Multi-chip package semiconductor memory device {MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device, and more particularly, to a multi-chip package semiconductor memory device capable of package testing using a test infrastructure for testing a single chip package.

Generally, a test circuit is included in a semiconductor memory device to test the semiconductor memory device.

Hereinafter, a test method of a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a test method of a conventional single chip package semiconductor memory device. 1 shows a semiconductor memory device having four external data pins and accessing a memory cell array with 16 bits for input and output of data.

As shown in FIG. 1, a conventional single chip package semiconductor memory device includes a memory cell array 110 that stores data, data pins DQ0, DQ1, DQ2, and DQ3, and data pins DQ0, DQ1, and DQ2 during a write operation. , The write circuit 120 receiving data from the DQ3 and writing the data to the memory cell array 110, and reading data from the memory cell array 110 during a read operation to the data pins DQ0, DQ1, DQ2, and DQ3. It consists of a readout circuit 130 for transmitting.

In addition, the write circuit 120 receives data from the multiplexer stage 126 and the multiplexer stage 126 that receives 4 bits from the data pins DQ0, DQ1, DQ2, and DQ3 and outputs 16 bits, thereby receiving a memory cell array ( It consists of an input circuit 121 for writing to 110.

In addition, the read circuit 130 receives the 16 bits of data from the output circuit 131 and the output circuit 131 to read and output 16 bits of data from the memory cell array 110 to generate 8 bits of data. The second stage comparator 150 that receives 8-bit data from the first stage comparator 140 and the first stage comparator 140, converts the 4-bit data into 4-bit data, and outputs the data to the data pins DQ0, DQ1, DQ2, and DQ3. It consists of).

The test of the conventional single chip package semiconductor memory device shown in FIG. 1 is as follows.

Data of 1 or 0 is input into the semiconductor memory chip 100 by 4 bits from the test equipment (not shown) through the data pins DQ0, DQ1, DQ2, and DQ3. The input 4-bit data is converted into 16-bit data in the multiplexer stage 126 and written to the memory cell array 110 through the input circuit 121. Here, the data written in the memory cell array 110 are all zeros or all ones. Data written to the memory cell array 110 is transmitted to the first stage comparator 140 through the output circuit 131 by 16 bits. Each of the comparators 132 to 139 constituting the first stage comparator 140 outputs 1 when the two inputs are the same, and outputs 0 when the two inputs are different. The 16-bit data input to the first stage comparator 140 is converted into 8 bits and transmitted to the second stage comparator. The second stage comparator 150 receives 8 bits of data and generates 4 bits of data to generate data. Output to pins DQ0, DQ1, DQ2, and DQ3. If the data output to the data pins DQ0, DQ1, DQ2, and DQ3 is the same as the data input to the data pins DQ0, DQ1, DQ2, and DQ3 at the time of writing, this semiconductor device is judged to be good; Is considered bad.

Recently, a multi-chip package semiconductor device having two or more chips in one package has been widely used. In addition, multi-chip memory devices in which two or more memory chips are mounted in one package are also manufactured. However, in order to test a multi-chip package, the test infrastructure of the existing single chip memory device cannot be used as it is, and a test infrastructure having a new configuration must be prepared. For example, in the case of a package in which two chips each input and output data in 4-bit units, test equipment capable of testing in 8-bit units is required. Therefore, the test equipment capable of testing in a conventional 4-bit unit cannot simultaneously test two chips contained in one package.

An object of the present invention is to provide a multi-chip package semiconductor memory device capable of package testing using a test infrastructure for testing a single chip package.

1 is a schematic block diagram illustrating a test method of a conventional single chip package semiconductor memory device.

2 is a schematic block diagram illustrating a test method of a multi-chip package semiconductor memory device of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 200, 300: semiconductor memory chip 400: package

110, 210: memory cell array 120, 220: write circuit

130, 230: readout circuit 126, 228: multiplexer end

140, 240: first stage comparator 150, 250: second stage comparator

A multi-chip packaged semiconductor memory device of the present invention is a semiconductor memory device including a multi-chip composed of K semiconductor memory chips, each of which can input and output data in units of M bits, comprising: a memory cell array; M data pins; In the single chip test, M bits of data are received from the data pins to generate N bits of data, and in the multi chip test, N bits of M bits are received by receiving a multi-chip package test control signal and K minutes of data from the data pins. A writing circuit comprising multiplexing means for generating data of the data and writing the N data into the memory cell array; And reading N bits of data from the memory cell array in a single chip test, generating M bits of data, and transmitting the M bits of data to the data pin, and receiving the multichip package test control signal in a multichip test. And a readout circuit comprising reading means for reading N bits of data from the memory cell array to generate M bits of data and transmitting the M bits of data to the data pins. It is characterized by.

Hereinafter, a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

2 is a schematic block diagram illustrating a test method of a multi-chip package semiconductor memory device of the present invention.

As shown in FIG. 2, in the multi-chip package semiconductor memory device of the present invention, two semiconductor memory chips 200 and 300 having the same configuration are embedded in one package 400, and eight data pins DQ0 are included. To DQ7). One memory chip 200 receives data from a memory cell array 210 that stores data, data pins DQ0, DQ1, DQ2, and DQ3, and data pins DQ0, DQ1, DQ2, and DQ3 during a write operation. A write circuit 220 for writing to the memory cell array 210, a read circuit 230 for reading data from the memory cell array 210 and transmitting the data to the data pins DQ0, DQ1, DQ2, and DQ3 during a read operation; And an inverter 260 for inputting the multi-chip package test control signal Scon to generate an inverted signal.

In addition, the write circuit 220 receives data from the data pins DQ0, DQ1, DQ2, and DQ3 and generates data from the multiplexer stage 228 and the multiplexer stage 228 that generate and output twice the bits of the received signal. And an input circuit 221 that receives and writes to the memory cell array 210.

Also, the read circuit 230 receives the 16 bits of data from the output circuit 231 and the output circuit 231 to read and output 16 bits of data from the memory cell array 210 to generate 8 bits of data. And a second stage comparator 150 that receives data from the first stage comparator 240 and the first stage comparator 240 and outputs the data to the data pins DQ0, DQ1, DQ2, and DQ3.

Hereinafter, an operation of the multichip package semiconductor memory device according to the present invention will be described with reference to FIG. 2. It is assumed here that the test equipment available can be tested in units of 4 bits.

When the two chips constituting the multi-chip package are tested separately one by one without being tested simultaneously, the following tests are performed in the same manner as in the conventional single chip test. In this case, the multi-chip package test control signal Scon is low and the signal passing through the inverter 260 is high. Thus, the multiplexers 222, 223, 224, and 225 of the multiplexer stage 228 operate, the multiplexers 226, 227 do not operate, and the comparators 241, 242 of the second stage comparator 250. 243 and 244 operate and the comparators 245 and 246 do not.

Data of 1 or 0 is input from the test equipment (not shown) into the semiconductor memory chip 200 in the package 400 by 4 bits through the data pins DQ0, DQ1, DQ2, and DQ3. The input 4-bit data is converted into 16-bit data in the multiplexer stage 228 and written to the memory cell array 110 through the input circuit 221. Here, the data written in the memory cell array 210 are all zeros or all ones. Data written to the memory cell array 210 is transmitted to the first stage comparator 240 through the output circuit 231 by 16 bits. Each of the comparators 232 to 239 constituting the first stage comparator 240 outputs 1 when the two inputs are the same, and outputs 0 when the two inputs are different. The 16-bit data input to the first stage comparator 240 is converted into 8 bits and transmitted to the second stage comparator 250. The second stage comparator 250 receives 8 bits of data and receives 4 bits of data. Generate and output to the data pins DQ0, DQ1, DQ2, and DQ3. Each of the comparators 241 to 246 constituting the second stage comparator 240 also outputs 1 when the two inputs are the same and 0 when the two inputs are different. If the data output to the data pins DQ0, DQ1, DQ2, and DQ3 is the same as the data input to the data pins DQ0, DQ1, DQ2, and DQ3 at the time of writing, this semiconductor device is judged to be good; Is considered bad.

In the case of simultaneously testing two chips constituting a multi-chip package, the following test is performed in the same manner as the conventional single chip test. In this case, the multi-chip package test control signal Scon is high and the signal passing through the inverter 260 is low. Accordingly, the multiplexers 222, 223, 224, and 225 of the multiplexer stage 228 do not operate, the multiplexers 226, 227 operate, and the comparators 241, 242 of the second stage comparator 250. 243 and 244 do not operate, and the comparators 245 and 246 operate.

Since the available test equipment can be tested only in units of 4 bits, two bits can be allocated to each of the semiconductor memory chip 200 and the semiconductor memory chip 300. Hereinafter, two data pins of the semiconductor chip 200 will be described. The case where (DQ0 and DQ2) are allocated will be described as an example.

Data of 1 or 0 is input into the semiconductor memory chip 200 in the package 400 by two bits from the test equipment (not shown) through the data pins DQ0 and DQ2. The input 2-bit data is converted into 16-bit data in the multiplexer stage 228 where the multiplexers 226 and 227 operate and is written to the memory cell array 210 through the input circuit 221. Here, the data written in the memory cell array 210 are all zeros or all ones. Data written to the memory cell array 210 is transmitted to the first stage comparator 240 through the output circuit 231 by 16 bits. The 16-bit data input to the first stage comparator 240 is converted into 8 bits and transmitted to the second stage comparator 250, and the second stage comparator 250 in which the comparators 245 and 246 operate is 8 bits. Receives data of 2 bits and generates 2 bits of data and outputs them to data pins DQ0 and DQ2. If the data output to the data pins DQ0 and DQ2 is the same as the data input to the data pins DQ0 and DQ2 at the time of writing, this semiconductor device is judged to be good, and if different, the semiconductor device is determined to be bad.

The multi-chip package test control signal Scon is a signal that becomes high when simultaneously testing two chips 200 and 300 in the package 400, and mainly uses a signal of a mode register and, if necessary, It can be applied externally when testing a multi-chip package.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, according to the multi-chip package semiconductor memory device according to the present invention, since the multi-chip package test can be performed using a test infrastructure for testing a single-chip package previously used, a separate test for the multi-chip package test There is no need to build infrastructure, which saves time and money.

Claims (2)

A semiconductor memory device comprising a multi-chip composed of K semiconductor memory chips and each of the multi-chips capable of inputting and outputting data in units of M bits, Memory cell arrays; M data pins; In the single chip test, M bits of data are received from the data pins to generate N bits of data, and in the multi chip test, N bits of M bits are received by receiving a multi-chip package test control signal and K minutes of data from the data pins. A writing circuit comprising multiplexing means for generating data of the data and writing the N data into the memory cell array; And Reads N bits of data from the memory cell array in a single chip test, generates M bits of data, and transmits the M bits of data to the data pins, and receives the multichip package test control signal in a multichip test. And a reading circuit including reading means for reading N bits of data from the memory cell array to generate M bits of data and transmitting the M bits of data to the data pins. A multi-chip package semiconductor memory device characterized in that. The semiconductor device of claim 1, further comprising a mode register. The multi-chip package test control signal is generated from the mode register by a signal input from the outside when the mode is set.