KR20030037462A - Apparatus for processing data in W-CDMA WLL PCI terminal and method thereof - Google Patents

Abstract

PURPOSE: A method of processing data in a W-CDMA WLL PCI(Peripheral Component Interconnect) terminal is provided to perform mastering for controlling a bus in a PCI controller in order to implement DMA(Direct Memory Access) for each device by a CPU, thereby improving a data rate by reducing a path of an internal device. CONSTITUTION: A W-CDMA WLL PCI terminal performs a bus mastering to control a bus in a PCI controller instead of a CPU(51). The CPU controls each device, and performs a DMA process(52). A main PC inputs data to the W-CDMA WLL PCI terminal(53). The PCI controller separates the inputted information into data and an address, and transmits the separated information to an FPGA(Field Programmable Gate Array)(54). The FPGA converts the inputted data in HDLC format, and transmits the converted data to a modem in serial(55). The modem band-spreads the transmitted data, and transmits the data to an RF module(56).

Description

APPARATUS FOR PROCESSING DATA IN W-CDMA WLL PCI TERMINAL AND METHOD}

The present invention relates to an apparatus and a method for improving data processing speed in a mobile communication system, and more particularly, to W-CDMA (Wideband Code Division Multiple Access) Wireless Local Loop (WLL) (Peripheral Component Interconnect) Peripheral device interconnection The terminal reduces the path of the internal device to improve the data processing speed by performing the mastering that delegates control of the bus to the PCI controller so that the CPU implements DMA for each device. An apparatus and method for making a

More specifically, the present invention provides a system in which a PC and a W-CDMA WLL PCI terminal connected to the PC are configured, wherein information (data and address) output from the PC is input through a PCI slot, and the CPU is in DMA mode. A PCI controller having control of the bus; An FPGA for converting data input from the PCI controller into an HDLC protocol frame format; A modem processing data input from the FPGA through wideband code division multiple access (W-CDMA) spread spectrum; RF module unit for converting the data inputted from the modem and transmits; the bus module is configured to perform bus mastering so that the PCI controller can control the bus instead of the CPU of the W-CDMA WLL PCI terminal, the CPU each component By DMA (Device), the data transfer speed can be improved.

Hereinafter, the prior art will be described.

1 is a HDLC protocol frame structure applied to the conventional and the present invention.

The HDLC is a representative data communication transmission control procedure used in a packet switched network or an integrated information communication network (ISDN). It is standardized by the International Organization for Standardization (ISO), and a basic mode transmission control procedure has been used as a transmission control procedure for data communications for a long time. However, as the communication between computers and the exchange of information through a complex communication network are required, more efficient and reliable transmission control procedures are required, and high data link control procedures (HDLC) have been used since the late 1970s.

As shown in the figure, in HDLC, information is divided and transmitted in units of frames. Partial transmission of data is the same as the basic mode transmission control procedure. However, a distinctive feature is that a code necessary for transmission control is always collected at the first part of a frame to be clearly distinguished from information.

The position of the frame is easily detected because the opening and closing flags of each frame are wrapped in a flag of 8-bit code (01111110).

In HDLC, six consecutive ones are limited to flags, and if six or more consecutive ones are included in the information, zeros are forced to be added after the fifth so that the flag can be clearly distinguished from the flag.

Next to the flag is an address address indicating the identification number of the transmitting side and the receiving side, a control symbol indicating various control information, a data information portion of arbitrary length, and a frame error check sequence. There is.

If an error is detected at the receiving end, retransmission is requested. Therefore, high reliability is ensured.

HDLC is a representative protocol of the data link layer (second layer) of the OSI basic reference model, and HDLC is also used in an X.25 based packet switching network or a signaling method through an ISDN D channel.

2 is a block diagram of a conventional W-CDMA PCI terminal connected to the main PC 10. As shown in FIG.

First, in the conventional conventional W-CDMA WLL PCI terminal, it was developed to be connected to the PCI slot inside the PC using PCI Spec. V.21 to implement the WLL terminal as a PCI card type, and 5V It has an operating voltage and clock speed of 33MHz.

The PC's CPU 10 and usually four PCI slots are also selected via the PCI Bus Arbitration Controller (10a) in the PC mainboard.

2 is composed of a main PC 10 and a W-CDMA PCI terminal 20.

The W-CDMA PCI terminal 20 includes: a PCI controller 22 into which information (data and address) output from the PC 10 is input through the PCI slot 21; The PCI controller separates the input information into data and addresses, respectively, and transfers the data to the DPRAM 23, which is a dual port RAM.

The HDLC CONTROLLER 25 converts the data stored in the DPRAM into HDLC PROTOCOL FORMAT and transmits the data to the FPGA 26 (Field Programmable Gate Array), which transmits the data to the modem 27, and in the modem, W- After the data is processed through CDMA spread spectrum, the data is transmitted to the RF module 28, and the RF module converts the data to analog and transmits the data.

The operation according to the configuration of FIG. 2 will be described.

In the conventional W-CDMA WLL PCI terminal 20, information input from the PC 10, that is, A / D (Analoge / Digital) data in which 32-bit addresses and data are muxed in the PCI slot 21 is stored in the PCI controller ( 22).

In the PLX which is a PCI controller 22, the input information is divided into addresses and data, and divided into 8 bits and loaded on an 8-bit bus for transmission to a DPRAM 23 having an 8K byte capacity.

The HDLC controller 25 converts the data into the HDLC FORMAT of FIG. 1 and transmits the data to the FPGA 26 in parallel by 8 bits, and the FPGA loads the parallel data into the E-1 TIME SLOT and transmits the modem as serial data. Send to 27.

The modem processes the data through W-CDMA spread spectrum and transmits the data to the RF module 28. In the RF module, the digital signal is converted into an analog signal through an A / D converter and then transmitted.

In the W-CDMA PCI terminal board, the CPU 24 controls each component.

3 is a flowchart of data processing in a conventional W-CDMA WLL PCI terminal.

Data is input from the main PC 10 to the W-CDMA WLL PCI terminal 20. (Step 31).

That is, information (data and address) is input to the PCI controller through the PCI slot.

In the PCI controller, the input information is separated into data and an address and transmitted to the DPRAM. (Step 32).

The stored data transmitted to the DPRAM is converted into HDLC format by the HDLC controller and transmitted to the FPGA. (Step 33).

The FPGA transmits data serially to the modem. (Step 34).

The modem transmits the transmitted data to the RF module after spread spectrum processing. (Step 35).

In the RF module, a digital signal is converted into an analog signal through an A / D converter and then transmitted.

However, in the conventional configuration and operation as described above, since the interrupt driving method for interrupting the CPU 24 whenever each component processes the data, the data transfer rate decreases for that time. The load on the processor is a big disadvantage.

In addition, the configuration as shown in FIG. 2 causes a large burden on the CPU 24 due to a long PATH of data, and since data is transmitted in 8 bits to the DPRAM 23 and the HDLC CONTROLLER 25, the processing speed of the internal data decreases. Will result.

Therefore, the present invention proposes to improve the internal processing speed to improve the data processing speed of the W-CDMA WLL PCI terminal to a near speed or to develop at the Mbps level, and removes the conventional DPRAM and HDLC controller from the configuration, and the present invention. It is proposed to improve the transmission efficiency by shortening the data processing path by allowing the PCI controller to control the bus of each configuration, the FPGA to convert the input data into the HDLC protocol FORMAT, and the CPU to perform the DMA function. .

1 is a HDLC protocol frame structure applied to the conventional and the present invention

2 is a block diagram of a conventional W-CDMA PCI terminal connected to a main PC 10.

3 is a flowchart of data processing in a conventional W-CDMA WLL PCI terminal;

4 is a block diagram of a W-CDMA PCI terminal 40 of the present invention connected to a main PC 10. FIG.

5 is a flowchart of data processing in a W-CDMA WLL PCI terminal of the present invention.

In the data processing apparatus of the W-CDMA WLL PCI terminal of the present invention, in a system composed of a PC and a W-CDMA WLL PCI terminal connected to the PC, information (data and address) output from the PC is transmitted through a PCI slot. A PCI controller which is input and has a CPU having control of a bus in DMA mode; An FPGA for converting data input from the PCI controller into an HDLC protocol frame format; A modem processing data input from the FPGA through wideband code division multiple access (W-CDMA) spread spectrum; And a RF module unit for converting and transmitting data input from the modem.

In addition, the data processing method in the W-CDMA WLL PCI terminal, comprising: performing bus mastering so that the PCI controller can control the bus instead of the CPU of the W-CDMA WLL PCI terminal; Inputting information output from the PC to the PCI controller through the PCI slot; Converting information input from the PCI controller into an HDLC protocol frame format in an FPGA and transmitting the information to a modem; Converting the input data and transmitting the converted data to the RF module unit.

Other objects and features of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, data processing in a W-CDMA WLL PCI terminal according to the present invention will be described with reference to the accompanying drawings.

4 is a block diagram of the W-CDMA PCI terminal 40 of the present invention connected to the main PC 10. As shown in FIG.

In the W-CDMA PCI terminal 40, information (data and address) output from the PC 10 is input through the PCI slot 41, and the PCI controller 42 in which the CPU has control of the bus in the DMA mode. )Wow; An FPGA (44) for converting data input from the PCI controller into an HDLC protocol frame format; A modem (45) for processing data through wideband code division multiple access (W-CDMA) spreading of data input from the FPGA; RF module unit 46 for converting and transmitting data input from the modem is configured.

The operation according to the configuration of FIG. 4 will be described.

First, the configuration of the present invention has a configuration in which the DPRAM 23 and the HDLC controller 25 which are components of FIG. 2 are deleted.

The information input from the PC 10 in the W-CDMA WLL PCI terminal 40 is, namely, A / D (Analoge / Digital) data in which 32 bits of address and data are mixed in the PCI slot 41 as addresses and data. It is separated and input to the PCI controller 42 having the control right of the bus by the DMA mode.

PLX, a PCI controller 42, separates the input information into an address and data, and sends the information directly to the FPGA 44.

The FPGA 44 converts the input information into the HDLC FORMAT of FIG. 1 and transmits the information to the modem 45 as serial data.

The modem processes the data through W-CDMA spread spectrum and transmits the data to the RF module 28. In the RF module, the digital signal is converted into an analog signal through an A / D converter and then transmitted.

In the W-CDMA PCI terminal board, the CPU 43 implements direct memory access (DMA) by performing bus mastering, which delegates control of the bus to the PCI controller 42.

Therefore, the CPU no longer participates in data transmission and controls each component, and bus control is performed by the PCI controller.

5 is a flowchart of data processing in a W-CDMA WLL PCI terminal of the present invention.

Bus mastering is performed so that the PCI controller can control the bus instead of the CPU of the W-CDMA PCI terminal. (Step 51).

The CPU 43 controls the respective devices and performs DMA capable. (Step 52).

Data is input from the main PC 10 to the W-CDMA WLL PCI terminal 20. (Step 53).

That is, information (data and address) is input to the PCI controller through the PCI slot.

In the PCI controller, the input information is separated into data and an address and transmitted to the FPGA. (Step 54).

The FPGA converts the input data into HDLC format and transmits the data serially to the modem. (Step 55).

The modem transmits the transmitted data to the RF module after spread spectrum processing. (Step 56).

In the RF module, a digital signal is converted into an analog signal through an A / D converter and then transmitted.

As described above, the present invention eliminates the conventional DPRAM and HDLC controller configurations, and improves the data processing speed by implementing DMA by performing bus mastering in which the CPU delegates bus control to the PCI controller.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments.

Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

According to the data processing method of the present invention, the CPU controls each component, but if a DMA controller is used, the CPU transfers the bus control authority to the PCI controller, so that each component needs to try to interrupt the CPU whenever data is processed. And the conventional DPRAM and HDLC controllers have been eliminated, the processing path is shortened and the data processing speed is improved.

Claims (4)

In a system configured with a PC and a terminal connected to the PC, A PCI controller, through which information output from the PC is input through a PCI slot and the CPU has control of the bus in DMA mode; An FPGA for converting data input from the PCI controller into an HDLC protocol frame format; A modem processing data input from the FPGA through wideband code division multiple access (W-CDMA) spread spectrum; RF module unit for converting and transmitting the data input from the modem; W-CDMA WLL PCI terminal data processing apparatus comprising a. The W-CDMA WLL PCI terminal of claim 1, wherein the PCI controller separates the input information into an address and data and transmits the information to the FPGA, and the FPGA transmits the data serially to the modem. Device. Performing bus mastering so that the PCI controller can control the bus instead of the CPU of the W-CDMA WLL PCI terminal; Inputting information output from the PC to the PCI controller through the PCI slot; Converting information input from the PCI controller into an HDLC protocol frame format in an FPGA and transmitting the information to a modem; Converting the input data and transmitting the converted data to an RF module unit. 4. The data processing method of claim 3, wherein the CPU implements DMA by performing bus mastering to delegate control of the bus to the PCI controller.