KR20030033810A - High voltage semiconductor devcie having burried transistor and method for fabricating the same - Google Patents

Abstract

PURPOSE: A high voltage semiconductor device having a buried transistor and a manufacturing method thereof are provided to be capable of reducing process difficulties due to the topology of a gate, and improving the degree of integration and operational characteristics. CONSTITUTION: An SOI(Silicon On Insulator) substrate(20) is formed by sequentially forming a buried oxide layer(12) and a silicon layer(13) on a silicon substrate(11). An isolation layer(22) connected with the buried oxide layer is formed on the predetermined portion of the buried oxide layer for defining an active region. After forming a trench in the active region, a gate(29) is formed on the center portion of the trench and a polysilicon spacer(30) is formed at both sidewalls of the trench, simultaneously. At this time, the polysilicon spacer is used as a buffer, thereby increasing breakdown voltage. A source and drain region(27) are formed at both sides of the gate(29). An interlayer dielectric(31) is formed on the resultant structure. The first, second and third metal wiring(34a,34b,34c) are formed on the interlayer dielectric for contacting the gate, the source and drain region, respectively. At the time, a transistor is buried in the trench, so that difficulties caused by the topology of a common transistor are solved.

Description

HIGH VOLTAGE SEMICONDUCTOR DEVCIE HAVING BURRIED TRANSISTOR AND METHOD FOR FABRICATING THE SAME

The present invention relates to a high-voltage semiconductor device, and more particularly, to a high-voltage semiconductor device and a method of manufacturing the same that can improve the degree of integration and operating characteristics while improving the process difficulties due to the topology.

As high integration and high performance of semiconductor devices are progressed, the size of patterns included in circuits is reduced, and various process technologies are being applied and developed to obtain excellent device characteristics in accordance with this trend.

Meanwhile, a semiconductor device having a critical dimension of 0.5 μm or less uses a low power of 3.3 V or less as a power supply for reducing power consumption and ensuring reliability, and in fact, many microprocessors or memory devices use 3.3 V. Alternatively, a 2.5V power supply is used as the standard power supply. However, such low voltage semiconductor devices are interconnected with other peripheral devices in one system, and in particular, since the peripheral devices use a high voltage of 5 V or higher as a power supply, an external chip using the high voltage in a circuit. A high voltage transistor must be provided to support the input voltage supplied from.

1 is a cross-sectional view illustrating a conventional high voltage semiconductor device having a high voltage transistor, and a manufacturing method thereof will be described below with reference to the drawing.

First, a high voltage P-type or N-type well 2 is formed in a p-type silicon substrate 1, and then the device isolation film 3 is placed in place on the substrate 1 through a known LOCOS process. Form. Subsequently, a drift photo process and an ion implantation process are performed, and then the gate electrode 5 is formed on the active region of the silicon substrate 1 defined by the device isolation film 3 through deposition and patterning of the polysilicon film. ).

Next, high concentration ion implantation and annealing are performed on the resultant to form source and drain regions 7 having high voltage drift regions 6 in the substrate regions on both sides of the gate electrode 5. Then, an interlayer insulating film 8 is formed on the resultant, and then the gate electrode 5 and the source / drain regions 7 are formed by the contact plug 9 on the interlayer insulating film 8 through a known process. ) To form metal wires 10 in contact with each other.

However, the conventional high voltage semiconductor device as described above, first, because of the device isolation structure by the LOCOS process, there is a problem that the cell density is reduced due to buzz-big, etc., second, the gate electrode is formed on the substrate There is a problem in that there is a process difficulty due to the topology, and thirdly, since the voltage applied to the drain region depends on the junction area of the drain, there is a problem that the area of the transistor is increased when the high voltage is implemented. When applied, there is a problem in that the operation characteristics of the transistor are deteriorated due to the influence of the capacitor due to the metal wiring.

Accordingly, an object of the present invention is to provide a high voltage semiconductor device and a method of manufacturing the same, which can improve the integration and operating characteristics while improving the process difficulty due to the topology. .

1 is a cross-sectional view showing a conventional high voltage semiconductor device.

2 is a plan view illustrating a high voltage semiconductor device according to an embodiment of the present invention.

3A to 3F are cross-sectional views of processes according to line A-A 'of FIG. 2 for explaining a method of manufacturing a high voltage semiconductor device according to an embodiment of the present invention.

4A and 4B are sectional views taken along the line BB ′ of FIG. 2, corresponding to FIGS. 3E and 3F.

Explanation of symbols on the main parts of the drawings

11 silicon substrate 12 buried oxide film

13: silicon layer 20: S-OI substrate

21: thermal oxide film 22: device isolation film

23: first photosensitive film pattern 24: trench

25 second photosensitive film pattern 26 drift region

27 source / drain region 28 gate electrode

29 gate 30 polysilicon spacer

31 interlayer insulating film 31a BPSG film

31b: SOG film 32, 33: contact plug

34a, 34b, 34c: metal wiring

The high voltage semiconductor device of the present invention for achieving the above object, the SOI substrate having a stacked structure of a silicon substrate, a buried oxide film and a silicon layer; An isolation layer formed in contact with the buried oxide film to define an active region in place of the silicon layer; A trench formed in an active region of the silicon layer defined by the device isolation film; A gate formed on a central portion and an outer side of the trench; Polysilicon spacers formed on trench sidewalls on both sides of the gate; Source and drain regions having drift regions formed on surfaces of active regions on both sides of the gate; An interlayer insulating layer formed on the remaining gate portions except the gate portion outside the trench, the device isolation layer, and the silicon layer; First, second, and third metal wires formed on the interlayer insulating layer to contact the gate, source, and drain regions, respectively.

In the high voltage semiconductor device of the present invention, the interlayer insulating film includes a BPSG film formed to fill the trench, an SOG film formed on the BPSG film, an isolation layer, and a silicon layer, and the first metal wiring is formed in the trench. Direct contact is made with the gate portion formed outside, and the second and third metal wirings are contacted with the source and drain regions by contact plugs.

Method of manufacturing a high voltage semiconductor device of the present invention for achieving the above object comprises the steps of providing an SOH substrate having a laminated structure of a silicon substrate, a buried oxide film and a silicon layer; Forming an isolation layer in contact with the buried oxide film to define an active region in place of the silicon layer; Forming a trench in an active region of a silicon layer defined by the device isolation film; Forming a first photoresist pattern on a central portion and an outer side of the trench; Performing drift ion implantation into silicon layers on both sides using the first photoresist pattern as a mask; Removing the first photoresist pattern, and forming a second photoresist pattern on a central portion and an outer side of the trench; Performing source and drain ion implantation into the silicon layers on both sides using the second photoresist pattern as a mask; Removing the second photoresist pattern and performing annealing to form a source and a drain region having a drift region thereunder; Forming a doped polysilicon film on the resulting product up to this step; Patterning the doped polysilicon layer to form a gate on the center and the outside of the trench and simultaneously forming polysilicon spacers on the sidewalls of the trench; Forming an interlayer insulating film on the resultant to cover the remaining gate portions except the gate portion outside the trench, the device isolation layer, and the silicon layer; Forming first and second contact plugs in contact with the source and drain regions, respectively, in place of the interlayer insulating film; And forming first, second and third metal wires on the interlayer insulating layer, the first and second metal wires contacting the gate and the first and second contact plugs, respectively.

Here, the method of manufacturing a high voltage semiconductor device of the present invention further includes performing a threshold voltage ion implantation between forming the trench and forming the first photoresist pattern. In addition, in the method of manufacturing the high voltage semiconductor device of the present invention, the forming of the interlayer insulating film may include depositing a BPSG film to fill the trench; Spin coating an SOG film on the BPSG film, the device isolation film, the silicon layer and the gate; And polishing the SOG film until the gate portion outside the trench is exposed.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating a high voltage semiconductor device according to an exemplary embodiment of the present invention, wherein reference numeral 23 denotes an isolation layer, 24 trenches, 29 polysilicon gates, and 32a, 32b, and 32c gates. And first, second and second metal wirings in contact with the source and drain regions, respectively.

As shown, the high voltage semiconductor device of the present invention is provided with a trench 24 in the active region defined by the isolation layer 23, the gate 29 is formed on the center and the outside of the trench. The metallizations 32a, 32b and 32c are also in contact with the source and drain regions (not shown), i.e. by contact plugs, but with the gate 29 directly in the outer portion of the trench 24. do. Therefore, the interlayer insulating film 30 is formed so as not to cover the gate portion outside the trench 24.

3A to 3F are cross-sectional views of processes according to line A-A 'of FIG. 2 for explaining a method of manufacturing a high voltage semiconductor device having a buried transistor according to an embodiment of the present invention.

Referring to FIG. 3A, a silicon on insulator (SOI) substrate 20 having a stacked structure of a silicon substrate 11, an buried oxide film 12, and a silicon layer 13 is provided. Then, in the state where the thermal oxide film 21 is formed on the surface of the silicon layer 13 by performing a surface oxidation process, a photo and ion implantation process for forming N-well / P-well, and a high voltage N Photo- and ion implantation processes for forming wells / P-wells are sequentially performed to form N-wells / P-wells and high-voltage N-wells / P-wells in the silicon layer 13, although not shown. do. Subsequently, a trench type device isolation film 22 defining an active region is formed in contact with the buried oxide film 12 in place of the silicon layer 13 through a known STI process.

Referring to FIG. 3B, in a state in which a photosensitive film is coated on the thermal oxide film 21, the photosensitive film is exposed and developed to form a first photoresist film pattern 23 covering the device isolation layer 22 and a part of the active region adjacent thereto. Then, the exposed portion of the thermal oxide film and the portion of the silicon layer below the first photoresist pattern 23 as an etch mask are etched to form a trench 24 having a predetermined depth and size in the active region of the silicon layer 13. Next, ion implantation is performed to adjust the threshold voltage Vt of the trench in the active region under the trench 24 using the first photoresist pattern 23 as an ion implantation mask.

Referring to FIG. 3C, in a state in which the first photoresist pattern is removed, a drift photo process, that is, the photoresist is applied again on the resultant, and then exposed and developed to expose the center portion and the outside of the trench 24. A second photosensitive film pattern 25 is formed on the silicon layer portion, and then low energy and low concentration drift ion implantation is performed using the second photosensitive film pattern 25 as an ion implantation mask.

Subsequently, although not shown, in the state where the second photoresist pattern is removed, a third photoresist pattern covering the source / drain formation region is formed, and then, using the third photoresist pattern as an ion implantation mask, high energy and high concentration are formed. Ion implantation is carried out.

Referring to FIG. 3D, annealing is performed on the resultant to form source and drain regions 27 in each of the silicon layer regions on both sides of the third photoresist pattern. In this case, the source and drain regions 27 are formed under the trench 24 and the surface of the silicon layer 13, and under the source and drain regions 27 below the trench 24, the drift region 28 is formed. ) Is formed.

Subsequently, in a state where the third photoresist pattern is removed, a polysilicon film is deposited on the resultant through a gate oxide film (not shown), and then doped with POCl _{3 in the} polysilicon film, and then, The doped polysilicon film and the gate oxide film are patterned to form a polysilicon gate 29 on the center and the outside of the trench 25. In this case, polysilicon spacers 30 are formed on sidewalls of the trenches 24 at both sides of the gate 29 to function as a buffer in the manufactured high voltage semiconductor device, that is, to increase the breakdown voltage by a cap action. .

Referring to FIG. 3E, an interlayer insulating film 30 is formed on the resultant up to the above step, but first, a BPSG film 31a having excellent buried characteristics in the trench 24 in which the gate 29 and the polysilicon spacer 30 are formed. Next, the SOG film 31b is deposited by spin coating on the BPSG film 31a, the gate portion outside the trench, and the silicon layer 13 and the device isolation film 22. Then, the surface of the SOG film 31b is polished by a chemical mechanical polishing (CMP) process until the gate portion outside the trench is exposed.

FIG. 4A is a cross-sectional view along the line BB ′ of FIG. 2 corresponding to FIG. 3E, as shown, the gate portion formed on the outside of the trench 24 is exposed by polishing the surface of the SOG film 31b. On the other hand, the gate portion formed in the trench 24 is buried by the SOG film 31b.

Referring to FIG. 3F, contact holes are formed to expose the source and drain regions 27, respectively, through a known contact process, and then the source and drain regions 27 are embedded by filling a conductive film in the contact holes. And first and second contact plugs 32 and 33 are respectively contacted with each other.

Subsequently, a predetermined metal film is deposited on the contact plugs 32 and 33 and the SOG film 31b, and then patterned to form a first metal wire directly contacting the gate portion disposed outside the trench 24. 34a and second and third metal wires 34b and 34c contacting the source and drain regions 27 by the first and second contact plugs 32 and 33, respectively.

FIG. 4B is a cross-sectional view taken along the line BB ′ of FIG. 2 corresponding to FIG. 3F, and as shown, the first metal wire 34a is in contact with the gate portion formed outside the trench 24.

Thereafter, although not shown, a well-known subsequent process is performed to complete the high voltage semiconductor device having the buried transistor according to the embodiment of the present invention.

In the high voltage semiconductor device of the present invention having the structure as described above, since the device isolation film is formed by the STI process rather than the LOCOS process, the conventional cell density reduction problem caused by the buzz-big and the like is solved.

In addition, in the high voltage semiconductor device of the present invention, the transistor is buried in the trench, and thus, compared with a conventional structure in which a gate is formed on a substrate surface, a process difficulty occurs due to the topology of the gate. Is solved.

In addition, the high voltage semiconductor device of the present invention can increase the area of the source and drain regions as compared with the conventional one, and can suppress the short channel effect without increasing the area of the transistor, as well as improve the junction breakdown voltage. .

In addition, since the high-voltage semiconductor device of the present invention forms a polysilicon buffer capable of increasing the breakdown voltage by capping on both sides of the gate, it is possible to suppress the occurrence of punch-through.

In addition, since the high voltage semiconductor device of the present invention directly contacts the gate and the metal wiring, the voltage efficiency can be maximized.

In addition, since the high voltage semiconductor device of the present invention uses a buried transistor, the thickness of the interlayer insulating film can be reduced, whereby the advantages in the process and the electrical characteristics can be obtained.

As described above, according to the present invention, by forming a high voltage transistor in a high voltage semiconductor device in a buried type, it is possible to improve the degree of integration without increasing the area while solving the process difficulties caused by the topology. In addition, the present invention can not only secure stable device characteristics but also improve characteristics by increasing source and drain regions, direct contact between gate and metal wiring, reducing interlayer dielectric thickness, and forming polysilicon spacers. have.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (7)

A SOI substrate having a stacked structure of a silicon substrate, an buried oxide film, and a silicon layer; An isolation layer formed in contact with the buried oxide film to define an active region in place of the silicon layer; A trench formed in an active region of the silicon layer defined by the device isolation film; A gate formed on a central portion and an outer side of the trench; Polysilicon spacers formed on trench sidewalls on both sides of the gate; Source and drain regions having drift regions formed on surfaces of active regions on both sides of the gate; An interlayer insulating layer formed on the remaining gate portions except the gate portion outside the trench, the device isolation layer, and the silicon layer; And first, second and third metal interconnections formed on the interlayer insulating layer to contact the gate, source, and drain regions, respectively. The high voltage semiconductor device of claim 1, wherein the drift region is formed under a source and a drain region under the trench. The method of claim 1, wherein the interlayer insulating film A BPSG film formed to fill the trench; And And a SOG film formed on the BPSG film, the device isolation film, and the silicon layer. The method of claim 1, wherein the first metal wiring is in direct contact with the gate portion disposed outside the trench, and the second and third metal wiring is in contact with the source and drain regions by a contact plug. High voltage semiconductor devices. Providing an S-OI substrate having a stacked structure of a silicon substrate, an buried oxide film, and a silicon layer; Forming an isolation layer in contact with the buried oxide film to define an active region in place of the silicon layer; Forming a trench in an active region of a silicon layer defined by the device isolation film; Forming a first photoresist pattern on a central portion and an outer side of the trench; Performing drift ion implantation into silicon layers on both sides using the first photoresist pattern as a mask; Removing the first photoresist pattern, and forming a second photoresist pattern on a central portion and an outer side of the trench; Performing source and drain ion implantation into the silicon layers on both sides using the second photoresist pattern as a mask; Removing the second photoresist pattern and performing annealing to form a source and a drain region having a drift region thereunder; Forming a doped polysilicon film on the resulting product up to this step; Patterning the doped polysilicon layer to form a gate on the center and the outside of the trench and simultaneously forming polysilicon spacers on the sidewalls of the trench; Forming an interlayer insulating film on the resultant to cover the remaining gate portions except the gate portion outside the trench, the device isolation layer, and the silicon layer; Forming first and second contact plugs in contact with the source and drain regions, respectively, in place of the interlayer insulating film; And And forming first, second and third metal wires on the interlayer insulating layer, the first and second metal wires contacting the gate and the first and second contact plugs, respectively. The method of claim 5, further comprising performing ion implantation for adjusting the threshold voltage between the trench forming step and the first photoresist pattern forming step. The method of claim 5, wherein the forming of the interlayer insulating film is performed. Depositing a BPSG film to fill the trench; Spin coating an SOG film on the BPSG film, the device isolation film, the silicon layer and the gate; And Polishing the SOG film until the gate portion outside the trench is exposed.