KR20030032295A - Method of forming capacitor of memory device - Google Patents

Method of forming capacitor of memory device Download PDF

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KR20030032295A
KR20030032295A KR1020010064000A KR20010064000A KR20030032295A KR 20030032295 A KR20030032295 A KR 20030032295A KR 1020010064000 A KR1020010064000 A KR 1020010064000A KR 20010064000 A KR20010064000 A KR 20010064000A KR 20030032295 A KR20030032295 A KR 20030032295A
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capacitor
nitride film
forming
spacer
hole
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KR1020010064000A
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Korean (ko)
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KR100772703B1 (en
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채광기
박수영
박원성
이원욱
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to easily perform an etch process for forming a storage node hole and open the storage node hole by decreasing the thickness of a sacrificial oxide layer for forming the capacitor. CONSTITUTION: The sacrificial oxide layer(215) is formed on a substrate(200). The sacrificial oxide layer is selectively etched to form a hole. A nitride layer spacer is formed on the sidewall of the hole. An isotropic etch process is performed on the front surface of the substrate including the nitride layer spacer to form a nitride layer spacer pattern of a roughness type. A polysilicon lower electrode conductive layer is deposited on the front surface of the substrate including the nitride layer spacer to form a lower electrode pattern. A dielectric layer and an upper electrode conductive layer are deposited on the front surface of the substrate including the lower electrode pattern and patterned to form the capacitor.

Description

반도체소자의 캐패시터 제조방법{METHOD OF FORMING CAPACITOR OF MEMORY DEVICE}METHODS OF FORMING CAPACITOR OF MEMORY DEVICE

본 발명은 반도체 집적회로의 제조방법에 관한 것으로, 특히 반도체 소자의 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

반도체 기억 소자들 중 DRAM(Dynamic Random Access Memory)은 집적도가 증가함에 따라 기억정보의 기본단위인 1비트를 기억시키는 메모리 셀의 면적은 작아지고 있다. 그런데 셀의 축소에 비례하여 캐패시터의 면적을 감소 시킬 수는 없는 바, 이는 센싱(sensing) 신호 마진(signal margin), 센싱 속도, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성 등을 위해서는 단위 셀당 일정 이상의 충전용량이 필요하기 때문이다. 따라서 제한된 셀 면적내에 메모리 캐패시터의 용량(C)을 적정값 이상 유지시키기 위한 방법은 C=εAs/d (ε:유전률, As:표면적, d:유전체 두께) 와 같이, 첫째는 유전체 두께(d)를 감소시키는 방법, 둘째는 캐패시터의 유효 표면적(As)을 증가시키는 방법, 셋째는 유전율(ε)이 높은 재료를 사용하는 방법이 고려되어 왔다.As the density of dynamic random access memory (DRAM) of semiconductor memory devices increases, the area of a memory cell that stores one bit, which is a basic unit of memory information, is decreasing. However, it is not possible to reduce the area of the capacitor in proportion to the shrinking of the cell, which is necessary for sensing signal margin, sensing speed, and durability against soft errors caused by α-particles. This is because a certain charging capacity is required per unit cell. Therefore, the method for maintaining the capacity (C) of the memory capacitor in the limited cell area more than the appropriate value is the first dielectric thickness (d), such as C = ε As / d (ε: dielectric constant, As: surface area, d: dielectric thickness) The second method is to increase the effective surface area (As) of the capacitor, and the third method is to use a material having a high dielectric constant (ε).

이 가운데, 캐패시터의 구조를 3차원 구조로 하여 캐패시터의 유효 표면적(As)을 증가시키는 방법은 크게 스택 구조와 컨캐이브 구조로 구분된다.Among these, a method of increasing the effective surface area As of the capacitor by using the capacitor as a three-dimensional structure is largely divided into a stack structure and a convex structure.

도 1은 종래기술에 의한 컨캐이브 캐패시터를 나타내는 단면도이다.1 is a cross-sectional view showing a conventional capacitor capacitor.

반도체기판(100) 상에 층간절연막(105)을 형성한 후, 상기 층간절연막을 관통하여 반도체기판의 활성영역(active region, 도시되어 있지 않음)과 연결되는 콘택홀을 형성한다. 상기 콘택홀을 폴리실리콘, 실리사이드층, 베리어층으로 채워 도전성 플러그(110)를 형성한다. 그 다음 컨캐이브 캐패시터의 스토리지노드를 형성하기 위하여 희생산화막(115)을 형성하고, 상기 플러그 상부를 선택적 식각하여 스토리지노드 홀을 형성한다. 그 후 하부전극이 형성될 도전층을 증착하고, 상기 도전층을 스토리지노드 분리하여 하부전극 패턴(120)을 형성한다. 상기 하부전극 패턴 위로 유전체막(125)과 상부전극 도전층(130)을 증착하고 패터닝하여 컨캐이브 캐패시터를 완성한다.After the interlayer insulating layer 105 is formed on the semiconductor substrate 100, a contact hole is formed through the interlayer insulating layer to be connected to an active region (not shown) of the semiconductor substrate. The contact hole is filled with polysilicon, a silicide layer, and a barrier layer to form a conductive plug 110. Next, a sacrificial oxide film 115 is formed to form a storage node of the concave capacitor, and the upper portion of the plug is selectively etched to form a storage node hole. Thereafter, a conductive layer on which a lower electrode is to be formed is deposited, and the conductive layer is separated from the storage node to form a lower electrode pattern 120. A dielectric capacitor 125 and an upper electrode conductive layer 130 are deposited and patterned on the lower electrode pattern to complete a condenser capacitor.

이 컨캐이브 캐패시터의 용량을 증가시키기 위해서는 희생산화막의 높이를 증가시켜야 하는데, 희생산화막의 두께가 두꺼워질수록 식각의 어려움은 커지고 있다. 또한 감광막과 희생산화막의 높은 식각선택비가 요구되면서 스토리지노드 홀 의 바닥에서의 CD(Critical Dimension)가 작아지거나, 나아가 스토리지노드 홀이 개방이 되지 않는 문제점이 있다.In order to increase the capacity of the concave capacitor, it is necessary to increase the height of the sacrificial oxide layer, and as the thickness of the sacrificial oxide layer becomes thicker, the difficulty of etching increases. In addition, as a high etching selectivity of the photoresist and the sacrificial oxide film is required, the CD (Critical Dimension) at the bottom of the storage node hole is reduced, or the storage node hole is not opened.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 희생산화막의 두께를 크게 증가시키지 않으면서 높은 캐패시터의 용량을 확보할 수 있는 반도체소자 제조방법을 제공하는데 목적이 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of securing a high capacitor capacity without significantly increasing the thickness of the sacrificial oxide film.

도 1은 종래기술에 의한 캐패시터를 나타내는 단면도,1 is a cross-sectional view showing a capacitor according to the prior art,

도 2a은 본 발명에 따른 스토리지노드 홀 형성한 후의 단면도,Figure 2a is a cross-sectional view after forming the storage node hole in accordance with the present invention,

도 2b는 본 발명에 따른 질화막 스페이서를 형성한 후의 단면도,2B is a cross-sectional view after forming the nitride film spacer according to the present invention;

도 2c는 본 발명에 따른 폴리실리콘 하부전극 형성 후의 단면도.Figure 2c is a cross-sectional view after forming the polysilicon lower electrode according to the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

200 : 반도체기판 215 : 희생산화막200: semiconductor substrate 215: sacrificial oxide film

220 : 스토리지노드 홀 225 : 질화막 스페이서220: storage node hole 225: nitride film spacer

상기 목적을 달성하기 위한 본 발명의 반도체소자의 캐패시터 제조방법은, 기판 상에 희생산화막을 형성하는 단계; 상기 희생산화막을 선택적 식각하여 홀을 형성하는 단계; 상기 홀 측벽에 질화막 스페이서를 형성하는 단계; 상기 질화막 스페이서를 포함한 기판 전면에 등방성 식각하여 요철 모양으로 질화막 스페이서 패턴을 형성하는 단계; 상기 질화막 스페이서를 포함하는 기판 전면에 하부전극 도전층을 증착하고 하부전극 패턴 형성하는 단계; 상기 하부전극 패턴을 포함하는 기판전면에 유전체막 및 상부전극 도전층을 증착하고 패터닝하여 캐패시터를 형성하는 단계를 포함한다.Capacitor manufacturing method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a sacrificial oxide film on a substrate; Selectively etching the sacrificial oxide layer to form a hole; Forming a nitride film spacer on the sidewalls of the holes; Forming an nitride film spacer pattern in an uneven shape by isotropic etching on the entire surface of the substrate including the nitride film spacer; Depositing a lower electrode conductive layer on an entire surface of the substrate including the nitride film spacers and forming a lower electrode pattern; And forming a capacitor by depositing and patterning a dielectric film and an upper electrode conductive layer on the entire surface of the substrate including the lower electrode pattern.

본 발명은 캐패시터의 용량을 증가시키기 위하여 희생산화막의 두께를 증가시키지 않고 동일한 두께의 희생산화막에서 높은 정전용량을 얻기 위해서, 희생산화막을 선택적으로 식각하여 스토리지노드 홀을 형성하고, 질화막 스페이서를 형성한 후 세정공정 진행없이 CF4와 O2가스를 사용하여 질화막 스페이서의 측벽이 부분적으로 식각되도록 하여 표면적을 증가시킨다.According to the present invention, in order to obtain a high capacitance in the sacrificial oxide film having the same thickness without increasing the thickness of the sacrificial oxide film in order to increase the capacitance of the capacitor, the sacrificial oxide film is selectively etched to form storage node holes, and nitride spacers are formed. The surface area is increased by partially etching the sidewalls of the nitride film spacer using CF 4 and O 2 gas without performing the post-cleaning process.

상술한 목적, 특징들 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해 질 것이다. 이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일실시예를 상세히 설명한다.The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a은 본 발명에 따른 스토리지노드 홀(220) 형성한 후의 단면도이다.2A is a cross-sectional view after the formation of the storage node hole 220 according to the present invention.

반도체기판(200) 상에 층간절연막(205)을 형성한 후, 상기 층간절연막을 관통하여 반도체기판의 활성영역(active region, 도시되어 있지 않음)과 연결되는 콘택홀을 형성한다. 상기 콘택홀을 폴리실리콘, 실리사이드층, 베리어층으로 채워 도전성 플러그(210)를 형성한다. 그 다음 컨캐이브 캐패시터의 스토리지노드를 형성하기 위하여 희생산화막(215)을 형성하고, 상기 도전성 플러그(210)와 대응되는 상부를 선택적 식각하여 스토리지노드 홀(220)을 형성한다.After the interlayer insulating layer 205 is formed on the semiconductor substrate 200, a contact hole is formed through the interlayer insulating layer to be connected to an active region (not shown) of the semiconductor substrate. The contact hole is filled with polysilicon, a silicide layer, and a barrier layer to form a conductive plug 210. Next, a sacrificial oxide film 215 is formed to form a storage node of the concave capacitor, and a storage node hole 220 is formed by selectively etching an upper portion corresponding to the conductive plug 210.

도 2b는 본 발명에 따른 질화막 스페이서(225)를 형성한 후의 단면도이다.2B is a cross-sectional view after forming the nitride film spacer 225 according to the present invention.

상기 스토리지노드 홀(220)을 형성한 후, 질화막을 100Å 내지 300Å 정도증착하고, CHF3와 O2가스를 사용하여 전면적으로 식각하여 질화막 스페이서(225)를 형성한다. 식각되는 질화막은 50Å 내지 100Å 정도로 한다.After the storage node hole 220 is formed, the nitride film is deposited to about 100 kV to about 300 kV, and the entire surface is etched using CHF 3 and O 2 gas to form the nitride film spacer 225. The nitride film to be etched is about 50 kPa to about 100 kPa.

질화막 식각시의 주 식각가스는 CHF3이며, O2는 불소(F) 라디칼의 활성화를 위하여 첨가된다.In etching the nitride film, the main etching gas is CHF 3 and O 2 is added to activate the fluorine (F) radical.

질화막 식각의 화학 반응식은 다음과 같다.The chemical reaction equation of the nitride etching is as follows.

SiN + CHF3+ O2= SiFx+ N2+ CO +H2 SiN + CHF 3 + O 2 = SiF x + N 2 + CO + H 2

CHF3+ RF 전력(power) = CHF2+ F-CHF 3 + RF power = CHF 2 + F-

식각시 질화막 스페이서 측벽에는 F(플루오린)계가 흡착되게 된다. 질화막 스페이서 표면에 잔류하는 F(플루오린)은 가스비, RF 전력, 압력, 온도로 조절 가능하며, 표면적의 30％의 밀도를 가지게 한다.During etching, the F (fluorine) system is adsorbed on the nitride spacer spacer sidewalls. F (fluorine) remaining on the nitride film spacer surface is adjustable by gas ratio, RF power, pressure and temperature, and has a density of 30% of the surface area.

도 2c는 본 발명에 따른 폴리실리콘 하부전극 형성 후의 단면도이다.2C is a cross-sectional view after the polysilicon bottom electrode is formed according to the present invention.

상기 질화막을 블랑켓 식각하여 스페이서를 형성하고, 식각 후 세정공정을 거치지 않고 다시 CF4와 O2가스를 사용하여 고압의 조건에서 등방성 식각을 실시하면 F(플루오린)계가 흡착되어 있는 곳의 식각 속도가 빠름으로 인해 부분적으로 질화막이 식각이 되어 요철모양의 질화막 스페이서 패턴(225a)이 형성된다.The nitride film is blanket-etched to form a spacer, and after etching, isotropic etching using CF 4 and O 2 gas again without performing a cleaning process is performed to etch the F (fluorine) system where it is adsorbed. Due to the high speed, the nitride film is partially etched to form the uneven nitride spacer pattern 225a.

주 식각가스는 CF4이며, O2는 불소(F) 라디칼의 활성화를 위하여 첨가되며, 화학식은 다음과 같다.The main etching gas is CF 4 , O 2 is added to activate the fluorine (F) radical, the formula is as follows.

SiN + CF4+ O2= SiFx(휘발성) + N2(휘발성) + CO(휘발성)SiN + CF 4 + O 2 = SiF x (volatile) + N 2 (volatile) + CO (volatile)

다음으로 하부전극 도전층으로 폴리실리콘(230)을 증착하면 전체적인 표면적이 증가하므로 캐패시터의 용량이 증가한다.Next, when the polysilicon 230 is deposited as the lower electrode conductive layer, the overall surface area increases, so that the capacity of the capacitor increases.

이후에 도면에는 도시되어 있지 않지만 유전체막과 상부전극 도전층을 형성하고, 패턴화하여 캐패시터를 완성한다.Thereafter, although not shown in the drawings, a dielectric film and an upper electrode conductive layer are formed and patterned to complete the capacitor.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

상기와 같이 이루어진 본 발명은, 캐패시터를 형성하기 위한 희생산화막의 두께를 낮출 수가 있으므로 스토리지노드 홀을 형성하기 위한 식각이 용이해지며 홀이 개방되지 않는 것을 방지하므로 수율을 증가시키는 효과가 있다.According to the present invention made as described above, since the thickness of the sacrificial oxide film for forming the capacitor can be lowered, the etching for forming the storage node hole is easier and the hole is not opened, thereby increasing the yield.

Claims (4)

기판 상에 희생산화막을 형성하는 단계;Forming a sacrificial oxide film on the substrate; 상기 희생산화막을 선택적 식각하여 홀을 형성하는 단계;Selectively etching the sacrificial oxide layer to form a hole; 상기 홀 측벽에 질화막 스페이서를 형성하는 단계;Forming a nitride film spacer on the sidewalls of the holes; 상기 질화막 스페이서를 포함한 기판 전면에 등방성 식각하여 요철 모양으로 질화막 스페이서 패턴을 형성하는 단계;Forming an nitride film spacer pattern in an uneven shape by isotropic etching on the entire surface of the substrate including the nitride film spacer; 상기 질화막 스페이서를 포함하는 기판 전면에 폴리실리콘 하부전극 도전층을 증착하고 하부전극 패턴 형성하는 단계;Depositing a polysilicon bottom electrode conductive layer on an entire surface of the substrate including the nitride film spacer and forming a bottom electrode pattern; 상기 하부전극 패턴을 포함하는 기판 전면에 유전체막 및 상부전극 도전층을 증착하고 패터닝하여 캐패시터를 형성하는 단계Forming a capacitor by depositing and patterning a dielectric film and an upper electrode conductive layer on an entire surface of the substrate including the lower electrode pattern; 를 포함하는 반도체소자의 캐패시터 제조방법.Capacitor manufacturing method of a semiconductor device comprising a. 제 1 항에서,In claim 1, 상기 홀 측벽에 질화막 스페이서를 형성하는 단계는,Forming a nitride film spacer on the sidewall of the hole, 상기 홀을 포함하여 기판 전면에 실리콘 질화막을 증착하는 단계;Depositing a silicon nitride film on the entire surface of the substrate including the hole; 상기 실리콘 질화막을 블랑켓 식각하여 상기 홀 측벽에 스페이서를 형성하는 단계Blanket etching the silicon nitride layer to form a spacer on the sidewalls of the hole 를 포함하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.Capacitor manufacturing method of a semiconductor device comprising a. 제 2 항에 잇어서,According to claim 2, 상기 실리콘 질화막은 100Å 내지 300Å 정도 증착하고,The silicon nitride film is deposited to about 100 ~ 300 Å, 상기 블랑켓 식각은 CHF3와 O2가스를 사용하여 질화막 스페이서를 형성하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.The blanket etching method of manufacturing a capacitor of a semiconductor device, characterized in that to form a nitride film spacer using CHF 3 and O 2 gas. 제 1 항에 있어서,The method of claim 1, 상기 질화막 스페이서 패턴을 위한 등방성 식각은 CF4와 O2를 이용하는 것을 특징으로 하는 반도체소자의 캐패시터 제조방법.Isotropic etching for the nitride film spacer pattern is a capacitor manufacturing method of the semiconductor device, characterized in that using the CF 4 and O 2 .
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KR100712355B1 (en) * 2005-10-24 2007-05-02 동부일렉트로닉스 주식회사 Capacitor for Semiconductor device and the manufacturing method thereof
KR100975909B1 (en) * 2008-11-12 2010-08-13 장공순 mold and method for manufacturing the custom made insole by using the mold thereof

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KR950021583A (en) * 1993-12-30 1995-07-26 김주용 Method of forming charge storage electrode of capacitor
KR0171925B1 (en) * 1994-12-30 1999-03-30 김주용 Method of manufacturing charge-storing electrode of capacitor
KR19980058655A (en) * 1996-12-30 1998-10-07 손욱 Fluorescence Display Exhaust System
KR100427540B1 (en) * 1997-06-25 2004-07-19 주식회사 하이닉스반도체 Method of forming capacitor of semiconductor device for improving capacitance

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KR100712355B1 (en) * 2005-10-24 2007-05-02 동부일렉트로닉스 주식회사 Capacitor for Semiconductor device and the manufacturing method thereof
KR100975909B1 (en) * 2008-11-12 2010-08-13 장공순 mold and method for manufacturing the custom made insole by using the mold thereof

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