KR20030031254A - Semiconductor memory device including metal layer for relocating pad - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a metal layer to realign a pad is provided to embody various layouts, and to improve transmit characteristic of signals by changing resistance and capacitance of the layouts. CONSTITUTION: A semiconductor memory device is disposed on a metal layer for interconnection. The metal layer for interconnection includes the first metal line, the second metal line. Capacitance between the first and second metal line is increased by realigning the first and second metal line.

Description

Semiconductor memory device including metal layer for relocating pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device comprising a pad repositioning metal layer for repositioning pads.

In a conventional semiconductor memory device, a pad is disposed in a metal layer for wiring. That is, there is no separate metal layer for pad repositioning for repositioning the pads. Therefore, the conventional semiconductor memory device has a problem that the area of the semiconductor memory device must be large due to the size of the pad, and it is difficult for all the wirings to be disposed on the wiring metal layer.

In addition, there is a problem that it is difficult to arrange a metal option that occupies a large area in the wiring metal layer. Here, the metal option refers to a structure that allows the connection or disconnection of devices prepared in advance to improve the operation characteristics of the circuit.

Accordingly, an aspect of the present invention is to provide a semiconductor memory device including a pad repositioning metal layer capable of implementing various layouts.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

FIG. 1 is a diagram for comparing sizes of widths of a power line and a signal line of a TTL level included in a pad repositioning metal layer of a semiconductor memory device according to example embodiments.

2 is a diagram illustrating a detection structure included in a pad repositioning metal layer of a semiconductor memory device according to an embodiment of the present invention.

3 is a diagram illustrating that a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is shielded by a power supply line.

4 is a diagram illustrating that a length of a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is changed as a pad is changed.

FIG. 5 is a diagram illustrating a method in which a length of a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is extended.

FIG. 6 is a diagram illustrating a layout when a power line and a TTL level signal line included in a pad layout metal layer of a semiconductor memory device are connected to a pad.

FIG. 7 is a diagram illustrating a layout of changing a capacitance value of a TTL level signal line by connecting a metal option to a TTL level signal line included in a pad repositioning metal layer of a semiconductor memory device according to an exemplary embodiment of the present invention. .

FIG. 8 is a diagram illustrating changing a resistance value of a signal line of a TTL level by connecting a metal option to a signal line of a TTL level included in a pad repositioning metal layer of a semiconductor memory device according to an embodiment of the present disclosure.

FIG. 9 is a diagram illustrating a layout in which a power line or a TTL level signal line included in a pad repositioning metal layer of a semiconductor memory device is disposed to avoid a fuse box.

FIG. 10 is a diagram illustrating a layout for increasing capacitance values between metal lines included in a pad repositioning metal layer of a semiconductor memory device according to example embodiments.

FIG. 11A shows a metal option disposed in a metal layer for wiring. FIG.

FIG. 11B illustrates a metal option disposed in a pad repositioning metal layer. FIG.

12A is a cross-sectional view showing an embodiment of a waveguide using a metal layer for pad repositioning in the semiconductor memory device of the present invention.

12B is a cross-sectional view showing another embodiment of the waveguide using the metal layer for pad repositioning in the semiconductor memory device of the present invention.

12C is a cross-sectional view showing still another embodiment of the waveguide using the metal layer for pad repositioning in the semiconductor memory device of the present invention.

FIG. 13 is a diagram illustrating that a metal wire included in a pad repositioning metal layer of the semiconductor memory device performs a function of a filter.

FIG. 14 is a diagram illustrating a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device of the present invention arranged to perform an inductor function.

FIG. 15 is a diagram illustrating a layout including metal wires capable of changing capacitance values, metal wires capable of changing resistance values, and metal wires performing inductor functions shown in FIGS. 7, 8, and 14, respectively.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a metal layer for wiring. The semiconductor memory device of the present invention is disposed on the wiring metal layer, and includes a pad repositioning metal layer for changing a pad position, a signal line having a TTL level included in the pad repositioning metal layer, and having a predetermined width; And a power line included in the pad repositioning metal layer and having a width wider than the width of the TTL level signal line.

According to a preferred embodiment, the pad repositioning metal layer further comprises a detection structure for testing a TTL level signal line included in the wiring metal layer, wherein the power line is disposed between the TTL level signal lines. do.

According to a preferred embodiment, the length of the signal line of the TTL level changes according to the position of the pad, and the pad and the signal line of the TTL level are smoothly connected.

According to a preferred embodiment, the capacitance of the signal line of the TTL level can be changed by selectively connecting the metal option to the signal line of the TTL level.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a metal layer for wiring. The semiconductor memory device of the present invention is disposed on the wiring metal layer, and includes a pad repositioning metal layer for changing a pad position, a first metal wire included in the pad repositioning metal layer, and the pad repositioning metal layer. A second metal wire is included, and the capacitance value between the first metal wire and the second metal wire is increased by using the arrangement between the first metal wire and the second metal wire.

According to a preferred embodiment, the first metal wire and the second metal wire are TTL level signal lines.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a metal layer for wiring. The semiconductor memory device of the present invention includes a TTL level signal line included in the wiring metal layer, a metal option for connecting to the TTL level signal line, and a pad repositioning metal layer for changing a pad position. The pad repositioning metal layer includes the metal option and is disposed on the wiring metal layer.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a metal layer for wiring. The semiconductor memory device of the present invention is disposed on the wiring metal layer, and includes a pad repositioning metal layer for changing a pad position and a signal line included in the wiring metal line layer, wherein the pad repositioning metal layer is the signal line. Characterized in that it performs the function of a waveguide for guiding the signal transmitted through.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a first wiring metal layer and a second wiring metal layer disposed under the first wiring metal layer. A semiconductor memory device of the present invention is disposed on the first wiring metal layer, and includes a pad repositioning metal layer for changing a pad position, a signal line included in the first wiring metal layer, and the pad repositioning metal. The layer and the second wiring metal layer may function as a wave guide for guiding a signal transmitted through the signal line.

In order to achieve the above technical problem, the semiconductor memory device of the present invention relates to a semiconductor memory device including a metal layer for wiring. The semiconductor memory device of the present invention is disposed on the wiring metal layer, and includes a pad repositioning metal layer for changing a pad position, and a signal line having a TTL level included in the pad repositioning metal layer. The signal line is formed spirally to perform the function of the inductor.

Since the semiconductor memory device of the present invention includes a pad repositioning metal layer having a sufficient margin, various layouts may be possible. By the layout described above, the signal transfer characteristics can be improved by changing the values of the resistance and the capacitance. In addition, circuits and waveguides using inductances implemented using metal wires in pad repositioning metal layers are suitable for systems operating at high speeds.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 1 is a diagram for comparing sizes of widths of a power line and a signal line of a TTL level included in a pad repositioning metal layer of a semiconductor memory device according to example embodiments. The power supply line and the TTL level signal line are metal lines included in the pad repositioning metal layer of the semiconductor memory device of the present invention.

Referring to FIG. 1, the width of the power supply line PL is wider than the width of the signal line TTLL of the TTL level. The width of the power supply line PL is large to reduce the resistive voltage drop, and the width of the signal line TTLL of the TTL level is small to reduce the input capacitance. Here, the power supply line PL transmits a current signal, and the TTL level signal line TTLL transmits a voltage signal. The signal line TTLL of the TTL level may be, for example, a data input / output line (DQ line).

2 is a diagram illustrating a detection structure included in a pad repositioning metal layer of a semiconductor memory device according to an embodiment of the present invention. Conventional semiconductor memory devices do not have a separate structure for probing, but since the metal layer for pad repositioning included in the semiconductor memory device of the present invention has a sufficient free area, the detection structure may be disposed. Referring to FIG. 2, the semiconductor memory device of the present invention includes a detection structure PS in a pad repositioning metal layer to test a TTL level signal line TTLL included in a wiring metal layer through a VIA (hole). It is easy. The wiring metal layer is disposed under the pad repositioning metal layer.

3 is a diagram illustrating that a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is shielded by a power supply line. Since the voltage signal flowing through the TTL level signal line TTLL is transmitted at a high speed, the voltage signal transmitted through the TTL level signal line TTLL is influenced by mutual inductance between the TTL level signal lines TTLL. I / O speed may vary. Therefore, when shielding the TTL level signal line TTLL with the power line PL whose voltage is kept fairly stable, the influence between neighboring TTL level signal lines TTLL is reduced, thereby reducing the TTL level signal line ( The value of the inductance of the TTLL may remain the same.

4 is a diagram illustrating that a length of a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is changed as a pad is changed. FIG. 5 is a diagram illustrating a method in which a length of a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device is extended.

In order to facilitate packaging, the position of the pad can be changed, and the length of the signal line of the TTL level varies according to the position of the pad. Referring to FIG. 4, OP represents a previous pad and NP represents a new pad whose position has been changed. Depending on the position of the new pad NP, the length of the TTL level is shortened (SP) or longer (LP). However, since the line load applied to the signal line TTLL of the TTL level should be the same, the length SP of the signal line TTLL of the short TTL level should be compensated. That is, the length SP of the signal line of short TTL level should extend as shown in FIG. The length of the power supply line PL also extends to shield the signal line TTLL of TTL level.

FIG. 6 is a diagram illustrating a layout when a power line and a TTL level signal line included in a pad layout metal layer of a semiconductor memory device are connected to a pad. Referring to FIG. 6, in the case of the power line PL, the width of the power line PL is larger than the width of the pad in order to reduce the resistive voltage drop and reduce the electric shock. However, in the case of the TTL level signal line TTLL, the width of the TTL level signal line TTLL is smaller than the width of the pad. Therefore, in order to reduce the electric shock by smoothing the impedance change, when connecting the pad and the signal line TTLL of the TTL level, the signal line TTLL of the TTL level should include a portion CON that is gently connected. The signal line TTLL of the TTL level may be safe against electrostatic discharge (ESD) by including the connection portion CON. In addition, attenuation or reflection of a signal transmitted through the TTL level signal line TTLL may also be prevented.

FIG. 7 is a diagram illustrating a layout of changing a capacitance value of a signal line of a TTL level by connecting a metal option to a signal line of a TTL level included in a pad repositioning metal layer of a semiconductor memory device according to an embodiment of the present disclosure. . OP and NP shown in FIG. 7 represent the previous pad and the new pad after the pad positions are changed, respectively. Referring to FIG. 7, the capacitances of the TTL level signal line TTLL may be changed to a desired value by selectively connecting the metal options M01 and MO2 to the TTL level signal line TTLL. 6 illustrates a layout in which only the metal option MO1 is connected. The metal options MO1, MO2 can be quickly created or removed using a forced ion beam (FIB), so that the desired capacitance value can be easily obtained.

FIG. 8 is a diagram illustrating changing a resistance value of a signal line of a TTL level by connecting a metal option to a signal line of a TTL level included in a pad repositioning metal layer of a semiconductor memory device according to an embodiment of the present disclosure. OP and NP shown in FIG. 8 represent the previous pad and the new pad after the pad positions are changed, respectively. By selectively connecting the metal options MO3, M04, and MO5 to the TTL level signal line TTLL, the resistance value of the TTL level signal line TTLL may be changed to a desired value. In addition, the capacitance of the signal line TTLL of the TTL level may be changed by the metal options MO3, MO4, and MO5.

The metal options MO1, MO2, MO3, MO4, and MO5 shown in FIGS. 7 and 8 can be quickly generated or removed using a forced ion beam (FIB), thus providing a desired capacitance value or resistance value. This can be easily obtained.

FIG. 9 is a diagram illustrating a layout in which a power line or a signal line having a TTL level is disposed in a semiconductor memory device according to an embodiment of the present invention, avoiding a fuse box. TTL level signal and power lines (TTLL, PL) contained in the pad repositioning metal layer should be wired away from the column decoder fuse box and the row decoder fuse box as shown in FIG. 9 for fuse cutting. . The column decoder fuse box and the row decoder fuse box are disposed under the metal layer for wiring.

FIG. 10 is a diagram illustrating a layout for increasing capacitance values between metal lines included in a pad repositioning metal layer of a semiconductor memory device according to example embodiments. Although most signal lines avoid capacitance between signal lines, there are cases where capacitance between signal lines is used for various operations of a circuit. In this case, as shown in FIG. 10, the capacitance of signals transmitted through the metal lines ML1 and ML2 may be increased by using the arrangement of the metal lines ML1 and ML2 included in the pad repositioning metal layer. Can be. In addition, since the semiconductor memory device of the present invention including the pad repositioning metal layer has a small area burden for wiring, a larger capacitance value can be obtained than the conventional semiconductor memory device. For example, the metal lines ML1 and ML2 may be signal lines TTLL or power lines PL having a TTL level.

FIG. 11A illustrates a metal option disposed on a metal layer for wiring, and FIG. 11B illustrates a metal option disposed on a metal layer for pad repositioning. 11A and 11B, metal wires ML1 to ML4 of the metal layer for wiring are disposed to avoid the metal option MO6. However, when the metal option MO6 is disposed on the pad repositioning metal layer, the metal wires ML1 to ML4 of the wiring metal layer are not limited by the metal option MO6, so that the wiring connection in the metal layer for wiring becomes easy. Can be. In addition, since the semiconductor memory device of the present invention includes a pad layer metal layer having a sufficient margin, the resistance value may be decreased by increasing the width of the metal option MO6. The metal option MO6 may be connected to the metal line ML2 of the metal layer for wiring through VIA.

12A, 12B and 12C are sectional views showing an embodiment of the waveguide using the metal layer for pad repositioning in the semiconductor memory device of the present invention. Waveguides can transmit signals with little loss of signal, and can easily implement impedance matching. Waveguides are also suitable for high frequency operation.

The dotted line interior shown in FIG. 12A functions as a waveguide. That is, the pad repositioning metal layer ML_PM functions as a waveguide for guiding a signal transmitted through the metal line ML_WM1 of the first wiring metal layer. The metal lines ML_WM21 and ML_WM22 are included in the second wiring metal layer disposed under the first wiring metal layer, and are signal lines for transmitting signals.

Referring to FIG. 12B, the pad layout metal layer and the second wiring metal layer ML_PM and ML_WM23 guide signals transmitted through the metal line ML_WM1 of the first wiring metal layer. Although not shown in FIG. 12B, the voltages of the pad layer metal layer and the second wiring metal layer ML_PM and ML_WM23 are designed to be the same.

Referring to FIG. 12C, the pad layer metal layer ML_PM, the metal layers M1 and M2 deposited through the VIA, the first wiring metal layer ML_WM12 and the second wiring metal layer ML_WM23 may be a first layer. The signal transmitted through the metal line ML_WM11 of the wiring metal layer is guided.

FIG. 13 is a diagram illustrating that a metal wire included in a pad repositioning metal layer of the semiconductor memory device performs a function of a filter. Referring to FIG. 13, the middle of the metal line PM_F of the pad repositioning metal layer is concave, and serves to filter the signal. Such a metal wire has a difficulty in forming in a conventional metal layer for wiring, and can effectively remove noise of a signal.

FIG. 14 is a diagram illustrating a signal line having a TTL level included in a pad repositioning metal layer of a semiconductor memory device of the present invention arranged to perform an inductor function. Referring to FIG. 14, the shape of the TTL level signal line TTLL_PM of the pad layer metal layer has a spiral shape to serve as an inductor, and the TTL level signal line serving as the inductor may be used for pad repositioning with sufficient free area. It can be easily disposed on the metal layer. Thus, the desired inductance value can be obtained. The TTL level signal line TTLL_PM of the pad layout metal layer may be connected to the TTL level signal line TTL_WM of the wiring metal layer through VIA.

FIG. 15 is a diagram illustrating a layout including metal wires capable of changing capacitance values, metal wires capable of changing resistance values, and metal wires performing inductor functions shown in FIGS. 7, 8, and 14, respectively. Referring to FIG. 15, for convenience of description herein, the pad repositioning metal layer may include a metal wire PM_C that may change capacitance value, a metal wire PM_R that may change resistance value, and an inductor function. The metal line PM_I to perform is shown as simple display means, respectively. Since the layout of the above configuration is configured in the pad repositioning metal layer, which is the uppermost metal layer, the impedance can be easily adjusted through repetitive work. Therefore, impedance matching to reduce skew of a signal transmitted through the pad can be easily performed.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Since the semiconductor memory device of the present invention includes a pad repositioning metal layer having a sufficient margin, various layouts may be possible. By the layout described above, the signal transfer characteristics can be improved by changing the values of the resistance and the capacitance. In addition, circuits and waveguides using inductances implemented using metal wires in pad repositioning metal layers are suitable for systems operating at high speeds.

Claims (15)

In a semiconductor memory device comprising a metal layer for wiring, A pad repositioning metal layer disposed on the wiring metal layer for changing a pad position; A signal line of a TTL level included in the pad repositioning metal layer and having a predetermined width; And And a power line included in the pad repositioning metal layer, the power line having a width wider than the width of the TTL level signal line. The method of claim 1, And a detection structure included in the pad repositioning metal layer, for detecting a signal line having a TTL level included in the wiring metal layer. The method of claim 2, And the power supply line is arranged between the signal lines of the TTL level. The method of claim 3, And the length of the signal line of the TTL level varies according to the position of the pad. The method of claim 4, wherein And the pad and the TTL level signal line are gently connected. The method of claim 5, And selectively connecting a metal option to the signal line of the TTL level to change the capacitance value of the signal line of the TTL level. The method of claim 5, And selectively connecting a metal option to the signal line of the TTL level to change the resistance of the signal line of the TTL level. The method of claim 5, And the TTL level signal line and the power line are arranged to avoid a fuse box disposed under the wiring metal layer. In a semiconductor memory device comprising a metal layer for wiring, A pad repositioning metal layer disposed on the wiring metal layer for changing a pad position; A first metal wire included in the pad repositioning metal layer; And And a second metal wire included in the pad repositioning metal layer, And a capacitance value between the first metal line and the second metal line is increased by using the arrangement between the first metal line and the second metal line. The method of claim 9, And the first metal line and the second metal line are TTL level signal lines. In a semiconductor memory device comprising a metal layer for wiring, A signal line having a TTL level included in the wiring metal layer; A metal option for connecting to the TTL level signal line; And A metal layer for pad repositioning to change the position of the pad, And the pad repositioning metal layer includes the metal option and is disposed on the wiring metal layer. In a semiconductor memory device comprising a metal layer for wiring, A pad repositioning metal layer disposed on the wiring metal layer for changing a pad position; And And a signal line included in the wiring metal line layer, And the pad repositioning metal layer functions as a waveguide for guiding a signal transmitted through the signal line. A semiconductor memory device comprising a first wiring metal layer and a second wiring metal layer disposed under the first wiring metal layer. A pad repositioning metal layer disposed on the first wiring metal layer and configured to change a position of the pad; And And a signal line included in the first wiring metal layer, And the pad repositioning metal layer and the second wiring metal layer function as a waveguide for guiding a signal transmitted through the signal line. The method of claim 13, And a via metal layer connecting the pad repositioning metal layer, the first wiring metal layer, and the second wiring metal layer. And the pad repositioning metal layer, the first wiring metal layer, the second wiring metal layer, and the via metal layer function as a waveguide for guiding a signal transmitted through the signal line. In a semiconductor memory device comprising a metal layer for wiring, A pad repositioning metal layer disposed on the wiring metal layer for changing a pad position; And And a signal line having a TTL level included in the pad repositioning metal layer. And the signal line of the TTL level is formed in a spiral shape to perform a function of an inductor.