KR20030030404A - The multiplier circuit - Google Patents

Abstract

PURPOSE: A multiplier circuit is provided to remove unnecessary output bits from a conventional multiplication circuit so that it can reduce a delay time from a data input from a data output, and a consumption power. CONSTITUTION: The circuit comprises a multiplier(401), an overflow checker(402) and a selector(403). The multiplier(401) receives N bit data and M bit data, and multiplies the N bit data by the M bit data while limiting the multiplication output within L bits where L is not over N + M. The overflow checker(402) checks whether there occurs an overflow at the output from the multiplier(401) by referring to the carry data of (N + M) - L. The selector(403) outputs the largest number which can be expressed with the L bits if there occurs an overflow at the output from the multiplier(401), and, otherwise, outputs the multiplication result with the L bits.

Description

The multiplier circuit

The present invention relates to a multiplier circuit having a limited size output. More specifically, when multiplying N bits × M bits, if it is certain that the result is within a range of (N + M) bits, for example, within L bits, do not return the result to (N + M) bits. It is a multiplier circuit that can reduce the area of hardware required for implementation and the delay between input and output by only finding bits, thus reducing power consumption.

FIG. 1 is a block diagram of a conventional multiplier. The block diagram of the multiplier multiplies the number of N bits and the number of M bits to obtain an output of L bits. Where L is a natural number not greater than N + M.

As shown in FIG. 1, a typical carry-saved multiplier 101 multiplies the number of N bits by the number of M bits and outputs the result of N + M bits, and the saturator 102 outputs the number of N + M bits. It converts the number of L bits.

That is, the saturator 102 makes the final output the largest number that can be represented by L bits if the number of N + M bits is out of the range that can be represented by L bits. Otherwise, the saturator 102 has a carry-saved multiplier ( The output of 101) is exported to the final output as it is.

FIG. 2 is a detailed block diagram of the general carry-saved multiplier shown in FIG. 1, in which two inputs are 9 bits and 5 bits, respectively. 3 shows a definition of a symbol of the multiplier shown in FIG. 2, and FIG. 4 is a detailed block diagram of the saturator shown in FIG. 1.

In the first input number, X8 means the highest digit bit of the number, and X0 means the lowest digit bit. In the second input number, Y4 means the highest digit bit of the number and Y0 means the lowest digit bit.

P is the result of the typical carry-saved multiplier 101 shown in FIG.

Equation 1 holds, and each term of the final result of Equation 1 corresponds in turn to 201, 202, 203, 204, and 205 shown in FIG. .

If you add partial products (201) to (205) in turn, P comes out. First, the parts added to (201) and (202) are semi-adders. The half adder is used to add a vertically overlapping digit portion of the 201 and 202, and since the input is only two, the half adder is used instead of the full adder.

On the other hand, from the next time (202) and (203) was added, the full adder was used because when adding (201) and (202) to add the vertically overlapping digits of (202) and (203) Because the carry output also needs to be added together.

Similarly, after adding up to the vertically overlapping digits of (204) and (205), the task of adding the sum output and the carry output from the full adder below (205) by one digit is left. The difference from adding () to (205) is that you don't need to pull the carry output except for the largest digit.

Thus, the vector merge adder 206 doing the work may use a full adder, but may use other more complex implementations, including a carry-lookahead approach, to speed up computation.

Unlike multipliers that carry the carry output to the left when adding the partial products 201 to 205 to each other, the carry-save multiplier 101 passes the carry output diagonally when adding the partial products together so that the critical path is from above. The vector merge adder 206 is passed. This has the advantage of enabling the calculation speed of the entire multiplier by adjusting the calculation speed of the vector merge adder 206.

The multiplier shown in Fig. 2 is an example of the case where the input is a specific number of bits, but in general, the hardware element necessary for the implementation of the multiplier outputting the number of N + M bits by multiplying the number of N bits with the number of M bits. Is shown below.

AND gate: N × M

Half adder: (N-1)

Full adder: (N-1) × (M-2)

Vector adder: (N-1) bits.

In this case, the size of the required hardware may vary according to the implementation method, and as the number of bits increases, the size of the hardware increases.

In the multiplier of FIG. 2, the critical path passes in order through one AND gate, one half adder, three full adders, and one vector adder to obtain X1Y0. In the general case, the critical path passes through the following elements:

1 AND gate

-1 half adder

-Full adder (M-2)

-1 vector adder

If the result 209 of the multiplier of FIG. 2 is always within the 10-bit representation range, for example, using 14 to extract the 14-bit result and discarding the first 4 bits results in 210 of FIG. This results in inefficiency.

Thus, the present invention eliminates the needless 210 if there is a guarantee that the result of the multiplier of FIG. 2 does not fall outside the 10-bit representation range, and instead indicates that the multiplication result is outside the 10-bit representation range. Provides a multiplier circuit with an overflow handler.

That is, the present invention has been made to solve the above problems, and an object of the present invention is to remove a portion for calculating unnecessary output bits in a multiplier, thereby reducing hardware area, delay time from input to output, and power consumption. To provide a multiplier circuit.

As a technical idea for achieving the above object of the present invention

In a multiplier circuit which multiplies the number of N bits by the number of M bits and outputs the number of L (≤N + M) bits,

A multiplier that receives an input of N bits and M bits and has an output of limited size;

An overflow determiner which receives (N + M) -L carry outputs from the multiplier and determines whether an overflow occurs;

A multiplier comprising a selector for selecting the largest number that can be represented by L bits and outputting the final output or output L bits as the final output according to whether or not the overflow judging has occurred; Present the circuit.

FIG. 1 is a block diagram of a conventional multiplier and shows a block diagram of a multiplier multiplying the number of N bits with the number of M bits to obtain an output of L bits.

FIG. 2 is a detailed block diagram of the general carry-saved multiplier shown in FIG. 1.

FIG. 3 shows definitions of symbols of the multiplier shown in FIG. 2.

4 is a detailed block diagram of the saturator shown in FIG. 1.

5 is a block diagram of a multiplier circuit according to the present invention.

FIG. 6 is a detailed block diagram of the multiplier circuit shown in FIG. 5.

FIG. 7 is a detailed block diagram of the overflow determiner illustrated in FIG. 5.

8 is a block diagram of an MPEG-4 image texture decoder according to the present invention.

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

5 is a block diagram of a multiplier circuit according to the present invention.

Referring to FIG. 5, a multiplier 401 having an output of limited size, an overflow determiner 402, and a selector 403 are configured.

The multiplier 401 having the output of the limited size is a multiplier that receives inputs of N bits and M bits, respectively, and outputs their products. The multiplier 401 of FIG. It is different from the general carry-saved multiplier 101.

For input A and input B, for example, 9 bits and 5 bits, respectively, 14 bits are usually needed to represent the output result, but we know in advance that the result can always be represented by 10 bits. The part corresponding to the 14th to 11th bits is removed. However, the relationship of the following equation 2 should be satisfied here.

At this time, MAX (M, N) becomes M if M> N, otherwise N. In Equation 2, L should be smaller than M + N because it may result in a saving in the carry-saved multiplier 101 of FIG.

If L = M + N, the result is the same multiplier as the carry-saved multiplier 101 of FIG. 1 and the multiplier 401 having the limited size output of FIG. In addition, it should always be satisfied that L should not be smaller than MAX (M, N) in Equation 2.

If L is smaller than MAX (M, N), then MAX (M, N) is larger than necessary. For example, if two inputs of a multiplier contain 9 bits (M) and 5 bits (N), and you can say that the output is always within 7 bits (L), then the 9-bit input must be expressible in 7 bits. do. After all, L should not be less than MAX (M, N).

On the other hand, when multiplication is completed in the multiplier 401 having a limited size output, (N + M) -L carry outputs are output, which are passed to the overflow determiner 402 so that the output of the multiplier 401 overflows. Determine whether or not. Overflow means that the output of the multiplier 401 with the output of limited size has become a value that cannot be represented by L bits alone.

Of course, the present invention should be used in situations where it is certain that the output of multiplier 401 with a limited size output can be represented in L bits, but either or both inputs of multiplier 401 with limited size output We also consider a case where an error occurs and the output exceeds the L bit representation range. This is because limiting the output of the multiplier 401 having a limited size output to the L bit representation range is more suitable for the purpose of using the multiplier.

The overflow determiner 402 and the selector 403 are generated because the multiplier 401 removes portions corresponding to unused bits of the output. As a result, the reduced hardware area in the multiplier 401 with the limited size output may appear to be offset by the newly introduced overflow determiner 402 and the selector 403, but in fact it is not.

This is because the saturator 102 of FIG. 1 is removed instead of the overflow determiner 402 and the selector 403. In addition, the hardware area of the saturator 102 in the existing multiplier is exactly the sum of the hardware area of the overflow determiner 402 and the selector 403 of the multiplier proposed in the present invention.

Accordingly, it is possible to determine whether the area of the multiplier according to the present invention is reduced by purely comparing the area of the carry-saved multiplier 101 of FIG. 1 and the multiplier 401 having the limited size output of FIG.

That is, when the overflow determiner 402 determines that an overflow has occurred, the selector 403 selects the largest number that can be represented by the L bit and sends it to the final output. The largest number that can be represented by L bits is As a binary number, L is 1 consecutive. On the other hand, when the overflow determiner 402 determines that no overflow occurs, the selector 403 outputs the output L bit of the multiplier 401 having the output of the limited size as it is to the final output.

FIG. 6 is a multiplier removing portions 210 for bits that will not be used in an output of the multiplier of FIG. 2, and receives a number of 9 bits and a number of 5 bits, and always outputs a number within a 10-bit representation range. Example of the case. 6 is an improvement of FIG. 2 as follows.

First, there are six AND gates.

Second, three full adders were reduced.

Third, the width of the vector merge adder has been reduced from 8 bits to 5 bits.

The third of these, in particular, complicates the implementation of the vector-adder, allowing more hardware area to be reduced in order to reduce the output delay of the overall multiplier.

Carry output of the leftmost full adder of the partial product 503 bottom full adder row of FIG. 6, carry output of the leftmost full adder of the bottom full adder row 504 The carry outputs of the vector merge adder are all connected to the inputs of the overflow determiner 402 of FIG. 5. The number of these signals, 4, is equal to the sum of the bits of the two inputs, minus 14, the number of bits of the limited output.

FIG. 7 is a detailed block diagram of the overflow determiner illustrated in FIG. 5.

The overflow determiner illustrated in FIG. 7 is an input received from the multiplier 401 having the limited size output of FIG. 5 to determine whether the output of the multiplier 401 is a meaningful value, that is, a value within a 10-bit representation range. To judge.

The way to judge it is to look at the result of ORing all the signals received. Because if the overflow determiner 402 has a non-zero value in any of the input signals, it must have 11th to 14th bits in the output of the multiplier 401 having a limited size output. This means that you can represent the result.

The multiplier of FIG. 6 is an example of the case where the input is a specific number of bits, but in general, that is necessary for the implementation of a multiplier that outputs the number of L (≤N + M) bits by multiplying the number of N bits with the number of M bits. The hardware elements are as follows.

-Vector adder: (L-M) bit

In this case, the size of the required hardware may vary according to an implementation method, and as the number of bits increases, the size of the hardware also increases.

However, MAX (A, B) means the lesser of A and B. In the above equations for hardware elements, the term after '-' represents a reduced number in the multiplier according to the present invention compared to the conventional multiplier of FIG. 2.

In the multiplier of FIG. 6, the critical path passes through an AND gate, a half adder, three full adders, and a vector combine adder carry output in order to obtain X1Y0. In the general case, the critical path passes through the following elements:

1 AND gate

-1 half adder

-Full adder (M-2)

-1 vector adder

The difference between the critical paths shown in FIGS. 2 and 6 is the width of the vector merge adder. How fast the multiplier according to the present invention depends on how the width of the vector merge adder is reduced due to the limited number of output bits for the implementation method of the same vector merge adder.

FIG. 8 is a block diagram of an MPEG-4 image texture decoder according to the present invention, and when applied to a digital image decoding device, in particular, an MPEG-4 image texture decoding device, many advantages can be seen.

Referring to FIG. 8, a variable length decoder (701), an inverse scan (702), an inverse AC / DC prediction (703), an inverse quantization (704) And an inverse DCT (705) and a motion compensation (706).

The present invention can be applied to the AD / DC coefficient compensator 703 and the inverse quantizer 704 of FIG. In order to predict the AC coefficient in the AD / DC coefficient compensator 703, the AC coefficient received from the inverse scanner 702 is multiplied by the quantization coefficient corresponding to the prediction direction. The absolute value of the coefficient can be represented by 10 bits, and the quantization coefficient can be represented by 5 bits.

However, the product of the two should be represented by 10 bits. In this case, in the case of N = 10, M = 5, and L = 10 in FIG. 5, the AND gates are reduced from 50 to 40 by Equation 3, and the half adders are reduced to 9 by Equation 4, compared to the conventional multipliers. 9 equals, the full adder is reduced from 27 to 21 by Equation 5, and the width of the vector merge adder is reduced from 9 to 5 bits by Equation 6.

Here, the hardware area of the vector adder can be reduced by up to one-tenth depending on the situation according to the present invention.

Suppose that the input-output delay time of the vector-adder should be less than or equal to 3 ns in order to make the output delay time of the entire multiplier less than or equal to a certain value without applying the present invention.

In a semiconductor manufacturing process, a 9-bit vector adder in an ripple-carry form has an area of 58, and a delay time of 4.51 ns. Since the vector-adder's delay must be 3ns or less, the carry-look-ahead method with a much larger area should be used.

However, when the present invention is applied, the width of the vector merge adder is reduced from 9 bits to 5 bits. If the 5-bit vector merge adder is implemented in the form of ripple-carrier under the same process and under the same conditions, the area is 32 and the delay time is 2.67 ns. Since the time is 3ns or less, the ripple-carry vector adder can be used. As a result, by applying the present invention, the area of the vector adder is reduced from 347 to 32 to about 10.8 / 1.

That is, the inverse quantizer 704 multiplies the 11-bit input by 5 bits of the quantization coefficient when inverse quantization. As a result, the inverse quantizer 704 must be 11 bits, so that the present invention can be applied to reduce hardware area.

As described above, according to the multiplier circuit having a limited size output according to the present invention, there are advantages as follows.

First, according to the present invention, the hardware area, the delay from the input to the output, and the power consumption can be reduced by removing a portion for calculating unnecessary output bits in the multiplier.

Second, when the general multiplier structure shown in FIG. 2 is used without applying the present invention, the delay time is increased from the input to the output and the delay time may need to be reduced through a more complicated implementation method such as the Booth algorithm. lets do it. In this case, considering that the present invention can also reduce the delay time by the carry-save multiplier as shown in FIG. 6, hardware resources can be further saved.

Third, the application of the present invention reduces the width of the vector adder, so that the hardware area is always reduced if its implementation is not changed, and furthermore, when it is necessary to complicate the method of implementing the vector merge adder to reduce the delay time of the multiplier. However, the reduction of the width of the vector adder by applying the present invention eliminates the need to further complicate the implementation method.

Claims (5)

In a multiplier circuit which multiplies the number of N bits by the number of M bits and outputs the number of L (≤N + M) bits, A multiplier having an input of N bits and M bits and having an output of limited size; An overflow determiner which receives (N + M) -L carry outputs from the multiplier and determines whether an overflow occurs; A multiplier comprising a selector for selecting the largest number that can be represented by L bits and outputting the final output or output L bits as the final output according to whether the overflow determiner has overflowed; Circuit. The multiplier circuit of claim 1 wherein the multiplier takes the form of a carry-save. The multiplier circuit of claim 1 or 2, wherein the following equation is satisfied to implement a carry-save type multiplier that outputs the number of L (≤N + M) bits. Vector Merge Adder: (L-M) Bit The method according to claim 1, wherein when the overflow determiner determines that an overflow has occurred, the selector is the largest number that can be represented by L bits. Selector and output to final output. The multiplier circuit of claim 1, wherein when the output of the multiplier is determined to be out of the L bit representation range by using the overflow determiner and the selector, the multiplier circuit replaces the final output with the maximum number that can be represented by the L bit.