KR20030030055A - Non volatile memory device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a method of fabricating the same are provided to realize high device integration by forming the selection gate at a sidewall of the memory gate in the shape of a spacer. CONSTITUTION: A nonvolatile memory device includes a semiconductor substrate, and a memory gate(219m) with a floating gate(210a), a gate interlayer dielectric(212a) and a control gate electrode(214a) sequentially deposited on the semiconductor substrate. A tunneling oxide layer(208) is interposed at the predetermined area between the floating gate(210a) and the semiconductor substrate. A selection gate(224s) covers the one sidewall of the memory gate(219m) and a specific area of the semiconductor substrate. A transistor insulating layer(223) is interposed between the selection gate(224s) and the memory gate(219m). A drain region(226d) is existent within the area of the semiconductor substrate sided with the selection gate(224s). A source region(226s) is existent with the area of the semiconductor substrate sided with the memory gate(219m). A channel region(204) is existent within the area of the semiconductor substrate under the transistor insulating layer(223) while being extended to the area of the semiconductor substrate under the tunneling oxide layer(208).

Description

Non-volatile memory device and method of manufacturing the same

The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a Floating Gate Tunneling Oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) memory device having a selection transistor and a memory transistor, and a method of manufacturing the same.

In general, an EEPROM cell has a floating gate, similar to an erasable programmable read only memory (EPROM) cell, and stores data by injecting or emitting electrons into the floating gate. However, the electron injection and emission method of EEPROM adopts a very different method compared to EPROM.

In the EPROM, the injection of electrons into the floating gate is performed by hot electrons having high energy among the electrons flowing between the source and the drain, and the electron emission uses the energy of ultraviolet rays. In contrast, the injection and emission of electrons from the EEPROM to the floating gate uses tunneling generated through a thin tunnel insulating film of about 100 kHz. In other words, when a high field of 10 MeV / cm is applied to both ends of the tunnel oxide film, current flows through the tunnel insulating film, which is called FN tunneling (Folow-Nordheim tunneling). The injection and emission of electrons in the EEPROM uses FN tunneling described above.

Among the EEPROM memories, in particular, the FLOTOX type memory comprises one transistor, two transistors, that is, a selection transistor for selecting a cell and a memory transistor for storing data.

1A is a plan view illustrating a conventional nonvolatile memory device.

FIG. 1B is a cross-sectional view of a conventional nonvolatile memory device taken along the line II ′ of FIG. 1A.

1A and 1B, the device isolation layer 102 is disposed in one direction in a predetermined region of the semiconductor substrate 100 to define an active region. A floating gate 110a is disposed in a predetermined region on the active region, and a control gate electrode 114a intersecting the device isolation layer 102 and crossing the active region is disposed across the upper portion of the floating gate 110a. . A tunnel oxide film 108 is interposed in a predetermined region between the floating gate 110a and the active region, and a memory gate oxide film 106 is interposed in a region surrounding the tunnel oxide film 108. In addition, a memory gate interlayer dielectric film 112a is interposed between the control gate electrode 114a and the floating gate 110a. The floating gate 110a, the memory gate interlayer dielectric film 112a, and the control gate electrode 114a constitute a gate electrode of the memory transistor. The first select gate 124s and the second select gate 124s that are sequentially stacked adjacent to the memory transistor gate electrode in a direction parallel to the control gate electrode 114a are disposed. A select gate interlayer dielectric film 112s is interposed between the first select gate 124s and the second select gate 124s. The first selection gate 124s and the second selection gate 124s are electrically connected to each other in a predetermined region of the semiconductor substrate 100 to form a gate electrode of the selection transistor. A channel region 104 exists in an active region between the memory gate and the select gate. The channel region 104 extends below the tunnel oxide layer 108. In addition, a source region exists in an active region adjacent to the other side of the memory gate where the channel region 104 is not formed, and a drain region exists in the other active region of the selection gate 124s.

As shown in the related art, the memory gates and the selection gates are arranged side by side at a predetermined interval. Accordingly, the FLOTOX nonvolatile memory device having a memory gate and a selection gate has a problem that the degree of integration is lower than that of a DRAM or a flash memory.

An object of the present invention is to provide a highly integrated nonvolatile memory device having a memory gate and a selection gate, and a method of manufacturing the same.

1A and 1B are plan and cross-sectional views illustrating a conventional nonvolatile memory device, respectively.

2A is a plan view illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along II-II 'of FIG. 2A.

3A through 7A are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to a preferred embodiment of the present invention taken along II-II ′ of FIG. 2A.

3B through 7B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention, taken along III-III ′ of FIG. 2A.

In order to achieve the above technical problem, the present invention provides a nonvolatile memory device and a method of manufacturing the same, which minimize the space between the memory gate and the selection gate. This device includes a memory gate composed of a floating gate, a gate interlayer dielectric film, and a control gate electrode sequentially stacked on a semiconductor substrate. A tunnel oxide film is interposed in a predetermined region between the floating gate and the semiconductor substrate, and a selection gate covering a predetermined region of the semiconductor substrate is disposed on one sidewall of the memory gate. A transistor insulating film is interposed between the selection gate and the memory gate to electrically insulate the selection gate and the memory gate. A drain region exists in the semiconductor substrate next to the selection gate and a source region exists in the semiconductor substrate next to the memory gate. In addition, there is a channel region extending from the semiconductor substrate under the transistor interlayer insulating film to the inside of the semiconductor substrate under the tunnel oxide film.

The method of manufacturing a memory device includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region, and forming at least one pair of channel regions in a predetermined region within the active region. Subsequently, a tunnel oxide film is formed in a predetermined region on the channel region, and a gate oxide film is formed on the entire surface of the region surrounding the tunnel oxide film on the active region. Preferably, the tunnel oxide film may be formed to a thickness thinner than that of the gate oxide film. Specifically, a thin tunnel oxide layer may be formed by first forming a gate oxide layer on the active region, removing the gate oxide layer on the channel region, and then performing a thermal oxidation process.

Subsequently, a stacked pattern is formed across the active region and covers the pair of channel regions. The stacking pattern includes a first conductive layer pattern, a gate interlayer dielectric layer pattern, and a second conductive layer pattern that are sequentially stacked. Subsequently, a transistor insulating film is formed to cover both sidewalls of the stacked pattern, and select gates respectively covering the transistor insulating film are formed at both sides of the stacked pattern. Patterning the stacked patterns having select gates formed on both sidewalls to expose active regions between the pair of channel regions, thereby forming a pair of memory gates passing over the channel regions and crossing the active regions side by side. Subsequently, a source region is formed in the active region exposed between the memory gates and a drain region is formed in the semiconductor substrate next to the selection gate. As a result, since the memory gate and the selection gate are adjacent to each other with the transistor insulating film interposed therebetween, the area can be minimized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents can be thorough and complete, and the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

2A and 2B show a plan view and a cross-sectional view of a nonvolatile memory device according to a preferred embodiment of the present invention, respectively.

2A and 2B, an isolation layer 202 is disposed in a predetermined region of the semiconductor substrate 200 to define an active region. The memory gate 219m and the selection gate 224s are arranged side by side in one direction across the active region. The memory gate 219m and the selection gate 224s constitute one cell gate. The cell gates are disposed symmetrically with neighboring cell gates on the semiconductor substrate 200. The memory gate 219m includes a floating gate 210a, a memory gate interlayer dielectric film 212a, and a control gate electrode 214a that are sequentially stacked. The floating gate 210a is positioned above the active region, and the memory gate interlayer dielectric layer 212a and the control gate electrode 214a cross the upper portion of the floating gate 210a and cross the active region. A tunnel oxide layer 208 and a memory gate oxide layer 206 surrounding sidewalls of the tunnel oxide layer 208 are interposed between the floating gate 210a and the active region. A feature of the present invention is that the select gate 224s is disposed in the form of a spacer on the sidewall of the memory gate 219m as shown. The selection gate 224s and the memory gate 219m are insulated from the transistor insulating layer 223. The transistor insulating layer 223 includes an insulating layer spacer 220a covering one sidewall of the memory gate 219m, and an interlayer insulating layer 222 covering an upper portion of the memory gate 219m and the insulating layer spacer 220a. The interlayer insulating layer 222 extends at least under the selection gate 224s. The interlayer insulating layer 222 interposed between the active region and the selection gate 224s corresponds to a selection gate insulating layer.

As illustrated, the cell gates including the selection gate 224s and the memory gate 219m are symmetrically disposed on the semiconductor substrate 200. A source region 226s exists in the active region between the symmetrical cell gates, and a drain region 226d exists in the active region next to the select gate 224s. The device isolation layer 202 may not be disposed between the memory gates 219m. In this case, the source region 226s is in the active region parallel to the memory gate 219m. In addition, a channel region 204 is present in the semiconductor substrate under the tunnel oxide layer 208, and the channel region 204 is formed under the transistor insulating layer 223 between the selection gate 224s and the memory gate 219m. Extends beyond the select gate 224s.

Unlike the prior art, according to the present invention, the memory gate and the selection gate are disposed at intervals of the thickness of the memory insulating film for electrically insulating them. Therefore, the size of the memory cell can be significantly reduced as compared with the prior art.

3A through 7A are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to a preferred embodiment of the present invention taken along II-II ′ of FIG. 2A.

3B through 7B are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a preferred embodiment of the present invention, taken along III-III ′ of FIG. 2A.

3A and 3B, an isolation region 202 is formed in a predetermined region of the semiconductor substrate 200 to define an active region. An impurity is implanted into a predetermined region in the active region to form at least a pair of channel regions 204. A gate oxide layer 204 is formed on the entire surface of the active region in which the channel regions 204 are formed, and the gate oxide layer 204 on each of the channel regions 204 is removed. Subsequently, a thermal oxidation process is applied to the semiconductor substrate 200 from which the gate oxide layer 204 is removed to form a tunnel oxide layer 208 on each of the channel regions 204. As a result, a thin tunnel oxide film 208 exists on top of each of the channel regions 204, and a gate oxide film 204 exists around the sidewalls of the tunnel oxide film 208 in front of the active region. .

4A and 4B, a first conductive film is formed on the entire surface of the resultant product in which the tunnel oxide film 208 is formed. Subsequently, the first conductive layer is patterned to expose an upper portion of the device isolation layer 202 to form a first conductive layer pattern covering the entire surface of the active region. Subsequently, a gate interlayer dielectric film and a second conductive film are sequentially formed on the entire surface of the resultant product on which the first conductive film pattern is formed. The gate interlayer dielectric film is a material having a high dielectric constant, and may be formed using, for example, an ONO film. In addition, a capping insulating layer may be further formed on the second conductive layer. Subsequently, the capping insulating layer, the second conductive layer, the gate interlayer dielectric layer, and the first conductive layer pattern are sequentially patterned to form a stacked pattern 219 that crosses the active region. In this case, it is preferable to expose part of the channel region 204 on both sides of the stack pattern 219. The stacked pattern 219 may sequentially cover the floating gate pattern 210 covering the active region, the upper portion of the floating gate pattern 210, and the gate interlayer dielectric layer pattern 212 and the second conductive layer pattern crossing the active region. 214. When the capping insulation layer is formed, the capping insulation layer pattern 218 may be further included on the second conductive layer pattern 214.

Subsequently, the insulating film 220 is conformally formed on the entire surface of the resultant product in which the stacked pattern 219 is formed. In this case, before forming the insulating layer 220, the gate oxide layer 204 exposed to both sides of the stack pattern 219 may be removed together to expose the active region. The insulating film is preferably formed of a silicon nitride film or a silicon oxide film.

5A and 5B, the insulating film 220 is anisotropically etched to form insulating film spacers 220a on both sidewalls of the stacked pattern 219. As a result, sidewalls of the stacked pattern 219 are covered with the insulating layer spacer 220a, and active regions adjacent to both sides of the stacked pattern 219 covered with the sidewalls are exposed by the insulating layer spacer 220a. Subsequently, an interlayer insulating film 222 is conformally formed on the entire surface of the resultant film on which the insulating film spacer 220a is formed. Subsequently, a third conductive film 224 covering the entire surface of the interlayer insulating film 222 is formed. The third conductive film 224 may be formed of a polysilicon film or a metal polyside film. The insulating film spacer 220a and the interlayer insulating film 222 constitute a transistor insulating film 223 electrically insulating the memory gate and the selection gate to be formed in a subsequent process.

6A and 6B, the third conductive layer 224 is anisotropically etched to form a selection gate 224s having a spacer structure on sidewalls of the stack pattern 219. The selection gate 224s is formed on each sidewall of the stack pattern 219 covered with the insulating film spacer 220a and the interlayer insulating film 222. That is, the insulating film spacer 220a and the interlayer insulating film 222 are interposed between the selection gate 224s and the stack pattern 219.

Referring to FIGS. 7A and 7B, the interlayer insulating layer 222 and the lamination pattern 219 that are present on the central portion of the lamination pattern 219 are sequentially patterned in parallel with the lamination pattern 219. A pair of memory gates 219m are formed to cross the active region side by side. Each of the memory gates 219m includes a floating gate 210a, a memory gate interlayer dielectric film 212a, and a control gate electrode 214a that are sequentially stacked on each of the pair of tunnel oxide films 208. . The memory gate 219m and the selection gate 224s disposed on one side wall of the memory gate 219m constitute one cell gate. That is, at least one pair of cell gates symmetrical with each other and across the active region are disposed on the semiconductor substrate 200. The gate insulating layer 206 interposed between the memory gate 219m and the active region corresponds to a memory gate insulating layer, and the interlayer insulating layer 222 interposed between the selection gate 224s and the active region is selected. It corresponds to a gate insulating film.

In addition, a source region 226s is formed by injecting impurities into the active region between the memory gates 219m, and a drain region 226d is formed by implanting impurities into the active region next to the selection gate 224s. do. The gate oxide layer 204 existing between the memory gates 219m may be removed before the source region 226s is formed. In addition, the device isolation layer 202 exposed between the memory gates 219m may be removed to form a common source line parallel to the memory gates 219m between the memory gates 219m.

As a result, according to the present invention, since the selection gate is formed in the form of a spacer on the sidewall of the memory gate, high integration can be achieved by minimizing the space between the selection gate and the memory gate.

As described above, according to the present invention, in the nonvolatile memory device including the selection gate and the memory gate, the integration of the device can be achieved by forming the selection gate in the form of a spacer on the sidewall of the memory gate. Therefore, the problem of the FLOTOX memory cell, which is difficult to integrate with other memory devices such as DRAM or flash memory, can be solved.

Claims (16)

A memory gate including a floating gate, a gate interlayer dielectric film, and a control gate electrode sequentially stacked on the semiconductor substrate; A tunnel oxide film interposed in a predetermined region between the floating gate and the semiconductor substrate; A selection gate covering one sidewall of the memory gate and a predetermined region of the semiconductor substrate; A transistor insulating layer interposed between the selection gate and the memory gate; A drain region existing in the semiconductor substrate next to the selection gate; A source region existing in the semiconductor substrate next to the memory gate; And And a channel region existing in the semiconductor substrate under the transistor insulating layer and extending to the semiconductor substrate under the tunnel oxide layer. According to claim 1, The memory gate is, And a capping insulating layer pattern covering an upper portion of the control gate electrode. According to claim 1, And a memory gate insulating layer interposed between the floating gate and the semiconductor substrate to surround the tunnel insulating layer. According to claim 1, The transistor insulating film, And an interlayer insulating layer covering an insulating layer spacer covering one sidewall of the memory gate and covering an upper portion of the memory gate. The method of claim 4, wherein And the interlayer insulating layer extends below the selection gate and is interposed between the selection gate and the semiconductor substrate. Device isolation layers disposed in one direction in a predetermined region of the semiconductor substrate to define active regions; A gate interlayer dielectric film and a control gate electrode sequentially stacked across the active region; Floating gates interposed between each of the active regions and the gate interlayer dielectric layer; Tunnel oxide films interposed in a predetermined region between each of the floating gates and the active regions; A selection gate disposed in parallel with the control gate electrode and covering all of one side wall of the control gate electrode, one side wall of the gate interlayer dielectric layer, and one side wall of the floating gates; A transistor insulating film disposed between the control gate electrode and the selection gate, between the interlayer dielectric film and the selection gate, and between the floating gates and the selection gate; Drain regions formed in active regions adjacent to the selection gate; Source regions formed in active regions opposite the drain region; and And a channel region existing in an active region below the transistor insulating layer and extending to the lower portions of the tunnel oxide layers. The method of claim 6, A memory gate oxide film interposed in a region surrounding the tunnel oxide film between each of the floating gates and the active regions; And And a selection gate oxide layer extending from the transistor insulating layer and interposed between the selection gate electrode and the active region. The method of claim 6, The transistor insulating film, An insulating film spacer covering one sidewall of the control gate electrode and one sidewalls of the floating gates; and And an interlayer insulating layer covering the upper portion of the control gate electrode and the insulating layer pattern and extending to the lower portion of the control gate electrode. The method of claim 6, And a gate interlayer dielectric film interposed between the control gate electrode and the floating gate electrodes. The method of claim 6, And the source regions are electrically connected to neighboring source regions to form a common source line, wherein the common source line is arranged in a direction parallel to the control gate electrode. Forming an isolation layer in a predetermined region of the semiconductor substrate to define an active region; Forming at least one pair of channel regions in a predetermined region of the active region; Forming a tunnel oxide film in a predetermined region on the channel region, and forming a gate oxide film on an entire surface of the region surrounding the tunnel oxide film on the active region; Forming a stacked pattern in which a first conductive layer pattern, a gate interlayer dielectric layer pattern, and a second conductive layer pattern are sequentially stacked across the active region and covering the pair of channel regions; Forming a transistor insulating film covering both sidewalls of the stacked pattern; Forming select gates on both sides of the stack pattern to cover the transistor insulating film; Patterning the stacked patterns in a direction parallel to the stacked patterns so that the active regions between the pair of channel regions are exposed to form a pair of memory gates passing over the respective channel regions and crossing the active regions; Forming a source region in an active region exposed between the memory gates and simultaneously forming a drain region in a semiconductor substrate next to the selection gate. The method of claim 11, wherein Forming the tunnel oxide film and the gate oxide film, Forming a gate oxide film on an entire surface of the semiconductor substrate on which the channel region is formed; Exposing the semiconductor substrate by removing the gate oxide layer over the predetermined region of the channel region; and And forming a tunnel oxide film on the exposed semiconductor substrate. The method of claim 11, wherein Forming the laminated pattern, Forming a first conductive layer pattern covering an upper portion of an active region in which the tunnel oxide layer and the gate oxide layer are formed; Forming a gate interlayer dielectric film covering the entire surface of the resultant product on which the first conductive film pattern is formed and a second conductive film covering the entire surface of the gate interlayer dielectric film; and Patterning the second conductive layer, the gate interlayer dielectric layer, and the first conductive layer in order, a first conductive layer pattern covering the upper portion of the active region, and a gate covering the first conductive layer pattern in sequence and crossing the active region. A method of manufacturing a nonvolatile memory device comprising forming an interlayer dielectric layer pattern and a second conductive layer pattern. The method of claim 13, After forming the first conductive film pattern, And removing the gate insulating layers exposed to both sides of the stacked pattern. The method of claim 11, wherein Forming the transistor insulating film, Forming an insulating film conformally covering the entire surface of the resultant product in which the lamination pattern is formed; Anisotropically etching the insulating film to form insulating film spacers on both sidewalls of the stacked pattern; and And forming an interlayer insulating film on the entire surface of the resultant in which the insulating film spacer is formed, wherein the insulating film spacer and the interlayer insulating film constitute a transistor insulating film. The method of claim 11, wherein Forming the selection gate, Forming a third conductive film on an entire surface of the resultant product in which the transistor insulating film is formed; and And anisotropically etching the third conductive layer to form a select gate having a spacer structure on sidewalls of the memory gate on which the transistor insulating layer is formed.