KR20030029151A - Trench mosfet with structure having low gate charge - Google Patents

Abstract

The present invention relates to trench MOSFET devices and methods of fabrication. Wrench MOSFET device,

a) a semiconductor substrate of a first conductivity type;

b) an epitaxial region of a first conductivity type provided within the bottom of the semiconductor epitaxial layer disposed on the substrate, wherein the epitaxial layer of the first conductivity type has a lower number of carrier concentrations than the substrate; An epitaxial region of;

c) a region of a second conductivity type provided within the semiconductor epitaxial layer;

d) a plurality of trench segments at the top surface of the semiconductor epitaxial layer, i) a plurality of trench segments extending through a region of a second conductivity type to an epitaxial region of a first conductivity type, and ii) each trench segment A plurality of trench segments, at least partially separated from adjacent trench segments by terminating regions of the semiconductor epitaxial layer, i) trench segments defining a plurality of polygonal body regions within regions of a second conductivity type. Wow;

e) a first insulating layer at least partially lining the boundaries of each trench segment;

f) a plurality of first conductive regions in trench segments adjacent the first insulating layer, each first conductive region being connected to an adjacent first conductive region by a connecting conductive region bridging at least one termination; A plurality of first conductive regions;

g) a plurality of source regions of a first conductivity type located within the top of the polygonal body region and adjacent to the trench segments.

The body region is preferably a rectangular body region defined by four trench segments, or a hexagonal body region defined by six trench segments.

Description

TRENCH MOSFET WITH STRUCTURE HAVING LOW GATE CHARGE}

Metal oxide semiconductor field effect transistor (MOSFET) devices using trench gates provide low turn-on resistance. In such trench MOSFET devices, the channels are arranged in a vertical manner instead of a horizontal manner as in most planar configurations. 1 shows a partial cross-sectional view of a conventional trench gate MOSFET device 2. The MOSFET device comprises a trench 4 filled with a conductive material 6 separated from the silicon region 8 by a thin layer of insulating material 10. Body region 12 diffuses in epitaxial layer 18, and source region 14 diffuses in body region 12 in turn. Due to the use of these two diffusion stages, this type of transistor is often referred to as a double diffusion metal oxide semiconductor field effect transistor with trench gating, ie simply a " trench DMOS. &Quot;

As arranged, the conductive and insulating materials 6 and 10 in the trench 4 form the gate 15 and gate oxide layer 16 of the trench DMOS, respectively. Furthermore, the depth L measured from the source 14 to the epitaxial layer 18 constitutes the channel length L of the trench DMOS device. The epitaxial layer 18 is part of the drain 20 of the trench DMOS device.

When a potential difference is applied across the body 12 and the gate 15, charge is induced capacitively in the body region 12 adjacent the gate oxide layer 16, thereby causing the channel 21 of the trench DMOS device. Will form. When another potential difference is applied across source 14 and drain 20, current flows from source 14 to drain 20 through channel 21, and the trench DMOS device is powered on. Can be said to be in a state.

Examples of trench DMOS transistors are described in US Pat. Nos. 5,907,776, 5,072,266, 5,541,425, and 5,866,931, the entirety of which is incorporated herein by reference.

Conventional discrete trench MOSFET circuits include two or more individual trench MOSFET transistor cells fabricated in parallel. The individual trench MOSFET transistor cells share a common drain contact, while the sources of the cells are all shorted through the metal and the gates are shorted together by polysilicon. Thus, even if the discrete trench MOSFET circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.

The unit cell configuration of the trench MOSFET circuit can take various forms. 2A and 2B show two trench configurations commonly used in the prior art. Unlike FIG. 1, which shows a partial cross-sectional view (or elevation) of a single trench region in a MOSFET circuit, FIGS. 2A and 2B show a partial plan view (top view) of two trench networks. In particular, FIG. 2A shows a partial view of the trench network 4 in which the trenches collectively form a series of hexagonal unit cells (magnification shows the cells to be in a honeycomb pattern). 2b shows a partial view of the trench network 4 in which the trenches form a series of square unit cells (magnification shows the cells to be arranged in a grid-like square manner). 2B may be considered to be formed by the intersection of two sets of parallel trench lines. All trench regions (ie all black portions) in FIGS. 2A and 2B are essentially the same depth within the trench network.

There is always a need for trench DMOS devices with low on-resistance. The simplest way to reduce on-resistance is to increase cell density. Unfortunately, as cell density increases, the gate charge associated with the trench DMOS device increases.

Thus, efforts to provide low on-resistance for trench DMOS devices by increasing cell density are currently frustrated by detrimental changes occurring simultaneously in, for example, the gate charge associated with the device.

These and other disadvantages in the prior art are addressed by the trench MOSFET device and method of the present invention.

TECHNICAL FIELD The present invention relates to microelectronic circuits, and more particularly to trench MOSFET devices.

1 is a partial cross-sectional view of a conventional trench DMOS device.

2A and 2B are partial plan views (or plan views) of trench configurations associated with DMOS devices having hexagonal and square unit cells, respectively.

FIG. 3 is a partial plan view (or plan view) of a MOSFET trench network such as shown in FIGS. 2A and 2B where substantial current flow and non-current current flow regions are shown.

4A is a partial cross-sectional view of a trench MOSFET device taking a view along a plane similar to that indicated by line A-A 'in FIG. 3 and having the same trench structure as in FIG.

FIG. 4B is a partial cross-sectional view of a trench MOSFET device taking a view along a plane similar to that indicated by line B-B 'in FIG. 3 and having the same trench structure as in FIG.

FIG. 5 is a graph of inactive area (%) vs. cell density for a trench MOSFET device with a trench structure as in FIG. 3. FIG.

6 is a partial plan view (or plan view) of a trench configuration of a MOSFET device in accordance with one embodiment of the present invention.

FIG. 7A is a partial cross-sectional view of a MOSFET device taking a view along a plane similar to that indicated by line A-A 'in FIG. 6 and having the trench structure of FIG.

FIG. 7B is a partial cross-sectional view of the MOSFET device taking a view along a plane similar to that indicated by line B-B 'in FIG. 6 and having the trench structure of FIG.

8A-8D are partial plan views of various trench designs that allow trench segments and trench lines to be used to form a square cell of a MOSFET device.

9A-9E illustrate a trench MOSFET manufacturing method of the present invention, taken along a field of view similar to FIG. 7A, and in accordance with one embodiment of the present invention.

10A through 10E illustrate a method of fabricating a trench MOSFET of the present invention, taken along a field of view similar to that of FIG. 7B, and in accordance with one embodiment of the present invention.

11 is a partial cross-sectional view of a trench MOSFET of the prior art.

According to one embodiment of the invention, a trench MOSFET device is provided. Trench MOSFET devices

a) a semiconductor substrate of a first conductivity type;

b) an epitaxial region of a first conductivity type provided within the bottom of the semiconductor epitaxial layer disposed on the substrate, wherein the epitaxial layer of the first conductivity type has a lower number of carrier concentrations than the substrate; An epitaxial region of;

c) a region of a second conductivity type provided within the semiconductor epitaxial layer;

d) a plurality of trench segments at the top surface of the semiconductor epitaxial layer, i) a plurality of trench segments extending through a region of a second conductivity type to an epitaxial region of a first conductivity type, and ii) each trench segment A plurality of trench segments, at least partially separated from adjacent trench segments by terminating regions of the semiconductor epitaxial layer, i) trench segments defining a plurality of polygonal body regions within regions of a second conductivity type. Wow;

e) a first insulating layer at least partially lining the boundaries of each trench segment;

f) a plurality of first conductive regions in trench segments adjacent the first insulating layer, each first conductive region being connected to an adjacent first conductive region by a connecting conductive region bridging at least one termination; A plurality of first conductive regions;

g) a plurality of source regions of a first conductivity type located within the top of the polygonal body region and adjacent to the trench segments.

The body region is preferably a rectangular body region defined by four trench segments, or a hexagonal body region defined by six trench segments.

In some preferred embodiments: i) the trench MOSFET device is a silicon device, ii) the first conductivity type is n-type conductivity, the second conductivity type is p-type conductivity, more preferably, the substrate is an N + substrate, The epitaxial region of the first conductivity type is an N region, the body region comprises a P region, the source region is an N + region, iii) the first insulating layer is an oxide layer, and iii) the first conductive region and the connecting conductive region. Is a polysilicon region and / or iii) a drain electrode is disposed on the surface of the substrate and the source electrode is disposed on at least a portion of the source region.

In accordance with another embodiment of the present invention, a method for forming a trench MOSFET device is provided. The method,

a) providing a semiconductor substrate of a first conductivity type;

b) forming a semiconductor epitaxial layer over the semiconductor substrate, wherein the epitaxial layer is of a first conductivity type and has a lower carrier concentration than the substrate;

c) the top of the semiconductor epitaxial layer (eg, by a method comprising implanting and diffusing impurities into the epitaxial layer) such that an epitaxial region of the first conductivity type remains within the bottom of the semiconductor epitaxial layer. Forming a region of a second conductivity type in the substrate;

d) forming a plurality of trench segments in the upper surface of the epitaxial layer (eg, by a method comprising forming a patterned masking layer over the epitaxial layer and etching the trench through the masking layer). (I) trench segments extend through regions of the second conductivity type to epitaxial regions of the first conductivity type, and (ii) each trench segment is at least partially from an adjacent trench segment by an end of the semiconductor epitaxial layer. Forming a plurality of trench segments, wherein the trench segments define a plurality of polygonal body regions within a region of a second conductivity type;

e) forming a first insulating layer in each trench segment;

f) forming a plurality of first conductive regions in trench segments adjacent the first insulating layer;

g) forming a plurality of connected conductive regions, each connecting conductive region forming a plurality of connected conductive regions, bridging at least one termination, and connecting one first conductive region to an adjacent first conductive region; Steps;

h) forming a plurality of source regions of a first conductivity type within the top of the polygonal body region and adjacent to the trench segments.

Preferably, the first insulating layer is an oxide layer and is formed through dry oxidation.

Forming the source region preferably includes forming a patterned masking layer and implanting and diffusing impurities over the polygonal body region.

The first conductive region and the connecting conductive region are preferably polysilicon regions, and are preferably formed at the same time. More specifically, the first conducting region and the connecting conducting region are formed by a method comprising depositing a polycrystalline silicon layer, positioning a patterned masking layer over the polycrystalline silicon, and etching the polycrystalline silicon layer through the patterned mask. Is formed.

One advantage of the present invention is that a trench MOSFET device is provided which has an increased cell density and thus a lower on-resistance while minimizing the increase in gate charge.

Another advantage of the present invention is that such a device can be manufactured relatively simply.

These and other embodiments and advantages of the invention will be readily apparent to those skilled in the art upon reading the following detailed description and claims.

The invention will now be described in more detail hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

FIG. 3 illustrates a trench pattern as in FIG. 2B. In this figure, two sets of parallel trench lines intersect to form a square unit cell 70. The dark areas of the trench lines (indicated by 54b) correspond to the portion of the trench where the source-drain current flows in the power-on state (referred to herein as " active trench region "), while the bright areas 54c Denotes the portion of the trench line that is substantially free of source-drain current flow in the power-on state (referred to herein as " inactive trench region "). These inactive trench regions 54c correspond to the locations where the trench lines intersect.

The current flow can be seen more clearly in FIG. 4A, which is a cross-sectional view of a trench MOSFET device with a trench structure as in FIG. The field of view is taken along a plane similar to that indicated by line A-A 'in FIG. This figure shows a gate trench (consisting of an active region 54b and an inactive region 54c) and N epitaxial bordered by an insulating material that is generally oxide (not shown) and filled with a conductive material such as polysilicon 58. An N + substrate 50 is shown with the tactile layer 52. The current flow from the drain to the surface of the active trench region 54b is shown by the arrows in FIG. 4A. Inactive trench region 54c is essentially free of such current, so no arrows are shown in these regions.

The field of view of FIG. 4B is taken along a plane similar to that indicated by line B-B ′ in FIG. 3. P-body region 56 (source of device not shown), as well as N + substrate 50, N epitaxial layer 52, and polysilicon region 58 in trenches (insulating material not shown) This is shown in the figure. As in FIG. 4A, the current flow from the drain to the surface of the active trench region 54b is shown by an arrow. Since region B-B 'does not include any region where the trenches overlap, no inactive trench region 54c is included by region B-B'.

As those skilled in the art will immediately recognize, when the cell density of FIG. 3 increases (ie, when the size of the trench segment of FIG. 3 decreases), the percentage of inactive areas associated with certain closed cells also increases. More specifically, as shown in FIG. 5, when the cell density increases from 49 million cells per square inch to 29 million cells per square inch, the relative area of the inactive trench is from about 10% of the total trench area to the total trench area. Increases to about 45%. Although the inactive region does not contribute to the current flow, the inactive region contributes to the gate charge, in particular the charge Qgd between the gate and the drain. As a result, as the cell density increases, the relative Qgd contribution from the inactive region also increases.

To solve this problem, the inventor proposes a new trench structure consisting of separate trench segments rather than a continuous trench network.

Referring now again to FIG. 6, a partial plan view (or plan view) of a trench configuration of a MOSFET circuit is shown in accordance with one embodiment of the present invention. This figure shows twelve trench segments 64. In contrast to FIG. 3, where trench lines 54 intersect to form a continuous trench network, trench segments 64 do not substantially intersect, thus representing a series of spaced trenches.

This property is shown in more detail in FIGS. 7A and 7B. 7A is a cross-sectional view of a device having a trench structure as shown in FIG. 6. The field of view is taken along a plane similar to that indicated by line A-A 'in FIG. This figure shows an N + substrate 60, with trench segments bounded by N epitaxial layer 62, P-body region 66, and oxide (not shown) and filled with polysilicon 68. Illustrated. In addition to filling the trench segments, polysilicon 68 also covers a portion of the P-body region 66. The current flow from the drain to the surface of the gate trench segment is shown by the arrows in FIG. 7A. As can be seen in this figure, all trench segments are active trench segments 64b. Although inactive regions with no current flow remain, these regions are associated with P-body region 66 rather than trench segments. Alternatively, the inactive region 54c of FIG. 4A is associated with a trench. This variant is advantageous in that the gate charge associated with the inactive trench region 54c of FIG. 4A no longer exists.

The field of view of FIG. 7B is taken along a plane similar to that indicated by line B-B ′ in FIG. 6. As in FIG. 7A, an N + substrate 60, an N epitaxial layer 62, a trench segment 64, a P-body region 66, and a polysilicon region 68 are shown. The arrow shows the current flow from the drain to the surface of the trench segment, which is the active trench segment 64b. The field of view of FIG. 7B is not substantially different from the field of view of FIG. 4B.

The embodiment of the present invention just mentioned above relates to a MOSFET structure having a cell (square cell structure) surrounded by trench segments on four sides. As used herein, a "trench segment" is a short trench that forms the face of a polygonal cell. Rather than extending substantially longer than the length of the cell face, the trench segments are at least partially blocked at the ends by a semiconductor region close to the corner of the polygonal cell. 8A-8D show partial plan views of various trench designs in which trench segments 64s (FIGS. 8A-8C) and trench lines 64t (FIG. 8D) can be used to form square cells 70 of MOSFET devices. Illustrated. 8A shows that trench segment 64s corresponds to semiconductor region 66+ (generally corresponding to portions of p-body region 66 and N-epitaxial region 62, as shown in FIG. 7A). The case of blocking by the figure is shown. In FIG. 8B, adjacent trench segments 64s barely meet each other, resulting in essentially complete blockage by semiconductor region 66+. In FIG. 8C, trench segment 64s is partially blocked by semiconductor region 66+.

Finally, FIG. 8D shows a configuration of the prior art. The semiconductor cell 70 is surrounded on four sides by trench lines 64t extending longer than each cell 70 to form the face of another cell. At the corner of the square cell 70, each trench 64t is essentially not blocked by the semiconductor region.

The trench MOSFET fabrication method of the present invention will now be described with reference to FIGS. 9A-9E taken along the field of view as shown in FIG. 7A and FIGS. 10A-10E taken along the field of view as shown in FIG. 7B. As mentioned above, the field of view of FIG. 7B (similar to FIG. 10E) is substantially the same as that of the prior art. This structure may further comprise blocking properties, which are well known in the art.

Referring now to these figures, in this particular example, the N doped epitaxial layer 202 is initially grown on the N + doped substrate 200. For example, the epitaxial layer 202 may have a thickness of 6.0 μm and may have an n-type doping concentration of 3.4 × 10 ¹⁶ cm ⁻³ , while the N + doped substrate 200 has a thickness of 250 μm. It may have a thickness and may have an n-type doping concentration of 5 × 10 ¹⁹ cm ⁻³ . P-type layer 204 is then formed in epitaxial layer 202 by implantation and diffusion. For example, the epitaxial layer 202 may be implanted with boron at 40 keV at a dose of 6 × 10 ¹³ cm ⁻² , followed by diffusion to a depth of 1.8 μm at 1150 ° C. The resulting structure is shown in FIGS. 9A and 10A.

The mask oxide layer is then deposited by chemical vapor deposition and patterned using a trench mask (not shown). Trench segments 201 are typically etched through apertures in mask oxide layer 203 patterned by reactive ion etching. The trench depth in this example is about 2.0 μm. Separate P-regions 204, 204 'are established as a result of this trench-forming step. Some of these P-regions 204 correspond to body regions within the device cell. The other of these P-regions 204 'serves to block the trench segments and does not constitute part of the device cell (as described below, no source region is provided in the P-region 204'). }. The resulting structure is shown in FIGS. 9B and 10B.

The patterned mask oxide layer 203 is then removed and the oxide layer 210 is grown in place by dry oxidation generally at 950-1050 ° C. Eventually, oxide layer 210 forms a gate oxide for the finished device. In general, the thickness for the oxide layer 210 is in the range of 500 to 700 GPa. The structural surface is then covered and the trench is generally filled with a polysilicon layer using CVD. Polysilicon is typically doped N-type to reduce resistivity, which is generally about 20 mA / sq. N-type doping can be performed, for example, during CVD with phosphorus chloride or by implantation with arsenic or phosphorus.

The polysilicon layer is then etched by, for example, reactive ion etching. The polysilicon layer in the trench segment is etched somewhat excessively due to etch uniformity, and the polysilicon gate region 211g thus formed is generally 0.1 to 0.2 μm below the adjacent surface of the epitaxial layer 204. Have a top surface (see, eg, FIG. 10C). The mask is used during etching to ensure that the polysilicon region 211b is established over the region 204 'so that the polysilicon gate regions 211g are in electrical contact with each other. Generally, a mask is used to protect polysilicon in the gate runner region, so no additional mask step is necessary.

The oxide layer 210 is then wet etched to a thickness of 100 kPa to form an implant oxide. The graft oxide avoids graft-channeling effects, graft damage, and heavy metal contamination during subsequent formation of the source region. Next, a patterned masking layer 213 is provided over the portion of the P-region 204. The resulting cross sectional view of this structure is shown in FIGS. 9C and 10C.

In general, source region 212 is formed within the top of P-body region 204 through an implantation and diffusion process. For example, source region 212 may be implanted with arsenic in a dose of 1 × 10 ¹⁶ cm ⁻² , and may be diffused to a depth of 0.4 μm at a temperature of 950 ° C. FIG.

A borophosphosilicate glass (BPSG) layer is then formed over the entire structure, for example by PECVD, and a patterned photoresist layer (not shown) is provided. This structure is generally etched by reactive ion etching to remove the BPSG and oxide layer 210 over at least a portion of each source region 212. The resulting cross sectional view of this structure is shown in FIGS. 9D and 10D. {In this embodiment, the boron P + region 215 is formed between the source regions by P + implantation after the contact is opened.}

The photoresist layer is then removed, and the structure is provided with a metal contact layer 218 (aluminum in this example) in contact with the source region 214 and serving as the source electrode. {In this example, boron is implanted to form P + region 215 before the metal is deposited.} The resulting cross-sectional view of this structure is shown in FIGS. 9E and 10E. In the same step, a separate metal contact (not shown) is connected to the gate runner located outside the cell. In general, other metal contacts (also not shown) are provided in connection with the substrate 200 and serve as drain electrodes.

As discussed above, when reviewed along line B-B ', the structure of the present invention (see Figure 10E) looks essentially the same as the structure of the prior art. However, when examined along the line A-A ', the structure of the present invention (Fig. 9E) is fundamentally different from the prior art. Figure 11 illustrates such a prior art structure. The prior art structure of FIG. 11 includes a single trench line along line A-A ', bounded by oxide 210 and filled with polysilicon 211g. In contrast, the device of FIG. 9E includes a plurality of trench segments bounded by oxide 210 and filled with polysilicon 211g. These trench segments are blocked in the semiconductor region 204 ', which was not etched during processing. Polysilicon region 211b is established over region 204 ′ to contact polysilicon gate region 211g with each other. Since no gate structure is established in these regions 204 ', the gate capacitance is eliminated.

Although various embodiments are particularly shown and described herein, it will be appreciated that modifications and variations of the present invention are encompassed by the above teachings and are within the limits of the accompanying drawings without departing from the spirit and intended scope of the invention. For example, the methods of the present invention can be used to form structures in which the conductivity of various semiconductor regions is in conflict with those described herein.

As mentioned above, the present invention relates to microelectronic circuits, and more specifically, to trench MOSFET devices and the like.

Claims (22)

As a trench MOSFET device, A semiconductor substrate of a first conductivity type; An epitaxial region of a first conductivity type provided in a lower portion of a semiconductor epitaxial layer disposed on the substrate, wherein the epitaxial region of the first conductivity type has a lower majority carrier concentration than the substrate; An epitaxial region of conductivity type; A region of a second conductivity type provided within the semiconductor epitaxial layer; A plurality of trench segments at the top surface of the semiconductor epitaxial layer, the plurality of trench segments extending through the region of the second conductivity type to an epitaxial region of the first conductivity type, each said A trench segment is at least partially separated from an adjacent trench segment by a terminating region of the semiconductor epitaxial layer, the trench segment defining a plurality of polygonal body regions within the region of the second conductivity type Trench segments of; A first insulating layer at least partially lining the boundaries of each trench segment; A plurality of first conductive regions in the trench segment adjacent the first insulating layer, each of the first conductive regions being adjacent by a connecting conductive regions bridging at least one of the terminations; A plurality of first conductive regions connected to the conductive regions; A plurality of source regions of the first conductivity type located within the top of the polygonal body region and adjacent to the trench segments. A trench MOSFET device, comprising. The trench MOSFET device of claim 1, wherein the plurality of body regions are rectangular body regions defined by four trench segments. The trench MOSFET device of claim 1, wherein the plurality of body regions are hexagonal body regions defined by six trench segments. The trench MOSFET device of claim 1, wherein the trench MOSFET device is a silicon device. The trench MOSFET device of claim 1, wherein the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity. The trench MOSFET device of claim 1, further comprising a drain electrode disposed on a surface of the substrate, and a source electrode disposed on at least a portion of the source region. The trench MOSFET device of claim 1, wherein the first insulating layer is an oxide layer. The trench MOSFET device of claim 1, wherein the first conductive region and the connection conductive region are polysilicon regions. 6. The trench MOSFET device of claim 5, wherein the substrate is an N + substrate, the epitaxial region of the first conductivity type is an N region, the body region comprises a P region, and the source region is an N + region. A method of forming a trench MOSFET device, Providing a semiconductor substrate of a first conductivity type; Forming a semiconductor epitaxial layer over the semiconductor substrate, the epitaxial layer being of the first conductivity type and having a lower carrier concentration than the substrate; Forming a region of a second conductivity type within the top of the semiconductor epitaxial layer such that the epitaxial region of the first conductivity type remains within the bottom of the semiconductor epitaxial layer; Forming a plurality of trench segments at the top surface of the epitaxial layer, wherein (i) the trench segments extend through an area of a second conductivity type to an epitaxial area of the first conductivity type, and (ii) each The trench segments are at least partially separated from adjacent trench segments by terminations of the semiconductor epitaxial layer, and (i) the trench segments define a plurality of polygonal body regions within the region of the second conductivity type. Forming a trench segment in; Forming a first insulating layer delimiting each of said trench segments; Forming a plurality of first conductive regions in the trench segments adjacent the first insulating layer; Forming a plurality of connected conductive regions, each connecting conductive region forming a plurality of connected conductive regions, bridging at least one of the terminations, and connecting one of the first conductive regions to an adjacent first conductive region; Making a step; Forming a plurality of source regions of the first conductivity type within the top of the polygonal body region and adjacent to the trench segments; And forming a trench MOSFET device. 11. The method of claim 10 wherein the polygonal body region is a rectangular body region, each defined by four trench segments. 11. The method of claim 10 wherein the polygonal body region is a hexagonal body region, each defined by six trench segments. The method of claim 10, wherein the MOSFET device is a silicon device. The method of claim 10, wherein forming the region of the second conductivity type comprises implanting and diffusing a dopant into the epitaxial layer. The method of claim 10, wherein forming a trench segment comprises forming a patterned masking layer over the epitaxial layer and etching the trench through the masking layer. The method of claim 10, wherein the first insulating layer is an oxide layer. 17. The method of claim 16 wherein the oxide layer is formed through dry oxidation. The method of claim 10, wherein the first conductive region and the connection conductive region are polysilicon regions. 19. The method of claim 18 wherein the plurality of first conductive regions and the plurality of connected conductive regions are formed simultaneously. 20. The polycrystalline silicon of claim 19, wherein the plurality of first conductive regions and the plurality of connected conductive regions deposit a polycrystalline silicon layer, locate a patterned masking layer over the polycrystalline silicon, and through the patterned mask. A method of forming a trench MOSFET device, formed by a method comprising etching a layer. 15. The method of claim 14, wherein forming a source region comprises forming a patterned masking layer and implanting and diffusing impurities over the polygonal body region. 17. The method of claim 16 wherein the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity.