KR20030026761A - Digital vestigial sideband transmit system - Google Patents

Abstract

PURPOSE: A digital VSB transmission system is provided to perform unsystematic Reed-Solomon coding within a limited short period of time while minimizing the hardware size of an unsystematic Reed-Solomon encoder. CONSTITUTION: A digital VSB(Vestigial SideBand) transmission system includes a parity position holder insertion unit(107), a data interleaver(102), a parity replacement unit, and an unsystematic Reed-Solomon encoder(113). The parity position holder insertion unit obtains a plurality of parity position holders when multiplexed data is an overhead data segment, and then inserts null byte into the parity position holders. The data interleaver interleaves the output of the parity position holder insertion unit to output multiple information bytes first and then output multiple parity bytes having the inserted null bytes next for each segment. The parity replacement unit replaces the parity bytes with parity bytes obtained through unsystematic Reed-Solomon coding. The unsystematic Reed-Solomon encoder receives information bytes other than the parity bytes through the parity replacement unit and performs unsystematic Reed-Solomon coding of the input of the data interleaver to calculate parity bytes again and outputs the parity bytes to the parity replacement unit.

Description

Digital vestigial sideband transmit system

The present invention relates to a VSB transmission system that is compatible with the existing ATSC 8T-VSB reception system and can transmit additional additional data.

Recently, the Advanced Television Systems Committee (ATSC) 8Trellis-Vestigial Sideband (ATSC) transmission method, which has been adopted as a standard for digital terrestrial broadcasting in North America and Korea, is a system developed for transmitting MPEG video / audio data. However, with the rapid development of digital signal processing technology and the widespread use of the Internet, digital home appliances, computers, and the Internet are being integrated into one big framework. Accordingly, in order to meet various needs of users, it is necessary to develop a system capable of transmitting various additional data in addition to video / audio data through a digital broadcasting channel.

However, since the beginning of digital broadcasting, ATSC VSB digital broadcasting receivers that receive only MPEG video / audio have been widely used in the market. Therefore, the additional data transmitted on the same channel as the MPEG video / audio should not have any effect on the existing ATSC VSB dedicated receivers that have been prevalent in the market. This situation is defined as ATSC VSB compatible, and the additional data broadcast system should be compatible with the ATSC VSB system.

Therefore, many VSB transmission systems that are compatible with the existing ATSC 8T-VSB reception system and can transmit additional additional data have been proposed, and FIG. 1 is one of them, which has been previously filed by the present applicant (application) No. P01-32611, filing date: June 1, 2001).

In FIG. 1, additional data includes 20 bytes of systematic Reed Solomon parity bytes while sequentially passing through a Reed Solomon encoder 101, a data interleaver 102, a null sequence inserter 103, and an MPEG header inserter 104. An MPEG header including a null sequence and a PID (Program ID) is converted into an inserted additional data packet.

The multiplex 105 multiplexes the additional data packet and the MPEG video / audio data packet and outputs the multiplexed data packet to the data randomizer 106.

The data randomizer 106 receives the MPEG transport segment and the additional data segment multiplexed from the mux 105 and randomizes the data to the Reed-Solomon encoder / parity position holder inserter 107. Output

The Reed-Solomon encoder / parity position holder inserter 107 performs systematic Reed Solomon coding or parity position holder insertion on randomized data.

That is, when the segment output from the data randomizer 106 is an MPEG transport segment, the Reed-Solomon encoder / parity position holder inserter 107 normally performs systematic Reed-Solomon encoding of the existing ATSC 8T-VSB system. To perform. On the other hand, in the case of the additional data segment, the parity byte is positioned so that 20 parity bytes are output later than 187 information bytes at the output terminal of the data interleaver 108 at the rear end, and then a null byte is written at the determined parity byte position. In the byte position, 187 information bytes received are written in order from the beginning. In this case, the null byte is later replaced with a parity value calculated by the unstructured Reed-Solomon encoder 113.

The output of the Reed-Solomon encoder / parity position holder inserter 107 is input to the parity replacer 109 after being reordered by the data interleaver 108. That is, in the data interleaver 108, 187 information bytes are first outputted to the parity replacement unit 109, and then 20 parity bytes having null bytes inserted are output to the parity replacement unit 109. The parity replacement unit 109 replaces the parity position holder inserted into the additional data segment with a parity byte calculated by the unstructured Reed-Solomon encoder 113 and outputs the result to the byte-symbol converter 110. The byte of outputs the input to the byte-symbol converter 110 as it is. In this case, when the byte input to the parity replacement unit 109 is a byte of the MPEG transport segment, the parity replacement unit 109 is bypassed and output to the byte-symbol converter 110.

Data converted into a symbol form by the byte-symbol converter 110 is input to the symbol-byte converter 112 and the trellis encoder 114 through the additional data symbol processor 111.

The symbol-byte conversion unit 112 converts the input additional data symbol into a byte unit and outputs it to the unstructured Reed Solomon encoder 113. The unstructured Reed-Solomon encoder 113 collects 187 information bytes of the additional data segment, calculates 20 parity bytes, and outputs the parity bytes to the parity replacement unit 109.

The trellis encoder 114 precodes data input with the upper bits, and outputs the data input with the lower bits to the mux 115 by trellis encoding the data. The mux 116 multiplexes the output data of the trellis encoder 114, the field synchronizing signal, and the segment synchronizing signal to the pilot inserter 116, and the pilot inserter 116 multiplexes the signal. The pilot is inserted into the VSB modulator 117 and output. The VSB modulator 117 outputs the RF data to the RF converter 118 after VSB modulation of the input data, and the RF converted data is transmitted through an antenna.

Here, the purpose of using the unstructured Reed Solomon encoder 113 is to maintain compatibility with the existing 8T-VSB receiver. In other words, the reed-solomon decoder of the existing 8T-VSB receiver does not discriminate additional data segments as errors. In addition, the term unsystematic means that 20 parity bytes are not interspersed with 187 information bytes in a segment but intermingled in the middle.

FIG. 2 shows a data interleaver of a typical ATSC 8T-VSB system, which is a convolutional interleaver with the number of branches B = 52 and the number of bytes M = 4 of the unit memory. The data field of the ATSC 8T-VSB system consists of one field synchronization segment and 312 data segments.

The data interleaver of FIG. 2 described above operates in synchronization with the field sync segment.

3 illustrates the data input and output order of the data interleaver. Data input is entered from top to bottom in segment units, and bytes within the segment are entered first temporally from left to right. The numbers on the figure show the output order of the interleaver. The first byte of the first segment, which is input after the field sync segment (signal), is input to branch 1 and immediately output. That corresponds to the number 0 in FIG. 3. The next input byte is entered into branch 2 and the output is the byte 52 x 4 = 208 bytes before the input byte. Therefore, the byte corresponding to the number 1 is output in FIG. 3. If the next byte is input, the bytes 52 x 8 = 416 bytes before the input byte are output. Therefore, the byte corresponding to the number 2 is output. In this manner, 52 bytes are output in the order of FIG. 3, and the 53th input byte is directly input to branch 1 and immediately output.

As can be seen from Figure 3, the order in which 207 bytes of a particular segment is output by the interleaver is determined by the following equation (1).

f (k, s) = (52k + s) mod 207, 0≤s≤51, 0≤k≤206

In Equation 1, mod denotes a remainder operation, and s is a segment number after the field sync signal, and has a value from 0 to 51. F (k, s) indicates the position of the byte in the segment, and has a value from 0 to 206. Therefore, the order in which the bytes of a specific segment are output from the interleaver becomes f (k, s) obtained by substituting k = 0 to 206 in Equation 1. Since the parity position holder is the last 20 bytes of the output of the interleaver 108, the position is a value of f (k, s) obtained by substituting k = 187 to 206 in Equation 1 above.

In Equation 1, the segment number s is a number of 312 segments after the field sync segment, and has a value from 0 to 51. This is because the interleaver output order of a specific segment is repeated in 52 segment periods. Therefore, the segment number s of the nth (0 ≦ n ≦ 311) segment after the field sync segment is n mod 52. In addition, it can be seen that there are 52 segments having different positions of the parity position holder.

On the other hand, since the bytes of a specific segment are output at intervals of 52 or 53 bytes by the interleaver 108, there is a minimum time of 52 bytes until the first parity position holder byte is output after 187 information bytes of the specific segment are output. .

Therefore, the parity byte to replace the parity position holder byte output from the interleaver 108 must be calculated within a 52 byte clock. In other words, byte-symbol conversion, additional data symbol processing, symbol-byte conversion, and unstructured Reed-Solomon encoder operations must be implemented within a 52-byte clock. In this case, since the processing delays of the byte-symbol conversion and symbol-byte conversion units 110 and 112 are 12 byte clocks, and there is no processing latency of the additional data symbol processing unit 111, the unstructured Reed-Solomon encoder 113 Must be implemented within a 28 byte clock.

That is, in FIG. 1, the output of the additional data symbol processing unit 111 is converted from a symbol to a byte by the symbol-byte conversion unit 112, and then input to the unstructured Reed-Solomon encoder 113, which is the data interleaver. (108) Same as the data order of the output. However, the unstructured Reed-Solomon encoder 113 must encode a data segment corresponding to the input of the data interleaver 108. To this end, de-interleaving (inverse process of the interleaver) of the output of the symbol-byte conversion unit 111 must be performed to perform unsystematic Reed-Solomon encoding, which can not be implemented within 28 bytes because of a large processing delay.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the hardware size of an unstructured Reed-Solomon encoder for unstructured Reed-Solomon coding for additional data segments as much as possible while reducing the unstructured Reed-Solomon in a limited time. The present invention provides a digital VSB transmission system that performs encoding.

1 is a block diagram of a digital VSB transmission system according to the present invention;

FIG. 2 is a diagram illustrating an interleaving example of the data interleaver of FIG. 1. FIG.

3 is a view showing the output order of the data interleaver of FIG.

4 is a block diagram of a general regression syndrome calculator

5 is a block diagram of a non-regressive syndrome calculator according to the present invention

6 is a block diagram of a regression syndrome calculator according to the present invention

7 is a block diagram of an error value polynomial calculator according to the present invention

8 is a block diagram of a parity calculator according to the present invention

9 is a block diagram of an erasure Reed-Solomon decoder according to the present invention

Explanation of symbols for the main parts of the drawings

901: Syndrome Calculator902: Error Value Polynomial Calculator

903 Parity Calculator904 Parity Buffer

905 control unit

The digital VSB transmission system according to the present invention for achieving the above object, multiplexes the additional data and MPEG broadcast data converted to the format of the MPEG transport packet, and if the multiplexed data is the additional data segment, a plurality of parity positions After obtaining a holder, a parity position holder inserter inserting a null byte into the parity position holder, and performing data interleaving on the output of the parity position holder inserter, outputting a plurality of information bytes for each segment first, and then a null byte. A data interleaver for later outputting a plurality of inserted parity bytes, a parity replacer for replacing parity bytes output from the data interleaver with parity bytes obtained by unstructured Reed Solomon coding, and a parity byte having the null byte inserted therein. Error location A non-systematic Reed Solomon encoder configured to receive information bytes excluding the parity bytes through a parity substituter, perform unstructured Reed Solomon coding on the data interleaver input, recalculate parity bytes, and output the parity bytes to the parity substituter. Characterized in that it comprises a.

Preferably, the unstructured Reed Solomon encoder sets the parity byte into which the null byte is inserted as an error position, and performs error resolving by performing Reed Solomon decoding on information bytes except the parity byte into which the null byte is inserted. And an erasure reed solomon decoder that outputs two parity bytes.

The digital VSB transmission system includes a byte-symbol converter for converting an output of the parity replacement unit in symbol units, an additional data symbol processor for performing additional additional data processing on information bits of the additional data converted in symbol units; The apparatus may further include a symbol-byte converter configured to convert a symbol output from the additional data symbol processing unit into a byte unit and output the symbol to the unstructured Reed Solomon encoder.

Preferably, the unstructured Reed-Solomon encoder performs M (M is 20) syndromes while N (N is 187) information bytes of a specific segment are inputted only when the data output from the parity replacement unit is additional data. A syndrome calculator that calculates and outputs an error value polynomial calculator that calculates coefficients of M error value polynomials using the calculated M syndromes and a previously calculated error position polynomial, and a pony algorithm on the coefficients of the error value polynomial. The parity calculator calculates and outputs error values for the positions of the M parity position holders and outputs them as parity bytes, and the parity of M bytes calculated by the parity calculator is stored. 187 <= k1 <= 206) only if the corresponding parity byte is output to the parity replacement unit It is characterized in that it is configured to generate a signal indicating that the parity buffer, the required number in each sub-segment, the segment within the byte number, and additional data to the controller for output to the angle.

Preferably, the syndrome calculator and the parity buffer are operated with a byte clock, and the error value polynomial calculator and the parity calculator are operated with a symbol clock.

Preferably the syndrome calculator has 207 constants A rom that stores s, an address generator that receives segment number s and byte number k in the segment, and generates address 206-f (k, s) to read constants from the rom, and inputs one information byte of a specific segment. A multiplier for multiplying a constant output from the ROM each time, a multiplier for adding and receiving feedback of the multiplier's output and a stored value, and a register for storing the output of the adder and feeding it back to the adder. When the last byte of information is input, the output of the register as a syndrome is output to the error value polynomial calculator, wherein the syndrome calculator is configured as many as the number of syndromes to generate.

Preferably the syndrome calculator has 52 constants And the address is a ROM using the segment number s, and the first constant according to the selection signal. , The second constant Or a third constant output from the ROM Mux for selectively outputting any one of them, and if byte number k in a particular segment is 0 ≦ k ≦ 185 and f (k, s) ≦ 154 Otherwise If k = 186 A mux controller for generating a selection signal to select and outputting the mux controller to the mux, an adder that feeds back a stored value whenever an information byte of a specific segment is input, and a constant output through the mux output and the mux And a multiplier for multiplying and storing the register in the register. When the last information byte of the corresponding segment is input, the register of the register is outputted to the error value polynomial calculator as a syndrome, and the syndrome calculator is configured by the number of syndromes to be generated. It is characterized by.

Preferably, the error value polynomial calculator calculates an error value polynomial having M coefficients by multiplying the syndrome polynomial calculated using the syndrome and the error location polynomial, and the error location polynomial converts the M-byte parity position holder into an error location. It is set to be characterized in that it is calculated in advance.

Preferably the parity calculator is a constant Is a constant, and the address uses a segment number s, the first ROM storing 20 values for each 50 segments, and a constant. The second ROM stores an address using the segment number s and stores 20 values for each of the 50 segments, and the coefficients of the error value polynomial are sequentially inputted from the highest order. The MUX selects and outputs the constant stored in the first ROM only when the coefficient of the polynomial is input. Otherwise, the MUX selects and outputs the constant stored in the second ROM, and feeds back the stored value whenever the coefficients of the error value polynomial are sequentially input. A multiplier that adds and adds the multiplier and multiplies a constant output through the mux, and stores the result in the register. The coefficient of the last error value polynomial is input and operated, and the stored value is finally output as a parity byte. The parity calculator is characterized by the number of parity position holders required.

Preferably, when the input data is not an additional data segment, the parity position holder inserter performs systematic Reed Solomon encoding on the input data.

Preferably, the parity position holder inserter determines the parity byte position so that 20 parity bytes are output later than 187 information bytes at the output terminal of the data interleaver when the input data is an additional data segment. Null bytes are written, and 187 information bytes received are sequentially written to the remaining 187 information byte positions.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

In order to reduce the hardware size of the unstructured Reed-Solomon encoder as much as possible and have a minimum processing delay, the unstructured Reed-Solomon encoder receives the data corresponding to the output of the interleaver and performs encoding at the input of the interleaver. Do it. In other words, 187 information bytes corresponding to the output of the interleaver are input, and 20 parity bytes are calculated by performing unsystematic Reed-Solomon coding on the interleaver input.

A widely used (N, K) Reed-Solomon encoder uses a systematic Reed-Solomon encoder that receives K information bytes and outputs them as they are, plus 20 parity bytes. Where N is the total number of bytes in the sign, and K represents the number of information bytes therein. However, the Reed-Solomon code has the feature of generating the same code by using any K position among the N bytes as an information byte. In other words, the set of all codewords generated by the systematic Reed-Solomon coder and the set of all codewords generated by the unstructured Reed-Solomon coder using any K positions as information bytes. Is the same.

Therefore, since the codeword encoded by the unstructured Reed-Solomon coder for the additional data segment is a valid codeword of the systematic Reed-Solomon code, the error is not judged in the Reed-Solomon decoder in the existing 8T-VSB receiver. In the conventional 8T-VSB receiver, since the PID is transmitted so that the additional data segment is discarded, it is not a problem that the position of the information byte is different.

In the present invention, the non-systematic Reed-Solomon encoder is implemented using an erasure Reed-Solomon decoder. That is, if the remaining 20 parity bytes other than the information bytes among the 207 bytes are written as null bytes and the decoding is performed by erasure, 20 null bytes are error corrected to generate a valid codeword.

Thus, the 20 corrected bytes are equal to the parity bytes generated by the unstructured Reed-Solomon encoder.

On the other hand, a typical Reed-Solomon decoder operates as follows. While N bytes are input, N-K syndromes are calculated and an error locator polynomial is calculated using them. In Chien search, we find the root of an error location polynomial by finding the root of the error. The error evaluator polynomial is calculated using the calculated syndrome and the error location polynomial, and the error value is calculated using the Forney algorithm.

However, the erasure Reed-Solomon decoder used as an unstructured Reed-Solomon coder knows 20 error positions in advance. Therefore, in the general Reed-Solomon decoding process described above, it is not necessary to calculate the error position polynomial, and the Chien search process may be omitted.

Hereinafter, the erasure Reed-Solomon decoder, which is an unstructured Reed-Solomon encoder 113 to be used in the digital VSB transmission system of the present invention, operates as follows.

First, while 187 information bytes are input from the symbol-byte converter 112, the unstructured Reed-Solomon encoder 113 calculates 20 syndromes. The error value polynomial is then calculated using this calculated syndrome and the precomputed error location polynomial. Finally, 20 parity bytes are calculated using the Forney algorithm.

Calculation of syndrome

Assume that 207 bytes of the parity position holder inserter 107 output segment are R0, R1, ..., R206. Among them, 20 null bytes, which are parity position holders, are included. The segment may be expressed as a polynomial as shown in Equation 2 below.

Then, 20 syndromes for the segment are calculated by Equation 3 below.

In Equation 3 Is a primitive element of GF 256. When data is input to a general Reed-Solomon decoder in the order of R0, R1, ..., R206, the syndrome can be simply calculated as shown in FIG. This is because the syndrome in Equation 3 may be expressed in a recursive form as shown in Equation 4 below.

In FIG. 4, both the multiplier 405 and the adders 401 and 403 are operations on the GF 256, and when all 207 bytes are input, the values of the registers 402 and 404 finally stored become syndromes.

However, since the data input to the erasure Reed-Solomon decoder is reordered by the interleaver 108, the conventional syndrome calculator shown in FIG. 4 cannot be used. In this case, considering the output order of the interleaver 108 of Equation 1, the calculation of the syndrome of Equation 3 may be expressed as Equation 5 below.

Since the parity position holder byte is a null byte in Equation 3, the syndrome can be calculated using only 187 information bytes.

For example, consider the case where the first segment after the field sync segment is an additional data segment. The order in which the segments are changed by the interleaver 108 and input to the erasure Reed-Solomon decoder 113 corresponds to the case in which the segment number s = 0 in the above-described equation (1). Therefore, the order of 187 information bytes input to the erasure Reed-Solomon decoder 113 is R0 R52 R104 R156 R1 R53 R105 R157 ... R150. Syndrome in this case The equation is expressed by the following equation (6) by the equation (5).

There are two ways to implement Equation 6.

The first method calculates a syndrome by multiplying a corresponding constant each time 187 information bytes are input one by one. FIG. 5 is a block diagram of hardware implementation.

That is, the multiplier 505 is the first time R0 is input Multiply and store in register 507, then R52 is entered The result of multiplying is added to the register 507 by the adder 506 and stored in the register 507 again. Repeat this process until the last time R150 is entered The result of multiplying is added to the register 507 by the adder 506 and stored in the register 507 again. This is syndrome Becomes The constant to be multiplied in this way may be stored and used in a read only memory (ROM) 504.

In Figure 5 ROM 504 has 207 constants The address generator 503 receives the segment number s and the byte number k in the segment to generate an address 206-f (k, s) for reading a constant from the ROM 504. Thus, each syndrome The size of ROM 504 needed to compute is 207 bytes. Since 20 such syndromes are to be calculated, 20 syndrome calculators as shown in FIG. 5 must be implemented.

By the way, syndrome Since only the input data needs to be added, the number of multipliers 505 required by the syndrome calculator, 20 adders 501 and 506, and the memory size of the ROM 504 are 19 X 207 (= 3933) bytes.

On the other hand, the second method of calculating the syndrome is to modify the conventional regression syndrome calculator to calculate in a regression form. Representation of Equation 6 in a regressive form is shown in Equation 7 below, and FIG. 6 is a block diagram of the hardware.

That is, when the first byte R0 is input, the first byte R0 is added to the first byte R0 through the adder 608 and the multiplier 606. Multiply by and store in register 607. When the second byte R52 is input, the adder 608 adds it to the value stored in the register 607 and outputs the result to the multiplier 606. The multiplier 606 outputs the addition result. Multiply by and store in register 607 again. Repeating this process, when the last 187th byte R150 is input, the adder 608 adds it to the value stored in the register 607 and outputs the result to the multiplier 606. The multiplier 606 outputs the addition result. Multiply by and store in the register 607. The stored value is syndrome Becomes

By the way, when calculating the syndrome in a regression form, as shown in equation (7), the information byte The constant to be multiplied when is input is determined by Equation 8 below.

In other words, the multiplier 606 is the first information byte to the 186th byte (0 ≤ k ≤ 185), when f (k, s) is 154 or less Multiply by and Multiply by And in the last 187th information byte (k = 186) Multiply by Since the last constant to be multiplied depends on the segment number s, it can be stored and used in the ROM 605, and the size of the required ROM 605 is 52 bytes.

In FIG. 6, ROM 605 has 52 constants. Is stored, and the address uses the segment number s. The mux 604 selects one of the three constants described above, and the mux controller 603 controls the mux 604 by equation (8).

That is, if 0? K? 185 and f (k, s)? 154, 0 is generated, otherwise 1 is generated. And if k = 186, 2 is generated. When the mux 604 outputs 0 from the mux control unit 603 Select and output to the multiplier 606, and 1 is output. Is selected and output to the multiplier 606. And, if 2 is outputted, the constant output through the ROM 605 Is selected and output to the multiplier 606.

Meanwhile, since 20 such syndromes are to be calculated, 20 syndrome calculators as shown in FIG. 6 must be implemented. In this case, 19 multipliers 606 necessary for the syndrome calculator, 20 adders 601 and 608, and a memory size of the ROM 605 are 19 X 52 (= 988) bytes.

Therefore, the regression syndrome calculator of FIG. 6 has a smaller ROM size than the non-regression syndrome calculator of FIG. 5. to be.

On the other hand, since the data of a specific segment is not input continuously but mixed with the data of 52 segments, the syndrome calculator must have 20 bytes of syndrome memory for each of the 52 segments. The syndrome calculator receives an input byte, a corresponding segment number, a byte number in a segment, and a signal indicating that the input byte is a byte of an additional data segment, and operates only when the input byte is a byte of an additional data segment. In case of additional data segment, 20 bytes of syndrome memory corresponding to segment number of input byte is read and the input data is updated and stored, and the value is calculated when all 187 information bytes of a specific segment are input and the syndrome is calculated. Pass in a polynomial calculator.

Calculate Error Value Polynomial

The error value polynomial is calculated with a syndrome polynomial and an error location polynomial. However, as described above, since the 20-byte parity position holder is an error position, the error position polynomial may store and use values calculated in advance for 52 segments.

That is, the error position polynomial may be defined as in Equation 9 below.

In Equation 9 Is a value indicating an error position and is represented by the following equation (10) by substituting the position of the parity position holder.

Therefore, Equation 9 may be calculated as Equation 11 below by substituting Equation 10.

As can be seen from Equation 11, since the error position polynomial is different according to the segment number, 20 coefficients must be calculated for 52 segments. Thus, the memory size of the ROM required to store the coefficients of the error location polynomial is 52 X 20 (= 1040) bytes.

The syndrome polynomial is defined as shown in Equation 12 using the syndrome calculated previously.

Then, an error value polynomial can be obtained as shown in Equation 13 using the error position polynomials and syndrome polynomials of Equations 11 and 12.

That is, the error position polynomial and the syndrome polynomial need to be multiplied to calculate only the 19th term. In Equation 13, the coefficient of each term is calculated as in Equation 14 below.

In this case, in order to implement Equation 14 in a 1 byte clock, 190 multipliers and 190 adders are required. However, in order to reduce hardware, Equation 14 described above can be implemented with 19 multipliers and 19 adders. In addition, when Equation 14 is operated as a symbol clock, Equation 14 may be implemented as a 5-byte clock, 19 multipliers, and 19 adders. This is because the 4 symbol clock corresponds to the 1 byte clock.

7 illustrates a process of calculating an error value polynomial during a 20 symbol clock. First, when a 20 byte syndrome is calculated, the coefficient of the error position polynomial ( ) And all the values of the registers 702 of the lower 20 bytes are set to zero. The next 20 syndromes are inputted one by one into the 20-byte register 702, and the register value is shifted to the right. In FIG. 7, the sum of the left first register output of the register 702 and the outputs of the 19 multipliers is the coefficient of the error value polynomial ( ) 20 syndromes from The coefficients of the error value polynomial from Until all are calculated.

Calculation of parity

Finally, the parity of the unstructured Reed-Solomon encoder 113 is calculated using the Forney algorithm. According to the Forney algorithm, the error value for each error location is given by the following equation (15). In equation (15) Is an error location Error value corresponding to.

In Equation 15 Is the error location polynomial Is differentiating Is determined by the position of the parity position holder.

Thus, the error value May be calculated as shown in Equation 16 by substituting the position of the parity position holder in Equation 15, and FIG. 8 is a block diagram of hardware implementation.

Since the error location and the error location polynomial are already known in Equation 16, the following terms can be stored and used in the ROMs 801 and 802. Here, the ROM1 801 has a constant Is stored, and a constant as shown in Equation 17 is stored in the ROM2 802. The value stored in the ROM 801,802 depends on the number s of the segment.

In this case, since 20 values are to be stored for each of the 52 segments, the size of the required ROMs 801 and 802 is 52 X 20 (= 1040) bytes, respectively.

Therefore, the equation (16) can be calculated by substituting only the error value polynomial in the inverse of 20 error positions.

In this case, since the order of the error position polynomial is 19th order and has 20 coefficients, 19 X 20 (= 380) multipliers and 380 adders are needed to calculate the 1-byte clock. However, if we calculate this over 20 symbol clocks to reduce the hardware, we can only implement 20 multipliers and 20 adders. This is to calculate the value of the error value polynomial in a regression form as shown in Equation 18 below.

8, the coefficients of the error value polynomial are 20 clocks from Calculation of parity is performed while input up to. At this time, the mux 803 is a constant stored in the ROM1 (801) when the input selection signal is 0 Is selected and output to the multiplier 804, where 1 is a constant stored in ROM2 802. Is selected and output to the multiplier 804. The selection signal input to the mux 803 is the coefficient of the last error value polynomial. Is 1 only when is entered.

First, first coefficient Is input, the multiplier 804 receives a constant from ROM1 801 via mux 803. Read and multiply and store in the register 805. Second coefficient Is input, the adder 806 adds it to the multiplier 804 by adding it to the value of the register 805, and the multiplier 804 outputs the addition result to the constant of ROM1 801. Multiply by and store in the register 805. In this way Count up to the last coefficient Is added, the adder 806 adds it to the multiplier 804 by adding it to the value of the register 805, and the multiplier 804 outputs the addition result to the constant of ROM2 802 (the value of Equation 17). Multiply by and store in the register 805. The stored value finally becomes a parity byte.

On the other hand, since 20 parity needs to be calculated, 20 parity calculators as shown in FIG. 8 should be implemented. Thus, 20 multipliers, 20 adders, and 2 X 52 X 20 (= 2080) bytes of ROM are required to calculate 20 parity.

When 20 parity bytes are calculated in this way, they are transferred to a parity buffer so that the parity position holder of the interleaver output can be replaced.

9 is a hardware implementation of the erasure Reed-Solomon decoder described above, which includes a syndrome calculator 901, an error value polynomial calculator 902, a parity calculator 903, a parity buffer 904, and a controller 905. It is composed.

First, the syndrome calculator 901 obtains from the symbol-byte converter 112 the input data together with the corresponding segment number s2, the byte number k2 in the segment, and r2 indicating whether the input byte is the byte of the additional data segment. Receive input. The syndrome calculator 901 reads and updates the syndrome memory of the segment corresponding to s2 only when the input data is additional data.

When all 187 information bytes of a specific segment are input and finally the syndrome S (x) is calculated, the syndrome S (x) is transmitted to the error value polynomial calculator 902, and the corresponding segment number s3 is obtained. And start signal to start the operation of the next block. The error value polynomial calculator 902 has the received syndrome S (x) and when the calculation of the error value polynomial is completed, the result Is transmitted to the parity calculator 903, along with the corresponding segment number s3 and the start signal to start the operation of the next block. The parity calculator 903 loads (load) the result e _l After the calculation of the parity of 20 bytes to the parity buffer 904. Finally, the parity buffer 904 receives the segment number s1, the byte number k1 in the segment, and r1 indicating the byte of the additional data segment from the control unit 905, and is additional data only when 187 <= k1 <= 206. Outputs the corresponding parity byte.

In FIG. 9, the control unit 905 generates signals indicating that the segment number, the byte number, and the additional data are required by the erasure Reed-Solomon decoder. The data interleaver 905a of the controller 905 receives the segment number s corresponding to the input of the data interleaver 108 of FIG. 1, the byte number k in the segment, and r indicating that the additional data segment is included. Where s is a value from 0 to 51 and is represented by 5 bits, k is a value from 0 to 206, and is represented by 8 bits and r is represented by 1 bit.

Accordingly, the input of the data interleaver 905a used in the control unit 905 of FIG. 9 is 15 bits in total, and it operates in the same manner as the data interleaver 108 of FIG. 1 described above.

On the other hand, in the control unit 905, the delay unit 905b controls the control unit as much as the processing delay of the byte-symbol conversion unit 110, the additional data symbol processing unit 111, and the symbol-byte conversion unit 112 shown in FIG. It serves to delay the output of the data interleaver 905a of 905. The data interleaver 905a outputs s1, k1, r1 of the control unit 905 are input to the parity buffer 904, and the outputs S2, k2, r2 of the delay unit 905b are input to the syndrome calculator 901.

At this time, the Erasure Reed-Solomon decoder 113 should calculate parity within a 28 byte clock. In the above-described syndrome calculator 901, when all 187 information bytes are input, the syndrome is calculated and stored, and thus the processing delay is 1 byte clock. On the other hand, the error value polynomial calculator 902 and the parity calculator 903 can each calculate within one byte clock. However, in this case, since the size of the hardware increases, the operation is performed at 20 symbol clocks as shown in Figs. That is, one byte clock equals four symbol clocks, so a 20 symbol clock equals five byte clocks.

Accordingly, in the erasure Reed-Solomon decoder 113 of FIG. 9, the syndrome calculator 901 and the parity buffer 904 use the byte clock, and the error value polynomial calculator 902 and the parity calculator 903 use the symbol clock. If implemented, the erasure Reed-Solomon decoder can be implemented within a total of 11 bytes of clock, while at the same time reducing the size of the hardware.

Table 1 below shows the hardware size and processing delay required when using the regression syndrome calculator of FIG. 6, the error value polynomial calculator of FIG. 7, and the parity calculator of FIG. 8.

Multiplier Adder ROM Processing delay Syndrome calculator 19 20 988 bytes 1 byte clock Error value polynomial calculator 19 19 1040 bytes 5 byte clock Parity calculator 20 20 2080 bytes 5 byte clock Sum 58 59 4108 bytes 11 byte clock

As described above, the digital VSB transmission system according to the present invention has the following effects.

First, it maintains compatibility with existing ATSC 8T-VSB systems. That is, the additional data segment can be normally decoded in the Reed-Solomon decoder of the conventional ATSC 8T-VSB receiver.

Second, the hardware size of the unstructured Reed-Solomon encoder used in the digital VSB transmission system can be reduced.

Third, the unstructured Reed-Solomon coding used in the digital VSB transmission system can be performed within a limited time (eg, within a 28-byte clock).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (16)

In a digital VSB transmission system for multiplexing and transmitting additional data converted into a format of an MPEG transport packet and MPEG broadcast data, A parity position holder inserter for obtaining a plurality of parity position holders and inserting null bytes into the parity position holders if the multiplexed data is an additional data segment; A data interleaver for performing data interleaving on the output of the parity position holder inserter to output a plurality of information bytes for each segment first, and then output a plurality of parity bytes inserted with null bytes later; A parity replacer for replacing parity bytes output from the data interleaver with parity bytes obtained by unstructured Reed Solomon coding; And Set the parity bytes into which the null byte is inserted as an error position, receive information bytes except the parity bytes through a parity replacement unit, recalculate parity bytes by performing unstructured Reed-Solomon encoding at the data interleaver input. And a non-systematic Reed Solomon encoder output to the parity replacement unit. The method of claim 1, wherein the unstructured Reed Solomon encoder Eraser Reed Solomon that sets the parity byte into which the null byte is inserted as an error position, and outputs a plurality of error-corrected parity bytes by performing Read Solomon decoding on information bytes except the parity byte into which the null byte is inserted. A digital VSB transmission system, which is a decoder. The method of claim 1, A byte-symbol converter for converting the output of the parity replacement unit into symbols; An additional data symbol processing unit for performing additional additional data processing on the information bits of the additional data converted in the symbol unit; And a symbol-byte converter configured to convert the symbols output from the additional data symbol processing unit into byte units and output the converted symbols to the unstructured Reed Solomon encoder. The method of claim 1, wherein the unstructured Reed Solomon encoder A syndrome calculator for calculating and outputting M (M is 20) syndromes while N (N is 187) information bytes of a specific segment are inputted only when the data output from the parity substitution unit is additional data; An error value polynomial calculator that calculates coefficients of M error value polynomials using the calculated M syndromes and a previously calculated error position polynomial; A parity calculator for applying the pony algorithm to the coefficients of the error value polynomial to obtain error values for the positions of the M parity position holders and outputting them as parity bytes; Storing the parity of M bytes calculated by the parity calculator, and outputting corresponding parity bytes to the parity replacement unit only when the byte k1 in the segment satisfies the following condition (187 <= k1 <= 206). Parity buffers, And a controller for generating a signal indicating that the segment number, the byte number in the segment, and the additional data are required in each unit, and outputting the signal to the respective units. The method of claim 3, wherein The syndrome calculator and the parity buffer operate on a byte clock, and the error value polynomial calculator and the parity calculator operate on a symbol clock. The method of claim 3, wherein the syndrome calculator Digital VSB transmission system characterized in that to calculate the M syndromes by applying the following equation. Where mod is the remainder operation, s is the segment number, k is the byte number in the segment, and f (k, s) is the position of the byte in the segment. The method of claim 3, wherein the syndrome calculator 207 constants Rom that stores the, An address generator which receives the number s of the segment and the byte number k in the segment and generates an address 206-f (k, s) for reading constants in the ROM; A multiplier for multiplying a constant output from the ROM each time one information byte of a specific segment is input; An adder for adding feedback from the output of the multiplier and a stored value; And a register for storing the output of the adder and feeding it back to the adder. And when the last information byte of the corresponding segment is input, output the register as a syndrome to the error value polynomial calculator, wherein the syndrome calculator is configured as many as the number of syndromes to generate. The method of claim 3, wherein the syndrome calculator 52 constants And the address is a rom using the segment number s, First constant according to the selection signal , The second constant Or a third constant output from the ROM Select any one of the mux, If byte number k in a particular segment is 0 ≤ k ≤ 185 and f (k, s) ≤ 154 Otherwise If k = 186 A mux controller for generating a selection signal to select a mux and outputting the mux to the mux; An adder that feeds back a stored value whenever an information byte of a specific segment is input, A multiplier configured to multiply the output of the adder by a constant output through the mux and store the multiplier in the register, And when the last information byte of the corresponding segment is input, output the register as a syndrome to the error value polynomial calculator, wherein the syndrome calculator is configured as many as the number of syndromes to generate. The method of claim 3, wherein the error value polynomial calculator Syndrome polynomial S (x) and error position polynomial calculated using the syndrome Multiplying to calculate an error value polynomial having M coefficients, wherein the error location polynomial is calculated in advance by setting the M-byte parity position holder to the error location. 10. The method of claim 9, wherein the error location polynomial is Digital VSB transmission system characterized in that the calculation in advance by applying the following equation. here, Is the value indicating the error position, and is obtained by substituting the position of the parity position holder. 10. The method of claim 9, wherein the error location polynomial is A digital VSB transmission system characterized by calculating and storing coefficients of M error position polynomials for 52 segments because they differ according to the segment number. The method of claim 3, wherein the error value polynomial calculator A digital VSB transmission system comprising calculating coefficients of M error polynomials by applying the following equation. The coefficient of each term is calculated as follows. 4. The parity calculator of claim 3, wherein the parity calculator Each error location by applying the following formula Error value for Digital VSB transmission system, characterized in that to obtain a parity to obtain. here, Is the error location polynomial Is differentiating Is determined by the position of the parity position holder. 4. The parity calculator of claim 3, wherein the parity calculator a constant A first ROM for storing 20 values for every 50 segments, a constant A second ROM for storing 20 values for each of the 52 segments, The coefficients of the error value polynomial are input sequentially from the highest order ( ), Coefficient of last error value polynomial Mux for selectively outputting the constant stored in the first ROM only when is input, and otherwise outputting the constant stored in the second ROM, The coefficient of the error value polynomial from An adder that adds feedback to the stored values every time it is sequentially inputted, Multiplying the output of the adder by a constant output through the mux and storing the multiplier in the register; Coefficient of last error value polynomial Is inputted and calculated, and the stored value is finally outputted as a parity byte, and the parity calculator is required as many as the number of parity position holders. The method of claim 1, wherein the parity position holder insert And if the input data is not an additional data segment, systematic Reed Solomon encoding is performed on the input data. The method of claim 1, wherein the parity position holder insert When the input data is an additional data segment, the parity byte is positioned so that 20 parity bytes are output later than 187 information bytes at the output terminal of the data interleaver, and then a null byte is written at the determined parity byte position, and the remaining 187 information is stored. Digital VSB transmission system, characterized in that write the 187 information bytes received sequentially in the byte position.