KR20030023613A - Vacuum Package Fabrication of Microelectromechanical System Devices with Integrated Circuit Components - Google Patents

Abstract

A MEMS device vacuum packaging method comprising forming a plurality of MEMS devices 12 on a device wafer 10.

The first sealing ring 16 is formed surrounding one of the MEMS devices 12 and the associated mating pad 70. A plurality of integrated circuits 80 are formed on the lead wafer 30, each integrated circuit 80 having one or more associated mating pads 82 and one or more associated bonding pads 86. . A plurality of second sealing rings 32 are formed on the lead wafer 30 and each second sealing ring surrounds one of any integrated circuit device 80 and any associated bonding pads 82. The second sealing ring 32 is located between the boundary of the integrated circuit device 80 and the associated bonding pad 86. The sealing layer is formed on each of the first sealing ring 16 or each one of the second sealing ring 32. The device wafer 10 is paired with the lead wafer 30 in a vacuum environment to form a plurality of vacuum packages comprising one or more integrated circuits 80 and one or more MEMS devices 12. .

Description

Vacuum package fabrication of microelectromechanical system devices with integrated circuit components

Microelectromechanical Systems (MEMS) are integrated micro devices or systems that combine electrical or mechanical components. MEMS devices are fabricated using standard integrated circuit batch processing techniques at microscale. MEMS devices are used in many ways, including sensing, control and actuating at microscale. MEMS devices function separately or collectively on microscale to produce effects.

Many MEMS devices require a vacuum environment to achieve maximum performance. The vacuum package also provides protection and the best operating environment for MEMS devices. Examples of MEMS devices include inertial MEMS, such as bolometers, infrared MEMS, gyroscopes and accelerometers. Typically, MEMS devices are packaged one by one in a vacuum compatible package after manufacture and dicing. Often, MEMS device packaging costs 10 to 100 times the fabrication cost. Their high cost of packaging makes it difficult to develop commercially available vacuum packaged MEMS devices.

MEMS devices are particularly brittle after dicing. MEMS devices must be handled with care, and conventional integrated circuit manufacturing machinery cannot adequately protect or handle MEMS devices. Therefore, special handling techniques have been developed for protecting MEMS devices until vacuum packaging is complete. This special handling procedure will add to the additional production costs of the MEMS device.

TECHNICAL FIELD The present invention relates to integrated circuit fabrication, and more particularly, to a method of vacuum packaging a microelectromechanical system apparatus having integrated circuit components.

A more complete understanding of the invention and better features and advantages will be described with reference to the accompanying drawings.

1 is a plan view of a silicon wafer having a MEMS device according to the present invention;

FIG. 2 is a plan view of the silicon wafer of FIG. 1 for explaining a sealing ring surrounding each MEMS device on the wafer; FIG.

3 is a plan view of a single MEMS device for explaining the MEMS device, the associated bonding pad and the sealing ring around;

4 is a cross-sectional view of a single MEMS device to illustrate various layers of the MEMS device;

5 is a plan view showing a patterned side surface of a silicon lead wafer;

6 is a cross-sectional view of the silicon lead wafer of FIG. 5;

7 is a cross-sectional view of an apparatus wafer and a lead wafer to illustrate a mating process for creating a vacuum packaged MEMS device;

8 is a cross-sectional view of a lead wafer before forming spacers on each lead sealing ring;

9 is a cross-sectional view of a lead wafer after forming a spacer over each lead sealing ring;

10 is a configuration diagram showing a part of a lead wafer having a lead sealing ring and a spacer formed thereon;

11 is a plan view of a combination of the finished lead wafer and the device wafer after removing the lead wafer portion to expose the bonding pads in the wafer assembly to test the device;

12 is a configuration diagram of a MEMS device prepared for mating with another integrated circuit device;

13 is a configuration diagram of a semiconductor device prepared for mating with a MEMS device;

14 is a flow chart illustrating the basic steps involved in MEMS device vacuum packaging at the wafer level.

As mentioned above, there is a need for an improved method for vacuum packaging MEMS or similar devices with integrated circuits in a manufacturing process. According to the present invention, an improved method for vacuum packaging MEMS or similar devices with integrated circuits in a manufacturing process is provided to sufficiently reduce the problems or disadvantages associated with the method of vacuum packaging MEMS or similar devices.

According to one embodiment of the present invention, a MEMS device is evacuated comprising forming a plurality of MEMS devices on a device wafer where each MEMS device and any associated mating pads are surrounded by one of the plurality of first sealing rings. It provides a method for packaging. Next, a plurality of integrated circuits are formed on the lead wafer. Each integrated circuit device has one or more mating pads that positionally correspond with an associated mating pad coupled to the MEMS device to provide an electrical connection between the integrated circuit device and the MEMS device. Next, a plurality of second sealing rings are formed on the lead wafer, each second sealing ring surrounding one of the plurality of integrated circuit devices and one or more mating pads coupled to the integrated circuit device. . Each of the plurality of second sealing rings is located between the boundary of the integrated circuit device and one or more bonding pads coupled to the integrated circuit device. Next, the sealing layer is formed on either one of each of the plurality of first sealing rings or each of the plurality of second sealing rings. The device wafers are then paired with the lead wafer in a vacuum environment to form a plurality of vacuum packages comprising one or more integrated circuits and one or more plurality of MEMS devices.

The present invention provides various advantages over conventional vacuum packaging methods. One of the technical advantages of the present invention is that a vacuum packaging process is involved in the MEMS device fabrication process. Another technical advantage is the elimination of individual die handling and individual MEMS vacuum packaging processes. Another advantage of the present invention is that all MEMS devices on silicon wafers are vacuum packaged at one time during device manufacturing, thereby significantly reducing the cost of vacuum packaging MEMS devices. The reduction in cost results in the development of commercially available MEMS devices. Another advantage of the present invention is that it is protected at an early stage in which the MEMS device is manufactured. Another advantage of the present invention is that it is possible to use conventional integrated circuit handling methods after the MEMS device is vacuum packaged and diced. Another advantage of the present invention is that all MEMS devices can be tested using the test procedures of conventional integrated circuits after vacuum packaging but before dicing. Other advantages will be apparent to those skilled in the art.

Infrared Microelectromechanical Systems and other inertial MEMS devices require a vacuum environment for maximum performance. For example, infrared microbolometers require an operating pressure of less than 10 millitorr to minimize thermal transfer from the detector element to the substrate and package wall. Therefore, vacuum compatible material handling and equipment should be used. Infrared devices also require optically transparent covers. Packaging requirements present a serious cost barrier to commercially available MEMS devices and require high cost and high effort. The cost of packaging a MEMS device is typically 10 to 100 times the cost of a basic device manufacturing process.

The solution to the high packaging cost is to eliminate the individual vacuum packaging process of conventional complete dies. According to the invention, this is accomplished by moving the packaging step into the wafer fabrication process. The lead wafer is aligned and mounted on the device wafer with sealing rings by annular solder or other sealing material and forms a sealed cell at each die position. The lead attach process is completed in a vacuum environment and places each MEMS device in a vacuum cell. The interconnect is made by solder sealing and disconnected by the dielectric layer.

Referring to FIG. 1, a silicon device wafer (Device Wafer) is generally represented by 10. The silicon device wafer 10 is a standard substrate used in the manufacture of integrated circuit devices, MEMS devices, or the like. However, any suitable substrate material may be used. For example, a substrate material incorporating a reader of an integrated circuit can be used as the device wafer. Silicon device wafers having multiple MEMS devices 12 are generally formed using conventional integrated circuit fabrication methods. Although embodiments of the present invention are discussed in terms of vacuum packaging for MEMS devices, the method may be used for the vacuum packaging of any integrated circuit device or similar device formed in substrate fabrication and included in a vacuum package. Each MEMS device 12 generally has one or more associated bonding pads 14. In FIG. 1, each MEMS device 12 has two associated bonding pads 14. Although embodiments of the present invention have been discussed in terms of having bonding pads on one side of the MEMS device 12, the bonding pads may be one or more of the MEMS device 12 depending on the particular application and design of the MEMS device 12. May exist on the side. As above, MEMS device 12 may be another micro device or MEMS device that benefits from a vacuum package and is formed on a suitable substrate. The term microdevice is used herein to refer to devices including integrated circuit devices, MEMS devices, or similar devices.

Referring to FIG. 2, device wafer 10 has MEMS device 12 and associated bonding pads 14. In order to create a separate vacuum package for each MEMS device 12 on the device wafer 10, sufficient space must be ensured to place the sealing ring 16 around each MEMS device 12. The sealing ring 16 delimits the vacuum package around the MEMS device 12. Although embodiments of the invention are discussed in terms of one MEMS device 12 or micro device per vacuum package or vacuum cell, one or more in one vacuum cell, depending on the requirements, functionality and design of the desired device. Micro devices may be included.

Referring to FIG. 3, a single MEMS device 12 is described to fully represent the structure for the device wafer 10. A lead 18 connects the MEMS device 12 and the bonding pad 14. Space is left to form the sealing ring 16 between the MEMS device 12 and the bonding pads 14. The lead 18 is formed at the bottom of the manufacturing layer formed inside the sealing ring 16. Since the sealing ring 16 defines the area of the device wafer 10 on which the vacuum package is to be formed, the sealing ring 16 is electrically connected to the bonding pad 14 without affecting the vacuum seal present around the MEMS device 12. The connection is made.

Referring to FIG. 4, an embodiment of a single MEMS device 12 to be included inside a vacuum package is described.

The device wafer 10 includes a silicon dioxide layer 20 that is deposited or grown on the surface prior to fabrication of the MEMS device 12. Leads 18 on one side of MEMS device 12 allow for bonding to bonding pads 14. While embodiments of the present invention have been described as having leads on one side of MEMS device 12, leads 18 may be present on one or more sides of MEMS device 12. As shown in FIG. Sufficient space is provided between the MEMS device 12 and the bonding pad 14 to produce a sealing layer for the sealing ring.

The bonding pad 14 may be composed of a metal or metals suitable for forming an electrical connection after being attached. In one embodiment, the first layer of bonding pad 14 is made of titanium, the second layer is made of palladium, and the last layer is made of gold. Since the bonding pads 14 are deposited on the leads 18, a solder based layer for the bonding pads 14 may not be needed. Bonding pads are manufactured with the MEMS device 12 and discussed only for completeness of the description. Bonding pads are not part of the vacuum packaging process.

Although the formation of a sealing ring 16 surrounding a single MEMS device 12 will now be described, all MEMS devices 12 on the device wafer 10 have a sealing ring that is formed simultaneously. A dielectric layer 22 is formed at the first stage of manufacturing a sealing ring 16 (not shown) using integrated circuit fabrication techniques. Preferably, dielectric layer 22 is formed of silicon nitride, but any suitable insulator may be used. Dielectric layer 22 provides electrical isolation for leads 18.

Solder adhesion layer 24 is formed on dielectric layer 22 as the next step in completing sealing ring 16. The solder attachment layer 24 is made of titanium, the middle layer of palladium, and the third layer of gold. However, multiple metals or combinations of metals may be used in the manufacture of the solder adhesion layer 24. The solder adhesion layer 24 may be deposited simultaneously with the bonding pads 14. Although the sealing ring 16 is described as utilizing a thermally activated solder, a compression seal, such as an indium compression seal, may be used. If compression seals are used, solder adhesion layer 24 is not formed over dielectric layer 22. At this point, the manufacture of the sealing ring 16 on the device wafer 10 is complete. Every MEMS device 12 on the device wafer 10 has a sealing ring 16 ready to receive a package lead Lid sealed with a heat activated solder.

5 is a diagram illustrating a silicon lead wafer 30.

Although the silicon wafer is used as the substrate of the lead wafer 30 in the preferred embodiment, other materials suitable as the substrate may be used. The lead wafer 30 includes a plurality of lead sealing rings 32 corresponding to the number of sealing rings 16 on the device wafer 10. Each lead sealing ring 32 is a mirror image of the sealing ring 16 such that the device wafer 10 and the lead wafer 30 are paired. Cavity 34 and bonding pad channel 36 are etched in lead wafer 30 using a suitable process, such as a wet or dry etch. Etching the cavity 34 and bonding pad channel 36 may include deposition of silicon nitride and patterning of the silicon nitride layer to form a suitable etch mask. Orientation dependent etching or other suitable treatment is then used to form the cavity 34 and bonding pad channel 36. The silicon nitride layer may be removed before the sealing ring 32 is deposited. Each of the cavities 34 is surrounded by a lead sealing ring 32. The function of the cavity 34 increases the volume for the MEMS device 12 being vacuum packaged. As described below, the increased volume for the vacuum packaged MEMS device 12 provides a higher vacuum level in the vacuum cell. In some embodiments of the present invention that do not require high vacuum, the cavity 34 is optional. The function of the bonding pad channel 36 is that the bonding pad 14 may be used at a later stage, such as a dicing saw, etching process or other suitable process to open the lead wafer to reveal the bonding pad for device testing prior to dicing the wafer. To provide clarity.

6 is a diagram illustrating a part of a cross section of the lead wafer 30. Lead sealing ring 32 is fabricated on lead wafer 30 to pair with sealing ring 16 on device wafer 10. An etching process or other suitable procedure is used to etch the surface of the lead wafer 30 and creates a cavity 34 and a bonding pad channel 36. The etching process includes a lead wafer corresponding to each of the bonding pad channel 36 of the lead wafer 30 corresponding to each of the rows of bonding pads 14 on the device wafer 10 and the MEMS device 12 on the device wafer 30 ( Create a cavity 34 of 30).

An alternative process of patterning the lead wafer 30 involves forming a window wafer and then bonding to the lead wafer. The window wafer may be formed by fully etching the cavity 34 and bonding pad channel 36 throughout the wafer and bonding to the unetched lead wafer 30. This process provides a smooth surface in the bonding pad channel 36 and cavity 34 when coupled to the lead wafer 30.

Another alternative process for patterning the lead wafer 30 involves etching the entire surface of the lead wafer, leaving the lead sealing ring 32 raised above the surface. The entire surface of the lead wafer 30 except for the lead sealing ring 32 is etched to a predetermined depth. The finished layer of lead wafer 30 excludes the pre-calculated depth etched lead sealing ring 32.

Light coating is required for the surface of the lead wafer 30 for the best performance of the MEMS device 12. If the MEMS device 12 is an infrared detector or other optical device, it is applied to the outer surface of the antireflective lead wafer 30. In addition, the cavities 34 of the lead wafer 30 may be coated by the antireflective coating 37.

The cavity 34 appears in the area of the lead wafer 30 directly above the MEMS device 12 when fabrication is complete to create a package for the MEMS device 12. The cavity 34 can be 0.5 to 0.75 millimeters deep. By etching the cavity inside the lead wafer 30 corresponding to the upper region of the individual MEMS device 12, the smaller for the interior of the individual package created by the combination of the device wafer 10 and the lead wafer 30. The surface to volume ratio is obtained. This small surface to volume ratio results in a small internal pressure inside the vacuum packaged MEMS device 12. Since pressure is proportional to the number of molecules per single volume, the pressure is reduced by increasing the volume for a given number of molecules.

After the lead wafer 30 is formed, a solder adhesion layer 38 is deposited to form the lead sealing ring 32. As mentioned above, the solder adhesion layer 38 is not needed in a method where no heat activated solder is used. In a preferred embodiment, since the thermally active solder is used, the lead solder adhesion layer 38 is deposited to form the lead sealing ring 32. The lead solder adhesion layer 38 is composed of any metal alloy or combination of metals that provides a stable attachment to the wettable surface and the device wafer 10 by the solder. Preferably, the lead solder adhesion layer 38 is made of titanium, the middle layer of palladium, and the outer layer of gold.

Solder layer 40 is deposited over lead solder adhesion layer 38. If a sealing method other than thermally active solder is used, the solder layer 40 is replaced with a material capable of obtaining a vacuum tight seal. In another embodiment, Indium crimping seals are used. However, in the preferred embodiment, a thermally active solder layer 40 is used. Solder layer 40 may be deposited through conventional integrated circuit fabrication techniques or other suitable deposition process. For example, it generates a solder layer 40 that is electroplated and deposited onto the lead solder adhesion layer 38. Another method for depositing the solder adhesion layer 38 includes using an electroless plate method. Another method of depositing the solder layer 40 uses vacuum deposition. The method of depositing another solder layer 40 includes using a preformed and prepunched solder layer that is aligned and attached on the lead solder layer 38. Any suitable deposition method may be used, including spot welding the preformed and punched solder layer to the lead solder adhesion layer 38. In another method of depositing the solder layer 40, a solder ball method may be used to deposit the solder layer 40. The solder ball method involves creating a template having a plurality of discrete holes to which solder must be deposited. The template with solder inside the hole is aligned and placed on the lead wafer 30. Solder balls are released from the template and attached to the lead solder adhesion layer 38. When the lead wafer 30 is heated to an appropriate level, the solder balls melt and form a continuous solder layer 30. Solder layer 40 may be comprised of a suitable material, such as indium compression seal, indium solder, metal solder, metal alloy solder, or solder balls. Although the solder layer 40 is deposited on the lead solder adhesion layer 38 in the preferred embodiment, it is also possible for the solder layer 40 to be deposited on the solder adhesion layer 24 on the device wafer 10.

FIG. 7 shows an assembly 50 comprising a lead wafer 30 and an apparatus wafer 10 ready for final assembly before being placed in a vacuum furnace (not shown in the figure). To prepare the assembly 50 for placement into the vacuum furnace, the lead wafer 30 is placed in the assembly holder (not shown) with the solder layer 40 facing up. The device wafer 10 is aligned on the lead wafer 30 such that the sealing ring 16 is aligned on the corresponding lead sealing ring 32. If a solder layer 40 is deposited on the solder adhesion layer 24 on the device wafer 10, the device wafer is placed in the bond holder with the solder layer 40 facing up, and the lead wafer 30 is placed on the device. Aligned above the wafer 10. The lead wafer 30 and the device wafer 10 are fixed by alignment at intervals so that gases on all surfaces can be released. The spacing is 2 millimeters. The assembly 50 therefore comprises a device wafer 10 and a lead wafer 30 that are aligned with the assembly holder at intervals that enable gas release. The gap supports more complete discharge of each vacuum cell, thereby providing a high level of vacuum in the vacuum packaged MEMS device 12.

The assembly 50 is located in the vacuum furnace. The vacuum furnace is discharged to a minimum pressure level of approximately 2 x 10 ^-7 torr. The vacuum furnace is heated up to just below the melting point of the solder layer 40. For example, if the melting point of the solder layer 40 is 280 ° C, the vacuum furnace is heated to approximately 275 ° C. The vacuum furnace temperature depends on the melting point of the solder layer 40. The combination 50 must be retained in the vacuum furnace for a period of time sufficient for gas release of all surfaces. This period can be approximately several hours. The retention period is determined by the final vacuum pressure required in the vacuum packaged MEMS device.

After gas release of all surfaces is complete, the vacuum furnace temperature is raised to the melting point of the solder layer 40. When the solder layer 40 melts, external gas release of the solder is allowed for a short time, and the device wafer 10 creates a vacuum seal between the lead sealing ring 32 and the sealing ring 16 and the lead wafer 30 ). Therefore, all MEMS devices 12 on the device wafer 10 are currently sealed in a vacuum package.

If the sealing layer 40 is not thermally active, a vacuum chamber may be used instead of the vacuum furnace to provide a suitable vacuum environment. In this situation, melting of the solder layer 40 is not necessary. Force may be required to seal the device wafer 10 and the lead wafer.

When the device wafer 10 is in contact with the lead wafer 30, a solder layer 40 of non-uniform thickness is caused. Uneven solder thickness can result in large losses of the MEMS device 12 vacuum packaged by cracks in the solder layer 40 resulting in a loss of vacuum in the vacuum cell. 8, 9, and 10 illustrate controlling the solder thickness to keep the solder thickness of all MEMS devices 12 uniform over the assembly 50. By keeping the solder thickness uniform, a suitable vacuum chamber and a suitable vacuum will be present for each vacuum packaged MEMS device 12 on the device wafer 10.

FIG. 8 shows the lead wafer 30 after the cavity 34 and the bonding pad channel 36 are etched leaving a lead sealing ring 32 surrounding each cavity 34. As already mentioned, the cavities 34, bonding pad channels 36, silicon nitride 102 are deposited on the surface of the lead wafer 30 and patterned for etch mask formation. Direction dependent etch or other suitable processing is used to form the cavities 34 and bonding pad channels 36 having the configuration of the lead wafer 30 of FIG. 8.

FIG. 9 shows a lead wafer 30 having spacers 100 formed on the lead sealing ring 32. Silicon nitride layer 102 is patterned and etched using any suitable etching process to form a small island of material defining spacer 100. The small island of silicon nitride layer 102 is approximately 20 microns in diameter. The number of silicon nitride 102 islands formed on the lead sealing ring 32 is determined to ensure the minimum thickness of the solder layer 40 on all the lead sealing rings 32. The lead wafer 30 applies direction dependent etching or other suitable patterning technique to form the spacer 100 over the lead sealing ring 32. Nitride may still remain on each of the spacers 100. However, the silicon nitride layer can be removed if necessary.

FIG. 10 shows a portion of lead wafer 30 after it has been patterned and etched to form cavity 34, lead sealing ring 32, and spacer 100. The cavity 34 is the region which is etched most deeply on the lead wafer 30. The upper and circumference of the cavity 34 is the lead sealing ring 32. The spacer 100 is positioned on the lead sealing ring 32. The spacer 100 is designed to ensure a uniform thickness of solder that will be present on the lead sealing ring 32 after the lead wafer 30 and the device wafer 10 are paired. After the space 100 is formed on the lead wafer 30, the lead sealing ring 32 is prepared with the solder layer 40 and the solder adhesion layer 38 as described with reference to FIGS. 6 and 7. . Spacer 100 is positioned in lead sealing ring 32 to evenly produce the thickness of the solder. The spacer 100 is approximately 5 to 20 microns high. Other suitable procedures for forming the spacer 100 may be used, including attaching a small dot material, such as silicon, to the surface of the lead sealing ring 32 rather than etching the surface of the lead sealing ring 32. have. Although the process of forming the spacer 100 is discussed in connection with the vacuum packaging of the MEMS device 12, the spacer 100 may be any wafer level packaging process in which the device wafer is paired with the lead wafer, regardless of the underlying components or devices. Can be included.

When the heated combination 50 is cooled, there is a subsequent outgassing at the surface, thereby raising the pressure level inside the vacuum packaged MEMS device 12. In order to minimize subsequent gas release of the surface within the vacuum packaged MEMS device 12, the binder 50 is cooled at a rate that minimizes subsequent gas release of the surface while minimizing thermal stress energy for the assembly. Thermal stress is caused by cracks, thereby damaging the density of the vacuum package. The desired vacuum (lowest) pressure level in the MEMS device 12 vacuum packaged by rapid cooling of the assembly 50 is achieved. In addition, as discussed above, the cavity 34 reduces the surface to volume ratio inside the vacuum packaged MEMS device 12, resulting in a decrease in pressure. The cavity 34 makes the vacuum packaged MEMS device 12 inside the package more resistant to subsequent gas release of the surface. According to the invention, lower pressure levels are possible but pressure levels as low as 5 millitorr have been achieved. By minimizing the vacuum pressure, the performance of a particular MEMS device is maximized. Infrared microbolometers, for example, require an operating pressure of less than 10 millitorr to minimize heat transfer from the sensor element to the substrate or package wall.

In FIG. 11, a probe channel 54 is formed in the lead wafer 30 by removing the lead wafer 30 over the bonding pad channel 36. After the probe channel 54 is formed in the lead wafer 30, the bonding pads 14 are accessible through the probe channel. The vacuum package region 52 represents an area between the lead wafer 30 and the device wafer 10 in which the vacuum package is present. Within each vacuum package region 52 is one or more MEMS devices 12. Preferably the probe channel 54 is formed by Sawing the channel through the lead wafer 30 on the bonding pad channel 36 which has already been etched. In addition, the probe channel 54 may be formed by an etching process or other suitable technique.

The bonding pads 14 are exposed after the probe channels 54 are formed in the lead wafer 30. The bonding pads 14 are each MEMS device 12 packaged under vacuum on the device wafer 10 using a conventional integrated circuit bulk testing process that probes each bonding pad 14. Can be used to test An important advantage of the present invention is that the vacuum packaged MEMS device 12 can be tested at the wafer level, thereby minimizing the cost for verifying complete operation of each of the vacuum packaged MEMS devices 12.

After testing the MEMS device 12, the device wafer 10 is diced by cutting through the probe channel 54 between the bonding pads 14. In addition, the dicing saw travels between all vacuum package regions 52. Cutting of the assembly 50 can be completed using conventional methods of cutting silicon wafers with completed integrated circuits. By vacuum packaging the MEMS device 12 at the wafer level, conventional integrated circuit handling methods can be used since the vacuum package can provide protection for the fine MEMS device 12.

The finished die representing the vacuum packaged MEMS device 12 may be mounted by a chip-on-board method or by injection molding into a plastic package. In addition, the completed die may be located in a non-vacuum package along with other components.

12 and 13 illustrate another embodiment of the present invention that allows device wafers with MEMS device 12 to be paired with lead wafers containing other semiconductor devices. After fabrication of Complementary Metal Oxide Semiconductor (CMOS), CMOS circuits cannot be exposed to temperatures above approximately 400 ° C. This temperature limit can be applied to other integrated circuit (IC) devices. MEMS manufacturing techniques are frequently used at temperatures in excess of 400 ° C. Therefore, when manufacturing a MEMS device on a wafer using a CMOS device, the available MEMS fabrication techniques are much limited. One solution to this problem is to manufacture the CMOS device and MEMS device separately so that the CMOS device is not exposed to temperatures above 400 ° C. The MEMS die and the CMOS die are then placed in a package and electrically connected. This process requires expensive individual die handling.

In an alternative embodiment of the invention, the MEMS device is fabricated on a device wafer and the CMOS device is fabricated on a lead wafer. These wafers are sealed together in a vacuum to produce a wafer with multiple vacuum packaged MEMS / CMOS devices. One advantage of this alternative embodiment is that the MEMS device can be produced without the limitation of processing. Another advantage is that wafer loss during MEMS device fabrication does not result in loss of the fully fabricated IC wafer. Because the alternative embodiment uses a CMOS or other IC device formed on the lead wafer, the alternative embodiment is not suitable for use with MEMS devices that require optically transparent lids. An example of a MEMS device that benefits from the replacement process is a mechanical MEMS device that is connected to a CMOS device or other IC device to form a complete and operable device. Although an alternative embodiment will be discussed in which a single MEMS device 12 and a single CMOS organ are vacuum packaged together, one or more MEMS devices 12 and one or more CMOS devices are inside a single vacuum packaged die. Can be merged into In addition, wafer fabrication design does not require that all MEMS devices be packaged with CMOS devices. For example, half of the die produced is a vacuum packaged device with only MEMS, while the other half is a vacuum packaged device with MEMS / CMOS.

12 shows a portion of a device wafer 10 with a MEMS device 12. A typical device wafer 10 has a number of MEMS devices 12. One or more mating pads 70 couple with the MEMS device 12 via leads 72. The mating pad 70 is used to provide an electrical connection between the MEMS device 12 and the CMOS or other integrated circuit (IC) on the lead wafer. The mating pad 70 is located within an area composed of a solder adhesion layer and bounded by the sealing ring 16 as described for the bonding pad 14, and therefore within the resulting vacuum package. The sealing ring 16 is prepared to be paired with the lead sealing ring on the lead wafer 30 as described above. Therefore, the sealing ring 16 includes a solder adhesion layer deposited and formed thereon. The alternative embodiment does not use a bonding pad coupled to the MEMS device 12 to provide electrical connection to the finished vacuum packaged die, thus eliminating the need for a dielectric layer for the sealing ring 16. The area bounded by the sealing ring 16 represents the area inside the vacuum package. It should be noted that an empty space is left inside the vacuum region to accommodate the CMOS or other IC device formed on the lead wafer 30.

FIG. 13 is a view showing a portion of the lead wafer 30 in which the CMOS or other IC device 80 is formed. The lead wafer 30 has a plurality of CMOS devices. The lead sealing ring 32 is defined as an area for forming the lead solder adhesion layer 38 as described above. One or more lead mating pads 82 are fabricated on the lead wafer. The lead mating pad 82 is a mirror image of the mating pad device 70, and the mating pad 70 and the lead mating pad 82 are properly aligned when the device wafer 10 and the lead wafer 30 are properly aligned. ) Can provide electrical connection between MEMS device 12 and CMOS device 80.

The lead mating pad 82 is connected to the CMOS device 80 through the lead 84. As described with reference to bonding pad 14, lead mating pad 82 is comprised of a solder adhesion layer. One or more package bonding pads 86 are connected to the CMOS device 80 through the leads 88 for each CMOS device 80 on the lead wafer 30. The lead 88 runs under the lead sealing ring 32. As described above with reference to the sealing ring 16, the lead sealing ring 32 is electrically insulated between the lead sealing 88 and the solder seal formed by the sealing ring 16 and the lead sealing ring 32. It has a silicon dioxide layer to provide it. Package bonding pads 86 provide electrical connections for vacuum packaged devices. As described above, the lead sealing ring 32 includes a solder layer deposited over the lead solder adhesion layer. However, the solder layer may be deposited on either the properly prepared sealing ring 16 or the lead sealing ring 32.

A solder layer is also deposited on either the mating pad 70 or the lead mating pad 82 so that a permanent electrical connection can be made when the device wafer 10 is paired with the lead wafer 30. The solder is any suitable metal or metal alloy. As a more complete gas release of the surface will occur, a low degree of vacuum in the vacuum packaged MEMS device 12 is expected for the solder with high melting point. For solders with low melting points, vacuum packaging by applying the solder to the lead wafer 30 and separately heating the device wafer 10 to a temperature above the melting point of the solder to obtain full surface gas emissions of the device wafer 10. The degree of vacuum inside the MEMS device 12 is improved. The temperature resistance of the desired lead wafer 30 and the vacuum level in the completed vacuum packaged MEMS device 12 determine the type of solder used, the temperature of the furnace, and the vacuum level of the furnace.

After the MEMS device 12 is fabricated on the device wafer 10 and the CMOS device 80 is fabricated on the lead wafer 30, the lead wafer is placed in the binder holder and the device wafer is aligned on the lead wafer. If the mating process uses a furnace temperature that will not damage the CMOS device 80 on the lead wafer 30, the device wafer and lead wafer 30 combination will be paired using the previously described procedure. The device wafer 10 must be heated individually if the temperature of the furnace uses a furnace temperature that can damage the CMOS device 80 on the lead wafer 30. The device wafer 10 is aligned with the lead wafer and produces the vacuum packaged MEMS device 12 by contacting the two wafers in a vacuum environment. After the finished assembly has cooled, the Probe Access Channels are opened over the package bonding pads so that the vacuum packaged MEMS device 12 can be tested utilizing a bulk IC testing process (in this case, Through the device wafer 10). After all the dies on the finished assembly have been tested, the finished assembly is cut into individual dies.

As with the preferred embodiment, if a high vacuum level is required in the vacuum packaged MEMS device 12, certain areas of the device wafer 10 are etched to provide cavities that increase the surface to volume ratio of the vacuum package result.

14 illustrates a process involved in vacuum packaging integrated circuit components in a manufacturing process. In step 200 a number of MEMS devices are formed on the device wafer 10. In step 202 a dielectric layer 22 is formed between the periphery of each MEMS device 12 and the associated bonding pads 14. Dielectric layer 22 forms a continuous ring surrounding MEMS device 12. In addition, an inherent dielectric layer within the structure of the MEMS device 12 may be used. In step 204 a sealing ring is formed over the dielectric layer 22. The sealing ring 16 may include a lead solder adhesion layer to facilitate mating of the device wafer 10 with the lead wafer 30 using thermally active solder. In step 206 a plurality of lead sealing rings 32 are formed corresponding to the number and position of the sealing rings 16. In step 208 a sealing layer is formed over each lead sealing ring 32. The sealing layer is composed of a thermally active solder, but may be composed of other suitable sealing materials. If the MEMS device 12 has a support layer for any moving ports of the MEMS device 12, the support layer is removed by an etching process prior to proceeding to step 210.

In step 210 the device wafer 10 is aligned with the lead wafer 30. After alignment, each sealing ring 16 is aligned with the corresponding lead sealing ring 32. In step 212 the device wafer 10 is paired with the lead wafer 30 in a vacuum to create a plurality of MEMS devices 12 that are vacuum packaged. Each MEMS device 12 vacuum packaged in step 214 is tested using a conventional integrated circuit test procedure. To facilitate testing, the probe access channel is opened over a bonding pad 14 coupled to a vacuum packaged MEMS device 12. The assembly completed in step 216 is cut using a technique for cutting conventional integrated circuits.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Claims (55)

A method for packaging a MEMS device in vacuum, Forming a plurality of MEMS devices on the device wafer; Forming a plurality of first sealing rings surrounding both one of the plurality of MEMS devices and one or more mating pads selectively coupled to the MEMS devices; One or more mating pads that respectively correspond to one or more mating pads selectively coupled to the MEMS device to enable selective electrical connection of the CMOS or other integrated circuit device to the selected MEMS device. Forming a plurality of CMOS or other integrated circuit devices having a lead wafer; Each surrounding one of the plurality of CMOS or other integrated circuit devices and the one or more mating pads of the CMOS or other integrated circuit device, the boundaries of the CMOS or other integrated circuit device and the CMOS or other integrated circuit. Forming a plurality of second sealing rings on the lead wafer positioned between one or more bonding pads coupled to the device; Forming a sealing layer on each of the plurality of first sealing rings or on each of the plurality of second sealing rings; And The device wafer in a vacuum environment to create a vacuum package including one or more plurality of MEMS devices and one or more CMOS or other integrated circuit devices within each of the plurality of first and second sealing rings; And pairing the lead wafers. The method of claim 1, wherein the forming of the plurality of first sealing rings comprises first forming a dielectric layer surrounding both one of the plurality of MEMS devices and one or more mating pads coupled to the MEMS device. Way. 3. The method of claim 2, wherein forming the plurality of first sealing rings comprises forming a solder adhesion layer on each of the plurality of dielectric layer rings. The method of claim 3, wherein the forming of the plurality of solder adhesion layers comprises: Depositing a titanium layer; Depositing a palladium layer on the titanium layer; And Depositing a gold layer over the palladium layer. The method of claim 1, wherein pairing the device wafer and the lead wafer comprises: Aligning the device wafer and the lead wafer to align the plurality of first sealing rings and the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; Positioning the aligned device wafer and lead wafer in a vacuum furnace; Creating a vacuum in the vacuum furnace; And Sealing the gap between the device wafer and the lead wafer to bring the plurality of first sealing rings and the plurality of second sealing rings into contact with one or more of the plurality of MEMS devices and one or more CMOS or other integrated circuit devices. Generating a plurality of vacuum packages comprising a. The method of claim 1, wherein pairing the device wafer and the lead wafer comprises: Aligning the device wafer and the lead wafer to align the plurality of first sealing rings and the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; Positioning the aligned device wafer and lead wafer in a vacuum furnace; Creating a vacuum in the vacuum furnace; Releasing gas in the surface region of the device wafer and lead wafer assembly by heating the vacuum furnace to a temperature sufficient to release gas on the surfaces of the device wafer and lead wafer; Sealing the gap between the device wafer and the lead wafer to bring the plurality of first sealing rings and the plurality of second sealing rings into contact with one or more of the plurality of MEMS devices and one or more CMOS or other integrated circuit devices. Generating a plurality of vacuum packages comprising; And Cooling the finished device wafer and lead wafer assembly at a predetermined rate to minimize the release of subsequent gases on the surface within the plurality of vacuum packages while minimizing thermal stress on the plurality of vacuum packages. How to. The method of claim 1, wherein pairing the device wafer and the lead wafer comprises: Aligning the device wafer and the lead wafer to align the plurality of first sealing rings and the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; Positioning the aligned device wafer and lead wafer in a vacuum furnace; Creating and heating a vacuum in the vacuum furnace; Sealing the gap between the device wafer and the lead wafer to bring the plurality of first sealing rings and the plurality of second sealing rings into contact with one or more of the plurality of MEMS devices and one or more CMOS or other integrated circuit devices. Generating a plurality of vacuum packages comprising; And Cooling the finished device wafer and lead wafer assembly at a predetermined rate to minimize the release of subsequent gases on the surface within the plurality of vacuum packages while minimizing thermal stress on the plurality of vacuum packages. How to. The method of claim 1, wherein forming the sealing layer comprises forming an indium crimp seal over each of the second sealing rings. A method for packaging a MEMS device in vacuum, Forming a plurality of MEMS devices on the device wafer; Forming a plurality of first sealing rings surrounding both one of the plurality of MEMS devices and one or more mating pads selectively coupled to the MEMS devices; A plurality having one or more mating pads each corresponding to a location of one or more mating pads selectively coupled to the MEMS device to enable selective electrical connection of the integrated circuit device to the selected MEMS device; Forming an integrated circuit device on a lead wafer; One or more bonding each surrounding one of the plurality of CMOS or other integrated circuit devices and the one or more mating pads of an integrated circuit device, the boundaries of the integrated circuit device and the other integrated circuit devices; Forming a plurality of second sealing rings between the pads on the lead wafer; Forming a sealing layer on each of the plurality of first sealing rings or on each of the plurality of second sealing rings; And The device wafer in a vacuum environment to create a vacuum package including one or more plurality of MEMS devices and one or more CMOS or other integrated circuit devices within each of the plurality of first and second sealing rings; And pairing the lead wafers. 10. The method of claim 9, further comprising heating the solder layer prior to pairing the device wafer and lead wafer. 10. The method of claim 9, wherein depositing the solder layer comprises aligning any one of the plurality of first sealing rings or the plurality of second sealing rings to position a preformed solder pattern. How to. 10. The method of claim 9, wherein depositing the solder layer comprises electroplating a wafer to deposit the solder layer. 10. The method of claim 9, wherein depositing the solder layer comprises vacuum deposition of a solder layer. 10. The method of claim 9, wherein depositing the solder layer comprises electroless plating. 10. The method of claim 9, wherein the forming of the plurality of second sealing rings comprises forming a plurality of solder adhesion layers on the lead wafer corresponding to positions and numbers of the plurality of first sealing rings. How to. The method of claim 1, Anti-reflective coating of the inner surface of the lead wafer inside the second sealing ring; And And antireflectively coating the outer surface of the lead wafer. The method of claim 1, And forming one or more spacers over said plurality of second sealing rings. The method of claim 1, And forming one or more bonding pad channels in the device wafer to correspond with the position of the bonding pads on the lead wafer. A method for packaging a MEMS device in vacuum, Forming a plurality of MEMS devices on the device wafer; Forming a plurality of first sealing rings surrounding both one of the plurality of MEMS devices and one or more mating pads selectively coupled to the MEMS devices; One or more mating pads that respectively correspond to one or more mating pads selectively coupled to the MEMS device to enable selective electrical connection of the CMOS or other integrated circuit device to the selected MEMS device. Forming a plurality of CMOS or other integrated circuit devices having a lead wafer; Each surrounding one of the plurality of CMOS or other integrated circuit devices and the one or more mating pads of the CMOS or other integrated circuit device, the boundaries of the CMOS or other integrated circuit device and the CMOS or other integrated circuit. Forming a plurality of second sealing rings on the lead wafer positioned between one or more bonding pads coupled to the device; Forming a sealing layer on each of the plurality of first sealing rings or on each of the plurality of second sealing rings; The device wafer in a vacuum environment to create a vacuum package including one or more plurality of MEMS devices and one or more CMOS or other integrated circuit devices within each of the plurality of first and second sealing rings; Pairing the lead wafers Opening a plurality of probe channels to provide a connection to a bonding pad for testing of the plurality of vacuum packaged integrated circuit devices in the lead wafer following generation of a plurality of vacuum packages; Testing each of the plurality of vacuum packaged integrated circuit devices by probing the bonding pads coupled to the respective integrated circuit devices; And Dicing the plurality of vacuum packaged integrated circuits after the testing. 20. The method of claim 19, further comprising forming a plurality of cavities on the lead wafer, wherein each cavity is surrounded internally by one of the plurality of second sealing rings and the CMOS or other integrated circuit. And not damage the device and one or more mating pads contained within each of the plurality of second sealing rings. 21. The method of claim 20, wherein forming the plurality of cavities comprises etching a plurality of pits in the lead wafer, each pit being surrounded by one of the plurality of second sealing rings. And thereby leave a cavity surrounded by one of the plurality of second sealing rings. A vacuum package comprising a MEMS device and one or more integrated circuit devices, A MEMS device formed on the device wafer with one or more associated mating pads; A sealing ring formed surrounding the MEMS device and the one or more mating pad boundaries associated with the MEMS device; And One or more integrated circuit devices formed on a lead wafer having one or more lead mating pads corresponding in position and number to the mating pad, and having one or more bonding pads; , The sealing ring seals the lead wafer to the device wafer to provide a vacuum package including the MEMS device and the one or more integrated circuit devices, wherein the one or more mating pads correspond to the corresponding one or more. And a bonding pad passing through an outer circumferential surface of the sealing ring. 23. The package of claim 22 further comprising one or more spacers formed over the sealing ring. A method for packaging an integrated circuit device in vacuum, Forming a plurality of integrated circuit devices on the device wafer; A plurality of first sealing rings each enclosing one or more integrated circuit devices and located between a boundary of the one or more integrated circuit devices and one or more bonding pads coupled to the one or more integrated circuit devices Forming a; Forming a plurality of second sealing rings corresponding to the plurality of first sealing rings in position and number on a lead wafer; Forming a sealing layer on one of each of the plurality of first sealing rings or each of the plurality of second sealing rings; Aligning the device wafer and the lead wafer to align each of the plurality of first sealing rings and each of the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; And Pairing the device wafer and the lead wafer in a vacuum environment to create a vacuum package including one or more plurality of integrated circuit devices inside each of the plurality of first and second sealing rings. Method comprising a. 25. The method of claim 24, further comprising forming a plurality of cavities on the lead wafer, wherein each of the cavities is enclosed therein by one of the plurality of second sealing rings. . 27. The method of claim 25, wherein forming the plurality of cavities comprises etching a plurality of pits in the lead wafer, each pit being surrounded by one of the plurality of second sealing rings. And thereby leave a cavity surrounded by one of the plurality of second sealing rings. The method of claim 25, wherein forming the plurality of cavities, Forming a plurality of holes in the window wafer corresponding to the plurality of integrated circuit devices; And Combining the window wafer and the lead wafer to create a plurality of cavities corresponding to the plurality of integrated circuit devices. 25. The method of claim 24, wherein pairing the device wafer and the lead wafer comprises: Positioning the aligned device wafer and lead wafer in a vacuum chamber; Creating a vacuum in the vacuum chamber; And Sealing the gap between the device wafer and the lead wafer to contact the plurality of first sealing rings and the plurality of second sealing rings to produce a plurality of vacuum packages including one or more plurality of integrated circuit devices. And comprising a step. 25. The method of claim 24, wherein pairing the device wafer and the lead wafer comprises: Positioning the aligned device wafer and lead wafer in a vacuum furnace; Creating a vacuum in the vacuum furnace; Releasing gas in the surface regions of the device wafer and lead wafer by heating the vacuum furnace to a temperature sufficient to release gas on the surfaces of the device wafer and lead wafer; Sealing the gap between the device wafer and the lead wafer to contact the plurality of first sealing rings and the plurality of second sealing rings to produce a plurality of vacuum packages including one or more plurality of integrated circuit devices. step; And Cooling the device wafer and lead wafer assembly after closure of the gap at a predetermined rate to minimize the release of subsequent gases on the surface within the plurality of vacuum packages while minimizing thermal stress on the plurality of vacuum packages. Characterized in that the method. 25. The method of claim 24, wherein forming the sealing layer comprises forming an indium crimp seal over each of the second sealing rings. 25. The method of claim 24, wherein forming the plurality of first sealing rings comprises forming a plurality of dielectric layer rings, the dielectric layer rings surrounding one or more integrated circuit devices, wherein the one or more integrated circuit devices are formed. And a boundary between an integrated circuit device and one or more bonding pads coupled to the one or more integrated circuit devices. The method of claim 24, Anti-reflective coating of the inner surface of the lead wafer inside the second sealing ring; And And antireflectively coating the outer surface of the lead wafer. The method of claim 24, And forming one or more spacers over said plurality of second sealing rings. The method of claim 24, Forming one or more bonding pad channels in the lead wafer to correspond with the position of the bonding pads on the device wafer. The method of claim 24, Opening a plurality of probe channels to provide a connection to a bonding pad for testing of the plurality of vacuum packaged integrated circuit devices in the lead wafer following generation of a plurality of vacuum packages; Testing each of the plurality of vacuum packaged integrated circuit devices by probing the bonding pads coupled to the respective integrated circuit devices; And Dicing the plurality of vacuum packaged integrated circuits after the testing. A method for packaging an integrated circuit device in vacuum, Forming a plurality of integrated circuit devices on the device wafer; A plurality of first sealing rings each enclosing one or more integrated circuit devices and located between a boundary of the one or more integrated circuit devices and one or more bonding pads coupled to the one or more integrated circuit devices Forming a; Forming a plurality of second sealing rings corresponding to the plurality of first sealing rings in position and number on a lead wafer; Depositing a sealing layer on either one of said plurality of first sealing rings or each of said plurality of second sealing rings; Aligning the device wafer and the lead wafer to align each of the plurality of first sealing rings and each of the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; And Pairing the device wafer and the lead wafer in a vacuum environment to create a vacuum package including one or more plurality of integrated circuit devices inside each of the plurality of first and second sealing rings. Method comprising a. 37. The method of claim 36, further comprising heating the solder layer prior to pairing the device wafer and lead wafer. 37. The method of claim 36, wherein depositing the solder layer comprises aligning any one of the plurality of first sealing rings or the plurality of second sealing rings to position a preformed solder pattern. How to. 37. The method of claim 36, wherein depositing the solder layer comprises electroplating the lead wafer to deposit a solder layer. 37. The method of claim 36, wherein depositing the solder layer comprises vacuum deposition of a solder layer. 37. The method of claim 36, wherein depositing the solder layer comprises electroless plating. A method for packaging an integrated circuit device in vacuum, Forming a plurality of integrated circuit devices on the device wafer; A plurality of first sealing rings each enclosing one or more integrated circuit devices and located between a boundary of the one or more integrated circuit devices and one or more bonding pads coupled to the one or more integrated circuit devices Forming a; Forming a plurality of second sealing rings corresponding to the plurality of first sealing rings in position and number on a lead wafer; Forming a sealing layer on one of each of the plurality of first sealing rings or each of the plurality of second sealing rings; Aligning the device wafer and the lead wafer to align each of the plurality of first sealing rings and each of the plurality of second sealing rings in a line with a gap between the device wafer and the lead wafer; And Pairing the device wafer and the lead wafer in a vacuum environment to create a plurality of vacuum packages comprising one or more plurality of integrated circuit devices. 43. The method of claim 42, wherein forming the plurality of first sealing rings comprises forming a solder adhesion layer on each of the plurality of first sealing rings. The method of claim 43, wherein the forming of the solder adhesion layer comprises: Depositing a titanium layer; Depositing a palladium layer on the titanium layer; And Depositing a gold layer over the palladium layer. 43. The method of claim 42, wherein the forming of the plurality of second sealing rings comprises forming a plurality of solder adhesion layers on the lead wafer corresponding to positions and numbers of the plurality of first sealing rings. How to. The method of claim 45, wherein the forming of the solder adhesion layer comprises: Depositing a titanium layer; Depositing a palladium layer on the titanium layer; And Depositing a gold layer over the palladium layer. A vacuum package comprising one or more integrated circuit devices, One or more integrated circuit devices formed on the device wafer with one or more associated bonding pads; A sealing ring formed on the device wafer between a boundary of the one or more integrated circuit devices and one or more bonding pads coupled to the one or more integrated circuit devices; And And a vacuum package lid providing a vacuum cell for the one or more integrated circuit devices and sealed to the sealing ring. 48. The package of claim 47 further comprising one or more spacers formed over the sealing ring. 48. The package of claim 47, wherein the vacuum package lead includes a cavity formed therein to increase the volume of the vacuum cell and thereby reduce the pressure level inside the vacuum cell. In a vacuum package for an integrated circuit device, A sealing ring having one or more spacers, located in a predetermined region on the substrate material, and surrounding one or more integrated circuit devices; And And a sealing layer over said sealing. 51. The package of Claim 50, further comprising a dielectric layer formed on said region designated by said sealing ring. 51. The package of Claim 50, wherein the one or more spacers are comprised of silicon nitride. 51. The apparatus of claim 50, wherein the one or more spacers are formed from the substrate material. 51. The apparatus of claim 50, wherein the sealing layer comprises indium compression seals. 51. The apparatus of claim 50, wherein the sealing layer comprises a solder layer.