KR20030023372A - Power supply circuit of electronic ballast - Google Patents

Abstract

PURPOSE: A power supply circuit for an electronic ballast is provided to obtain a high power factor and reduce stress for voltages of insulated gate bipolar transistors, while reducing manufacturing costs. CONSTITUTION: A power supply circuit comprises an AC power input unit(300); a rectifying unit(400) for rectifying the alternating current input from the AC power input unit into direction current; a charging unit(800) for charging a first AC voltage rectified by the rectifying unit with DC voltage; an inverter unit(600) for generating a signal having a predetermined switching frequency; and a power factor improvement unit(500) for receiving the signal from the inverter unit and generating a second AC voltage which is obtained by frequency-converting the DC voltage of the charging unit in accordance with the predetermined frequency of the signal. The power factor improvement unit clamps the first AC voltage and charges the charging unit with DC link voltage.

Description

Power supply circuit of electronic ballasts

The present invention relates to a power supply circuit of an electronic ballast for fluorescent lamps, and more particularly, to a power supply circuit of a previous ballast in which the power factor is close to 1 and the power factor correction circuit and the inverter circuit are combined.

Since fluorescent lamps have negative impedance characteristics, they cannot be used by directly connecting to commercial transmission lines. Therefore, a device for controlling the current, that is, a ballast, is required to protect the fluorescent lamp due to overcurrent. The ballast provides the starting and holding voltages for the fluorescent lamp and controls the current flowing into the fluorescent lamp. In addition, high power factor with low total harmonic distortion should be maintained in accordance with international standards.

In addition, the operating frequency of the fluorescent lamp should be increased in order to reduce flicker, stroboscopic effect and noise of the fluorescent lamp while having a compact size. When fluorescent ballasts operate at high frequencies, energy efficiency can be increased by increasing the efficiency of luminance by about 10%. Therefore, in recent years, electronic ballasts having a high frequency have been actively studied.

The high frequency electronic ballast converts the frequency of the home into high frequency output. In general, an electronic ballast consists of a full-bridge diode rectifier and a DC / AC inverter operating at high frequency to drive a fluorescent lamp. The electric ballast has a low power factor because the current flowed directly from the commercial transmission line by the ballast has large harmonics. Therefore, in order to solve this problem, a power factor correction (PFC) circuit is used for the ballast.

Conventionally, using an active power factor improvement circuit employing a discontinuous current mode boost converter, the current having the same phase as the voltage waveform of the input sine wave flows in a fluorescent lamp, and thus the effect of power factor improvement can be seen. there was. However, such a power factor improvement circuit of the related art has a two-step process of changing the power, thereby increasing the manufacturing cost and lowering the reliability of the ballast. To solve this problem, an electronic ballast, in which a full-bridge diode and a boost converter / inverter are combined to perform a one-step power conversion process, is described in IEEE-APEC, 1996 (pp.616-627). with high power factor "and" High-power factor electronic ballast with constant dc-link voltage "of IEEE Trans, 1998, PE-13, (6) (pp. 1030-1037). In this electronic ballast, four power semiconductor elements are connected in series between the output of the ballast from a commercial transmission line. However, in this case, it is more desirable to reduce the number of power semiconductor devices in consideration of efficiency, reliability, and reduction in manufacturing cost. On the other hand, conventional discrete boost converters having a circuit having a power conversion process of one or two stages can obtain high power factor by simple control, but since their output voltage is higher than the peak voltage of a commercial transmission line, power semiconductors The devices increase the stress on the voltage.

Accordingly, an object of the present invention is to provide a power supply circuit of an electronic ballast that can reduce the stress on the voltage of the power semiconductor devices.

In addition, another object of the present invention is to provide a power supply circuit of an electronic ballast having a high energy conversion efficiency and high reliability compared to the conventional high power factor electronic ballast and at the same time reduce the manufacturing cost.

1 is a circuit diagram showing a power supply circuit of an electronic ballast for a fluorescent lamp according to an embodiment of the present invention;

2 is a block diagram of a power factor improvement circuit according to an embodiment of the present invention;

3 is a block diagram showing operation of a power factor improvement circuit diagram according to an embodiment of the present invention;

4 is a view showing a waveform of a power factor improvement circuit according to an embodiment of the present invention;

5 is a block diagram of a circuit of a known self-oscillating type D inverter provided in a power supply circuit of an electronic ballast according to an embodiment of the present invention;

6 and 7 are graphs showing the experimental results of the electronic ballast according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 2, 3, 4, 5, 6, 71, 73: Diodes 11, 12: Switching element (switch)

21, 22: parasitic diodes of switching elements 31, 32: parasitic capacitors

51, 42, 64: inductors 41, 52, 68: capacitors

43: DC link capacitor 61, 62, 63: transformer

65: fluorescent lamp 72, 74: zener diode

100: power factor improvement circuit (PFC circuit) 200: inverter circuit

300: AC power supply input 400: rectifier

500: power factor improvement circuit 600: inverter

700: fluorescent lamp 800: charging section

The power supply circuit of the electronic ballast for supplying power to the fluorescent lamp according to an embodiment of the present invention includes an AC power input unit to which the input AC power is applied; A rectifier for rectifying the AC input from the AC power input unit into DC; A charging unit configured to charge the first AC voltage rectified by the rectifier to a predetermined DC voltage; An inverter unit generating a signal having a predetermined switching frequency; And a power factor improvement circuit unit configured to receive the signal having the predetermined switching frequency from the inverter unit and generate a second AC voltage obtained by frequency converting the DC voltage of the charging unit to the predetermined switching frequency. The circuit unit clamps the first AC voltage to charge the charging unit to a predetermined DC link voltage.

In the above embodiment, the rectifying unit, four diodes are arranged in the form of a bridge, the input terminal of the bridge is connected to the output terminal of the AC power input unit, the output terminal of the bridge is connected to both ends of the charging unit, In the power factor improving circuit, first and second switching elements having parasitic diodes connected in parallel are arranged in the form of two diodes and a bridge, and a node between the first and second switching elements and the two diodes. It is preferable that an inductor is connected between nodes between the capacitors, and a capacitor is connected between one of the rectifier input terminals and a node between the two diodes in the power factor improving circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a power supply circuit of an electronic ballast for a fluorescent lamp according to an embodiment of the present invention. As shown in Figure 1, the power supply circuit of the electronic ballast according to an embodiment of the present invention is the AC power input unit 300 for inputting the AC power to the rectifier 400 of the power supply circuit from a commercial transmission line, power factor Inverter unit 600 for supplying a switching frequency signal to the power factor improvement circuit unit 500, the power factor improvement circuit unit 500 to improve, the fluorescent lamp unit 700 and the charging unit 800 for charging the rectified current from the rectification Is made of.

On the other hand, as shown in Figure 1, the power supply circuit of the electronic ballast according to an embodiment of the present invention is combined with a power factor improvement circuit (see 100 of FIG. 2) and an inverter circuit (see 200 of FIG. 5) for driving a fluorescent lamp In one step, power factor improvement and inverter work.

First, the power factor improvement step according to the embodiment of the present invention will be described.

2 is a block diagram of a power factor improvement circuit (also called a PFC circuit) according to an embodiment of the present invention. 3A to 3J are circuit diagrams for explaining each mode of the PFC circuit 100 during the switching period T _S , and FIG. 4 is a waveform showing the operation thereof. 2, the voltage V _Cr is the voltage across the resonant capacitor 41 having a capacitance C _r, the current i _Lr is the current flowing through the resonant inductor 42 having an inductance L _r. 3, the current I _Lr is a peak value of i _Lr during the switching period. When the PFC circuit operates normally, as shown in Fig. 3, the PFC circuit has ten modes during the period T _S that switches once. Since the capacitance of the DC link capacitor 43 has a large value, the ripple component of the DC link voltage V _d is ignored. The ballast is designed so that the DC link voltage V _d is greater than the amplitude V _m of the input voltage V _i . It is assumed that the supply voltage V _i is constant during the switching period.

Prior to the first mode, current i _Lr continues to flow through diode 5, first switch 11 (hereinafter also referred to as first switching element) and resonant inductor 42 with a negative peak value I _Lr . The capacitor voltage V _Cr is reset.

The operation of the first mode for the PFC circuit 100 will be described with reference to FIGS. 3A and 4. The first switch 11 is turned off at time t ₀ when the first mode is started. Then, the time t _1, the resonance inductor 42 begins to discharge the parasitic capacitor 32, which is inherent in the charge and the second switching device of the parasitic capacitor 31, which is inherent to the first switching element. The voltage V _S2 across the second switch 12 (hereinafter also referred to as a second switching element) decreases and the voltage V _S1 across the first switch 11 increases. The voltage across the resonant inductor 42 decreases and the current i _Lr flowing through the resonant inductor 42 decreases slightly. Therefore, the transition time t _t and the current i _Lr flowing through the resonant inductor 42 are

,

Given by

Here, since the capacitances of the parasitic capacitors 32 and 32 connected in parallel with the first and second switches 11 and 12 have the same value as small as C _S1 = C _S2 = C _S , the switches 11 and The transition times t _t of 12) are very small. Therefore, the current of the resonant inductor 42 is almost constant.

Next, the operation of the second mode for the PFC circuit 100 will be described with reference to FIGS. 3B and 4. At time t ₁ , the voltage V _S2 across the second switch 12 becomes 0 [V] and the parasitic diode 22 inherent in the second switching element 12 is turned on. Since the current i _Lr that continues to flow through the resonant inductor 42 flows into the DC link capacitor 43, the magnetic energy stored in the resonant inductor 42 is transferred to the DC link capacitor 43 to the DC link capacitor 43. Accumulate as electrical energy. Since the voltage across the resonant inductor 42 is fixed at the DC link voltage V _d , the current flowing through the resonant inductor 42 is maintained until time t ₂ .

Increase linearly as

Next, the operation of the third mode for the PFC circuit 100 will be described with reference to FIGS. 3C and 4. At time t ₂ , the second switch 12 is turned on. Since the current has already flowed through the parasitic diode 22 before the second switch 12 is turned on, the voltage of the second switch 12 has 0 [V] when the second switch 12 is turned on. . The current i _Lr flowing through the resonant inductor 42 increases linearly as in the second mode, and becomes zero at the time t ₃ when the third mode ends. Therefore, the time t _l at which the current i _Lr flowing in the resonant inductor 42 increases linearly

Is given by

Next, operation of the fourth mode for the PFC circuit 100 will be described with reference to FIGS. 3D and 4. When the direction of the current i _Lr flowing in the resonant inductor 42 is switched at time t ₃ , the diode 5 is turned off and the diode 2 is turned on. Thereafter, the AC power input unit 300 on the left side of the PFC circuit 100 starts supplying current to the PFC circuit 100 to charge the resonant capacitor 41. By the resonance of the resonant capacitor 41 and the resonant inductor 42, the voltage of the resonant capacitor 41 increases. Thus, the input voltage at the input terminal V _i are each a resonant capacitor 41 and resonant inductor 42

,

By supplying a voltage and a current satisfying the voltage is supplied to the resonant capacitor 41 and the resonant inductor 42. Here, the resonance frequency ω _o and impedance Z _o of the resonance circuit composed of the resonance capacitor 41 and the resonance inductor 42 are

,

Is given by

At the time t ₄ at the end of the fourth mode, the voltage of the resonant capacitor 41 reaches v _i , and then the current i _Lr of the resonant inductor 42 reaches an amplitude i _Lr which is a peak value. Therefore, the resonant time t _r of the fourth mode and the peak current i _Lr of the resonant inductor 42 are respectively.

,

Is given by

Next, the operation of the fifth mode for the PFC circuit 100 will be described with reference to FIGS. 3E and 4. At time t ₄ , capacitor voltage V _Cr of resonant capacitor 41 reaches input voltage v _i . Thereafter, the diode 6 is turned on and the resonant inductor 42 continues to flow current through the resonant inductor 42, the second switch 12 and the diode 6 until time t ₅ .

Next, operation of the sixth mode for the PFC circuit 100 will be described with reference to FIGS. 3F and 4. The second switch 12 is turned off at time t ₅ . Thereafter, the current i _Lr flowing in the resonant inductor 42 starts to charge the parasitic capacitor 32 and discharge the parasitic capacitor 31. By the time t ₆ , the switch voltage V _S2 of the parasitic capacitor 32 increases and the switch voltage V _S1 of the parasitic capacitor 31 decreases. The transition time t _t of the switches 11 and 12 is the same as in the first mode.

Next, the operation of the seventh mode for the PFC circuit 100 will be described with reference to FIGS. 3G and 4. At time t ₆ , the switch voltage V _S1 across the first switch 11 becomes 0 [V] and the parasitic diode 21 inherent in the first switching element 11 is turned on. Since the current i _Lr that continues to flow through the resonant inductor 42 flows into the DC link capacitor 43, the magnetic energy stored in the resonant inductor 42 is transferred to the DC link capacitor 43, and the DC link capacitor 43 is supplied to the DC link capacitor 43. Electrical energy is accumulated. Since the voltage across the resonant inductor 42 is fixed at -V _d , the current i _Lr flowing through the resonant inductor 42 is until time t ₇ .

Increase linearly as

Next, operation of the eighth mode for the PFC circuit 100 will be described with reference to FIGS. 3H and 4. At time t ₇ the first switch 11 is turned on. As in the third mode, when the first switch 11 is turned on, the voltage of the first switch 11 has 0 [V]. The current i _Lr flowing through the resonant inductor 42 decreases linearly to become zero at time t ₈ at the end of the eighth mode. The time t _t at which the current i _Lr flowing through the resonant inductor 42 decreases linearly is equal to the linear increase time in the second and third modes.

Next, operation of the ninth mode for the PFC circuit 100 will be described with reference to FIGS. 3I and 4. When the direction of the current i _Lr flowing through the resonant inductor 42 is switched at time t ₈ , the diode 6 is turned off. Thereafter, the resonant capacitor 41 starts to increase the current i _Lr flowing in the resonant inductor 42 in the direction opposite to that previously flown, and the diode 3 is turned on. Energy stored in the resonant capacitor 41 is transferred to the resonant inductor 42. Then, the time t ₉ to the resonant capacitor 41 in the resonant circuit the voltage across the capacitor V _Cr and an inductor current of the resonant inductor (42), i _Lr is

,

Is given by The resonance time and the current flowing continuously are the same as in the fourth embodiment.

Next, the operation of the tenth mode for the PFC circuit 100 will be described with reference to FIGS. 3J and 4. At time t ₉ , the capacitor voltage V _Cr of the resonant capacitor 41 reaches 0 [V]. Thereafter, the diode 5 is turned on and the resonant inductor 42 continues to flow current through the resonant inductor 42, the diode 5 and the first switch 11 until time t ₁₀ .

The input voltage v _i of the input stage is substantially constant during the switching period T _S. Next, from the fourth mode, the effective value i _iavg of the input current i _i is

Is given by

The commercial current i _S is given by the effective value of the input current i _i by the filter capacitor 52 and the filter inductor 51. Since the input filter inductor 51, the voltage drop across the be ignored in the commercial frequency, the input voltage of the electronic ballast v _i is below nominal voltage v _S, i.e.

Same as Where V _m and ω are amplitude and angular frequency, respectively.

Next, the commercial current i _s is

Is given by

The effective input power P _i is

Is given by

Power factor PF

= 1

Is given by

The capacitance C _r of the resonant capacitor 41 is

And it is preferably designed to have the effective input power P _i of the desired steps.

Since the transition times t _t of the switches 11 and 12 can be neglected, as shown in FIG. 4, the time t _f that the current continues to flow in the resonant inductor 42 in the fifth and tenth modes decreases to zero. Can be. In addition, the time t ₁ at which the current flowing through the resonant inductor 42 linearly increases or decreases has a maximum value at the peak voltage of the input voltage. One switching period T _S

Is given by

Therefore, the following relation for power factor 1 is satisfied.

Therefore, in order to satisfy the power factor 1, the resonance inductor L _r of the resonance inductor 42 in the PFC circuit 100 is

It is desirable to be designed to satisfy.

Next, the power supply circuit of the electronic ballast according to the embodiment of the present invention includes a known self-oscillating class D inverter (200) as an inverter circuit for supplying a signal of the switching frequency to the power factor improvement circuit. You may also do it.

5 is a block diagram of a self-oscillating type D inverter circuit 200 using a saturable transformer. The switching frequency of the power factor improving circuit is controlled by the secondary winding N _s of the transformer 63 in the self-oscillating type D inverter circuit 200.

The present inventors experimented the Example of this invention shown in FIG. 1 with the fluorescent lamp of 40W on the following conditions.

v _s = 208 Vrms C _d = 22㎌

L _f = 3mH C _f = 0.22㎌

L _r = 1mH C _r = 90㎋

L _s = 3mH C _s = 0.22㎌

C _p = 2.2㎋

The frequency of the experiment is 21 kHz. 6A shows the voltage V _S and the current i _s of the commercial transmission line. The power supply circuit of the electronic ballast according to the embodiment of the present invention has a power factor of 0.997 nearly 1 and the total harmonic distortion of the commercial current is 8. 6B shows the input voltage V _i , the input current i _i and the output DC link voltage V _d . As shown in FIG. 6B, the power supply circuit of the electronic ballast according to the present invention has the same phase with the input voltage v _i and the input current i _i , thereby achieving a power factor close to one. FIG. 7A shows the inductor current i _Lr and the capacitor voltage V _Cr of the resonant circuit, and FIG. 7B shows the resonance inductor current i _Ls and the high frequency output voltage V _o .

As described above, the power supply circuit of the electronic ballast according to the present invention has a power factor close to 1, and the power factor improving circuit and the inverter circuit share the first and second switching elements so that they can operate in one step. . Furthermore, the power supply circuit of the previous ballast according to the present invention clamps the voltage input from the AC power input unit by the resonant capacitor, so that the DC link voltage of the DC link capacitor serving as the charging unit can be relatively low. Therefore, the stress of the voltage can be reduced for the power semiconductor device. In addition, it is possible to provide an electronic ballast that can have a high energy conversion efficiency and high reliability as compared with the conventional HPF electronic ballast and at the same time reduce the manufacturing cost.

Claims (2)

In the power supply circuit of the electronic ballast for supplying power to the fluorescent lamp, An AC power input unit to which an input AC power is applied; A rectifier for rectifying the AC input from the AC power input unit into DC; A charging unit configured to charge the first AC voltage rectified by the rectifier to a predetermined DC voltage; An inverter unit generating a signal having a predetermined switching frequency; And A power factor improvement circuit unit configured to receive a signal having the predetermined switching frequency from the inverter unit and generate a second AC voltage obtained by frequency converting the DC voltage of the charging unit according to the predetermined switching frequency, And the power factor improving circuit part clamps the first AC voltage to charge the charging part to a predetermined DC link voltage. The method of claim 1, wherein the rectifying unit, Four diodes are arranged in the form of a bridge, the input terminal of the bridge is connected to the output terminal of the AC power input unit, the output terminal of the bridge is connected to both ends of the charging unit, The power factor improvement circuit unit, First and second switching elements each having a parasitic diode connected in parallel are arranged in the form of a bridge with two diodes, and an inductor between a node between the first and second switching elements and a node between the two diodes. And a capacitor is connected between one of the rectifier input terminals and a node between the two diodes in the power factor correction circuit.