KR20030021733A - Address buffer and semiconductor memory device using this buffer - Google Patents

Abstract

PURPOSE: An address buffer and semiconductor memory device using the same are provided to reduce current consumption by preventing a mode set signal from being varied according to variation of an externally applied address. CONSTITUTION: An address buffer comprises the first buffer(30) and the second buffer(32'). The first buffer(30) buffers an externally applied signal(A) at a read operation and generates a buffered address(AB). The second buffer(32') maintains a mode set signal at a reset state at the read operation, and buffers the externally applied signal to output the buffered signal as the mode set signal at a mode set operation.

Description

Address buffer and semiconductor memory device using this buffer}

The present invention relates to a semiconductor memory device, and more particularly, to an address buffer and a semiconductor memory device using the same.

An address buffer of a conventional semiconductor memory device includes an address buffer for buffering an address applied from an address pin in a normal operation, and a mode setting signal buffer for buffering a mode setting signal applied from an address pin in a mode setting operation. Consists of.

By the way, the address buffer of the conventional semiconductor memory device has a problem that the current consumption is increased by the mode setting signal transitions in accordance with the transition of the address input during normal operation. That is, there is a problem that the current consumption increases because the mode setting signal, which should not be changed in the normal operation, changes according to the transition of the address.

FIG. 1 is a block diagram showing the structure of a conventional semiconductor memory device, wherein the address pins 10-1 to 10-n, the instruction pins 12-1 to 12-3, and the address buffers 14-1 to 14- are shown in FIG. n), CSB buffer 16-1, RASB buffer 16-2, CASB buffer 16-3, address decoder 18, mode setting register 20, instruction decoder 22, and PCLKR generation circuit It consists of 24.

The function of each of the blocks shown in FIG. 1 will be described below.

The address pins 10-1 to 10-n input addresses A1 to An applied from the outside. The command pins 12-1 to 12-3 input commands (CSB, RASB, CASB) that are applied from the outside. Each of the address buffers 14-1 to 14-n latches the addresses A1 to An in response to the signal PCLKR, generates the mode setting signals MAB1 to MABn, and in response to the active signal ACT. The addresses A1 to An are buffered to generate buffered addresses AB1 to ABn. The address decoder 18 decodes the buffered addresses AB1 to ABn to generate the decoded addresses DAB1 to DABm. The mode setting register 20 outputs the buffered mode setting signals MAB1 to MABn as the mode setting signals MDAB1 to MDABk in response to the mode setting command MRS. The CSB buffer 16-1 buffers the inverted chip select signal CSB to generate a buffered inverted chip select signal CSBB. The RASB buffer 16-2 buffers the inverted row address strobe signal RASB to generate a buffered inverted row address strobe signal RASBB. The CASB buffer 16-3 buffers the inverted column address strobe signal CASB to generate the buffered inverted column address strobe signal CASBB. The command decoder 22 decodes the buffered signals CSBB, RASBB, and CASBB to generate a mode setting command MRS, an active command ACT, a precharge command PRE, and a refresh command REF. . The PCLKR generation circuit 24 generates the signal PCLKR in response to the buffered inverted row address strobe signal RASBB.

FIG. 2 is a circuit diagram showing the configuration of the address buffer shown in FIG. 1, which is composed of inverters I1, I2, I5, I6, I7, CMOS transfer gates C1, C2, and inverters I3, I4. Mode setting signal composed of an address buffer 30 composed of a latch L1, and an inverter I8, a CMOS transfer gate C3, a PMOS transistor P, and a latch L2 composed of inverters I9, I10. The buffer 32 is comprised.

In Fig. 2, A denotes an address applied from the outside, AB denotes a buffered address, MAB denotes a mode setting signal, and ACT denotes an active command. The signal PCLKR represents a clock signal generated in response to the inverted low address strobe signal RASB of the "low" level, and the voltage VCCH transitions to the "high" level at power-up and then "low". Indicates the voltage that transitions to the level.

The operation of the circuit shown in Fig. 2 is as follows.

Inverter I1 inverts the address A1. The CMOS transfer gate C1 is turned on in response to the "low" level signal PCLKR to transmit the output signal of the inverter I1. The latch L1 latches and inverts the output signal of the CMOS transfer gate C1. The CMOS transfer gate C2 is turned on in response to the "low" level active signal ACT to transmit the output signal of the latch L1. Inverters I6 and I7 buffer the output signal of CMOS transfer gate C2 to generate a buffered address AB.

The inverter I8 inverts the output signal of the latch L1. The CMOS transfer gate C3 is turned on in response to the " high " level signal PCLKR to transmit the output signal of the inverter I8. The PMOS transistor P is turned on in response to the signal VCCH of " low " level after powering up to make the node n a power supply voltage. The latch L2 is reset by the PMOS transistor P to generate the mode setting signal MAB of the "low" level. However, the latch L2 generates the mode setting signal MAB of the "low" level when the CMOS transfer gate C3 is turned on and the signal of the "high" level is transmitted. When the signal of the "low" level is transmitted, Generates a mode setting signal MAB of high " level.

That is, the conventional address buffer is generated in response to the inverted row address strobe signal RASB during normal operation (ie, active command ACT, precharge command PRE, or refresh command REF). When the CMOS transfer gate C1 is turned on in response to the low level signal PCLKR, an external address A is transmitted through the inverter I1, the CMOS transfer gate C1, and the latch L1. . When the signal PCLKR transitions from the "low" level to the "high" level, the CMOS transfer gate C3 is turned on to convert the signal latched in the latch L1 to the inverter I8, the CMOS transfer gate C3, and Transfer is via latch L2.

Therefore, the address buffer of the conventional semiconductor memory device is changed from the "low" level to the "high" level in the normal operation, and the mode setting signal MAB is also changed from the "low" level to the "high" level. There was a problem that the unwanted current consumption is caused by the change.

FIG. 3 is an operation timing diagram for explaining the operation of the address buffer shown in FIG. 2, and is an operation timing diagram for explaining the operation when the address A transitions from the "low" level to the "high" level.

When the clock signal CLK rises, an inverted low address strobe signal is applied from an external low row strobe signal RABB having a low level and an address A transitioning from a low level to a high level. The signal PCLKR is generated in response to the RB signal RASB. The CMOS transfer gate C1 outputs an address A applied from the outside to the latch L1 in response to the signal " low " level PCLKR. The CMOS transfer gate C3 outputs the signal latched to the latch L1 to the latch L2 in response to the signal "PCLKR" at the "high" level. Thus, the mode setting signal MRA transitions from the " low " level to the " high " level in accordance with the change of the address A, resulting in current consumption. When the "high" level active signal ACT is generated, the CMOS transfer gate C2 is turned on to generate a buffered address AB that transitions from the "low" level to the "high" level.

That is, in the conventional address buffer, when the signal PCLKR is generated in response to the inverted row address strobe signal RASB in the normal operation, the mode setting signal MRA is changed according to the change of the address, causing current consumption. There was a problem. This current consumption increases as the number of address buffers used for mode setting increases.

An object of the present invention is to provide an address buffer that can reduce current consumption by preventing the mode setting signal from being changed in accordance with the change of an address applied from the outside during normal operation.

Another object of the present invention is to provide a semiconductor memory device using an address buffer for achieving the above object.

The address buffer of the present invention for achieving the above object is a first buffer means for buffering a signal applied from the outside during normal operation to generate a buffered address, and maintains the mode setting signal in the reset state in the normal operation And a second buffer means for buffering the signal applied from the outside during the mode setting operation and outputting the signal as the mode setting signal.

A semiconductor memory device of the present invention for achieving the above another object is a semiconductor memory device having a plurality of pins, and a plurality of buffers for buffering a signal input from the plurality of pins, each of the buffers is a normal operation A first buffer means for buffering the signal at a time to generate a buffered signal, and maintaining a mode setting signal in a reset state in the normal operation, and buffering the signal at the mode setting operation as the mode setting signal. And a second buffer means for outputting.

An embodiment of a semiconductor memory device of the present invention for achieving the above another object is a semiconductor memory device having a plurality of pins, and a plurality of buffers for buffering a signal input from the plurality of pins, each of the buffers First buffer means for latching the signal in response to a first control signal in normal operation, buffering the latched signal in response to a second control signal, and generating a buffered signal; And a second buffer means for generating the latched signal as a mode setting signal in response to a first control signal and a mode setting command, and for maintaining the mode setting signal in a reset state in the normal operation. .

1 is a block diagram showing the structure of a conventional semiconductor memory device.

FIG. 2 is a circuit diagram showing the configuration of the address buffer shown in FIG.

FIG. 3 is an operation timing diagram for explaining the operation of the address buffer shown in FIG.

4 is a block diagram showing a configuration of a semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram of an embodiment of the address buffer shown in FIG.

6A and 6B are operation timing diagrams for explaining the operation of the address buffer shown in FIG.

Hereinafter, an address buffer and a semiconductor memory device using the same will be described with reference to the accompanying drawings.

Fig. 4 is a block diagram showing the structure of the semiconductor memory device of the present invention, and instead of the address buffers 14-1 to 14-n shown in Fig. 1, the address buffers 40-1 to 40-n are shown. It is configured in place of.

In FIG. 4, the configuration of the remaining blocks except for the address buffers 40-1 to 40-n is indicated by the same number because they are the same as the blocks shown in FIG.

The functions of the address buffers 40-1 to 40-n shown in FIG. 4 will be described below.

The address buffers 40-1 to 40-n latch the addresses A1 to An in response to the signal PCLKR, and the latched addresses in response to the signals PCLK and MRS receive the mode setting signals MAB1. MABn), and the latched addresses A1 to An are buffered in response to the active command ACT to the buffered addresses AB1 to ABn.

That is, the address buffers 40-1 to 40-n of the semiconductor memory device of the present invention shown in FIG. 4 generate the buffered addresses AB1 to ABn only during normal operation and the mode setting signals MAB1 to MABn. To keep the "low" level. The mode setting signals MAB1 to MABn are generated only when the mode setting command MRS is generated.

Therefore, the address buffer of the semiconductor memory device of the present invention does not cause current consumption by not changing the mode setting command MRS even if the address changes during normal operation.

FIG. 5 is a circuit diagram of the embodiment of the address buffer shown in FIG. 4, in which a NAND gate NA and an inverter I11 are added to the circuit diagram shown in FIG.

That is, the configuration of the address buffer 30 shown in FIG. 5 is the same as that of the address buffer 30 shown in FIG. 2, and the configuration of the mode setting signal buffer 32 'is the mode setting signal buffer 32 shown in FIG. ) Is different from the configuration.

In Fig. 5, elements having the same circuit configuration as those shown in Fig. 2 are denoted by the same reference numerals and numbers.

In Fig. 5, the NAND gate NA nonlogically multiplies the signal PCLKR with the mode setting command MRS. The inverter I11 inverts the output signal of the NAND gate NA.

The operation of the circuit shown in Fig. 5 is as follows.

The operation of the address buffer 30 will be easily understood by referring to the operation of the address buffer shown in FIG. 2, and only the operation of the mode setting signal buffer 32 'will be described here.

In normal operation, the NAND gate NA generates a "high" level signal when a "high" level signal PCLKR and a "low" level mode setting command MRS are generated. The CMOS transfer gate C3 is turned off in response to a signal of the "high" level. Then, no signal is transmitted from the latch L1 to the latch L2 through the CMOS transfer gate C3. In this case, regardless of the change in the address signal A, the mode setting signal MAB maintains the " low " level so that current consumption does not occur.

In the mode setting operation, the NAND gate NA generates a signal of "low" level when the "high" level signal PCLKR and the "high" level mode setting command MRS are generated. The CMOS transfer gate C3 is turned on in response to a signal of "low" level. Then, a signal is transmitted from the CMOS transfer gate C3 to the latch L2, and the latch L2 latches the signal transmitted through the CMOS transfer gate C3. In this case, a signal is transmitted through the CMOS transfer gate C3, so that the mode setting signal MAB changes according to the change of the address A. FIG.

6A and 6B are operation timing diagrams for explaining the operation of the address buffer shown in Fig. 5, Fig. 6A is an operation timing diagram during normal operation, and Fig. 6B is an operation timing diagram during mode setting operation. This is an operation timing diagram for explaining the operation when the address A transitions from the "low" level to the "high" level.

The operation of the address buffer in the normal operation will be described with reference to FIG. 6A as follows.

In the rising transition of the clock signal CLK, the "low" level inverted low address strobe signal RASB and the low address A are applied from the outside to generate a "high" level signal PCLKR. The CMOS transfer gate C1 latches the address A in the latch L1 in response to the "low" level signal PCLKR. The CMOS transfer gate C3 is turned off in response to the "low" level signal PCLKR to transmit no signal. Therefore, the mode setting signal MAB is maintained at the "low" level. When the signal PCLKR is shifted to the "high" level and the mode setting command MRS is the "low" level, the CMOS transfer gate C3 is turned off to not transmit the signal. Thus, even if the signal PCLKR transitions to the "high" level, the mode setting signal MAB remains at the "low" level. When the "high" level active command ACT is generated, the CMOS transfer gate C2 is turned on to transmit the latched signal to the latch L1. That is, a buffered address AB of "high" level is generated.

That is, as shown in Fig. 6A, during normal operation, the CMOS transfer gate constituting the mode setting signal buffer is turned off to keep the mode setting signal MAB "low", thereby preventing unwanted current consumption.

The operation of the address buffer in the mode setting operation will be described with reference to FIG. 6B as follows.

In the rising transition of the clock signal CLK, the "low" level inverted low address strobe signal RASB and the low address A are applied from the outside to generate a "high" level signal PCLKR. The CMOS transfer gate C1 latches the address A in the latch L1 in response to the "low" level signal PCLKR. When the mode setting command MRS is at the "high" level, the CMOS transfer gate C3 is turned on in response to the "high" level signal PCLKR and the mode setting command MRS to transmit the latched signal to the latch L1. do. Thus, the mode setting signal MAB transitions from the "low" level to the "high" level. In this case, since the active command ACT is not generated, the CMOS transfer gate C2 is turned off so that the latched signal is not transmitted to the latch L1, and the buffered address AB has a "high" level or a "low" level. Keep the previous level.

That is, in the address buffer of the semiconductor memory device of the present invention, the mode setting signal MAB changes in response to the transition of a signal applied from the outside during the mode setting operation.

Therefore, the address buffer of the semiconductor memory device of the present invention maintains the mode setting signal at the " low " level during the normal operation, and generates the mode setting signal that changes according to a signal applied from the outside during the mode setting operation. Undesirable current consumption can be prevented at the time.

The semiconductor memory device of the above-described embodiment has been described in which the mode setting signal is input through the address pins during the mode setting operation. However, when the mode setting signal is not applied through the address pins, the corresponding pins to which the mode setting signal is applied are applied. The buffers may be configured identically to the address buffer of the present invention.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Therefore, the address buffer and the semiconductor memory device using the same of the present invention can prevent the unwanted current consumption during normal operation by changing the mode setting signal according to a signal applied from the outside only during the mode setting operation.

Claims (14)

First buffer means for buffering a signal applied from the outside during normal operation to generate a buffered address; And And a second buffer means for maintaining a mode setting signal in a reset state in the normal operation, and buffering a signal applied from the outside in the mode setting operation and outputting the signal as the mode setting signal. . The method of claim 1, wherein the first buffer means A first transmission gate turned on in response to a first control signal to transmit the signal; A first latch for latching an output signal of the first transfer gate; A second transmission gate that is turned on in response to a second control signal to transmit an output signal of the first latch; And And a buffer for buffering the output signal of the second transfer gate to generate the buffered address. The method of claim 2, wherein the second buffer means An AND circuit for ANDing the first control signal and the mode setting command; A third transmission gate for transmitting the output signal of the first latch in response to the output signal of the AND circuit; And And a second latch for resetting the mode setting signal and latching the signal output from the third transmission gate to generate the mode setting signal. The method of claim 3, wherein the second latch And a reset transistor for resetting the mode setting signal. A plurality of pins; And A semiconductor memory device having a plurality of buffers for buffering a signal input from the plurality of pins. Each of the buffers First buffer means for buffering the signal to generate a buffered signal in normal operation; And And a second buffer means for maintaining a mode setting signal in a reset state in the normal operation and for buffering the signal and outputting the signal as the mode setting signal in the mode setting operation. The method of claim 5, wherein the first buffer means A first transmission gate turned on in response to a first control signal to transmit the signal; A first latch for latching an output signal of the first transfer gate; A second transmission gate which is turned on in response to the second control signal to transmit an output signal of the first latch; And And a buffer configured to buffer the output signal of the second transfer gate to generate the buffered signal. The method of claim 5, wherein the second buffer means An AND circuit for ANDing the first control signal and the mode setting command; A third transmission gate for transmitting the output signal of the first latch in response to the output signal of the AND circuit; And And a second latch for resetting the mode setting signal, latching a signal output from the third transfer gate to generate the mode setting signal. The method of claim 7, wherein the second latch And a reset transistor for resetting the mode setting signal. A plurality of pins; And A semiconductor memory device having a plurality of buffers for buffering a signal input from the plurality of pins. Each of the buffers First buffer means for latching the signal in response to a first control signal in normal operation, and buffering the latched signal in response to a second control signal to generate a buffered signal; And A second buffer means for generating the latched signal as a mode setting signal in response to the first control signal and a mode setting command in a mode setting operation, and maintaining the mode setting signal in a reset state in the normal operation; A semiconductor memory device, characterized in that provided. The semiconductor memory device of claim 9, wherein the semiconductor memory device comprises: And a first control signal generation circuit configured to generate the first control signal in response to an inverted row address strobe signal. The semiconductor memory device of claim 10, wherein the semiconductor memory device comprises: And a command decoder for decoding the inverting chip select signal, the inverting column address strobe signal, and the inverting row address strobe signal to generate the second control signal and the mode setting command. The method of claim 9, wherein the first buffer means A first transmission gate turned on in response to a first control signal to transmit the signal; A first latch for latching an output signal of the first transfer gate; A second transmission gate which is turned on in response to the second control signal to transmit an output signal of the first latch; And And a buffer configured to buffer the output signal of the second transfer gate to generate the buffered signal. The method of claim 9, wherein the second buffer means An AND circuit for ANDing the first control signal and the mode setting command; A third transmission gate for transmitting the output signal of the first latch in response to the output signal of the AND circuit; And And a second latch for resetting the mode setting signal, latching a signal output from the third transfer gate to generate the mode setting signal. The method of claim 13, wherein the second latch And a reset transistor for resetting the mode setting signal.