KR20030015653A - Stacked chip scale package and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A stack chip scale package is provided to highly integrate and miniaturize a memory product and to make a mass production without making a large investment through a conventional process. CONSTITUTION: An electronic circuit is integrated in a semiconductor chip(1). Elastomer(2) for attaching the chip is adhered to the upper surface of polyimide tape(3). A copper pattern(5) and resist(7) for protecting the copper pattern are adhered to the lower surface of the polyimide tape. A wire(4) electrically connects the chip with the copper pattern to transmit a signal. A plurality of the first and second solder balls(9a,9b) are melted and attached to a surface of the copper pattern to transmit the signal to the outside, connected to the copper pattern. A resin encapsulating unit(6) protects the chip and its peripheral constitution parts from outside oxidation and corrosion. The third chip scale package(8c) and the first and second chip scale packages(8a,8b) constitute a mirror type. A solder ball land corresponding to the second solder ball is formed in the third chip scale package. The second solder ball of the first and second chip scale package is connected to the solder ball land of the third chip scale package so that the first and second chip scale packages are electrically connected to the third chip scale package.

Description

Stacked chip scale package and manufacturing method thereof

The present invention relates to a laminated chip scale package and a method of manufacturing the same, and more particularly, to a laminated chip scale package and a method of manufacturing the same, which can realize a high integration, miniaturization and thinning of a memory product by stacking a conventional chip scale package. .

Currently, a chip scale package is being used that can reduce the size of a semiconductor package, reduce its size, and achieve high integration and high performance. As shown in FIG. The integrated semiconductor chip 1, an elastomer 2 for attaching the chip 1 to the upper surface, and a copper pattern 5 and a resistor 7 for protecting the copper pattern 5 are coated on the lower surface. Polyimide tape (3), the wire (4) to electrically connect the chip (1) and the copper pattern (5) to transmit a signal, the copper pattern (5) is connected to the copper pattern (5) to transmit a signal to the outside It consists of a plurality of solder balls (9) fused to one side of the) and the resin encapsulant (6) wrapped around the outside to protect the chip (1) and other peripheral components from external oxidation and corrosion.

In addition, the stack package is manufactured by stacking a plurality of chips in various forms or stacking a completed package in order to improve memory density and multifunction.

However, until now, most of the laminated packages have been manufactured using a single plastic package, and recently, each company is in the development stage to apply the stacking technology to the chip scale package, but there are not many special technologies released. However, with the recent demand for high integration of memory products and small and thin packaging technologies, stacking technology for chip-scale packages remains a necessary future task in each sector.

Accordingly, an object of the present invention is to provide a stacked chip scale package structure capable of stacking the above-described conventional chip scale package to achieve high integration, miniaturization, and thickness in a stacked package.

1 is a schematic diagram of a conventional single chip scale package;

2 is a schematic diagram of a stacked chip scale package according to the present invention;

3A is a schematic diagram illustrating first and second chip scale packages of a stacked chip scale package according to the present invention;

3B is a schematic diagram illustrating a third chip scale package of the stacked chip scale packages according to the present invention; And

3C is a schematic diagram of a state in which the first and second chip scale packages according to the present invention are stacked on the third chip scale package.

<Brief description of the main parts of the drawing>

One; Chip 2; Elastomer

3; Tape 4; wire

5; Copper pattern 6; Resin encapsulant

7; register

8a, 8b, 8c; First, second and third chip scale package

9; Solder balls 9a and 9b; 1st and 2nd solder ball

10; Solder ball land

In order to achieve the above object, the present invention provides a semiconductor chip in which an electronic circuit is integrated, a polyimide tape coated with an elastomer for attaching the chip to an upper surface thereof and a copper pattern and a resistor for protecting the copper pattern on the lower surface thereof, A wire that electrically connects the chip and the copper pattern to transmit a signal, and a plurality of first and second solder balls fused to one surface of the copper pattern and a chip and other peripheral components connected to the copper pattern to transmit a signal to the outside. The first and second chip scale packages and the first and second chip scale packages are formed in a mirror type with the first and second chip scale packages and the solder balls are not formed to protect against oxidation and corrosion. A third chip scale package, wherein some of the solder balls of the first and second chip scale packages are coupled to the solder ball lands of the third chip scale package Control the first and second chip-scale package and the third chip-scale package provides a stacked chip-scale package, it characterized in that it is electrically connected to each other.

In another aspect, the present invention (a) preparing the first and second chip scale package described above, (b) preparing the third chip scale package described above, (c) the first and second chip scale package described above A method of manufacturing a stacked chip scale package is provided that includes coupling to a third chip scale package.

Hereinafter, a multilayer chip scale package structure and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

As shown in Fig. 2, the stacked chip scale package according to the present invention is formed by combining a part of each of the first and second chip scale packages 8a and 8b with the third chip scale package 8c. The first and second chip scale packages 8a and 8b include a semiconductor chip 1 in which electronic circuits are integrated, an elastomer 2 for attaching the chip 1 to an upper surface thereof, and a copper pattern 5 on a lower surface thereof. Polyimide tape (3) coated with a resistor (7) to protect the copper pattern (5), a wire (4) and a copper pattern (4) for transmitting signals by electrically connecting the chip (1) and the copper pattern (5) ( 5) the plurality of first and second solder balls 9a and 9b fused to one surface of the copper pattern 5 and the chip 1 and its peripheral components to be externally oxidized and connected to transmit a signal to the outside. It is composed of a resin encapsulation material 6 wrapped around the outside to protect it from corrosion, and the third chip scale package 8c is formed in a mirror type with the first and second chip scale packages 8a and 8b. Although no solder balls are formed, only a plurality of solder ball lands corresponding to the second solder balls 9b are provided, so that the first and second chip scale packages are provided. Is to be attached to (8a, 8b) and the third when combined in a chip scale package (8c) of claim 1, a plurality of first pluralities of the second solder ball (9b) The above-described solder balls of a second chip-scale package (8a, 8b) lands. At this time, when the first and second chip scale packages 8a and 8b are combined with the third chip scale package 8c, the thickness of the second solder ball 9b fused with the third chip scale package 8c and the solder ball lands thereof. Should be smaller than the size of the first solder ball 9a. In this way, the first and second chip scale packages 8a and 8b and the third chip scale package 8c are electrically connected to each other by the second solder balls 9b. The first and second chip scale packages 8a and 8b are electrically connected to each other by the first solder balls 9a, so that the first, second and third chip scale packages and the substrate may transmit electrical signals to each other. It becomes possible.

In the above-described preferred embodiment of the present invention, a plurality of first and second solder balls 9a and 9b are formed in the first and second chip scale packages 8a and 8b, and solder balls are not formed in the third chip scale package 8c. However, only the first solder balls 8a are formed in the first and second chip scale packages 8a and 8b, and the second solder balls 8b are formed in the third chip scale packages 8a and 8b. 8b) and the third chip scale package 8c can be manufactured.

The total thickness of the laminated chip scale package according to the preferred embodiment of the present invention is preferably 1.2 mm, the thickness of the chip 1 is 150 μm, the thickness of the polyimide tape 3 is 75 μm, and the first solder balls 9 a. ), The size of 450 m, the thickness of the elastomer 2 is 50 m, the thickness of the copper pattern 5 is 18 m, and the thickness of the resistor 6 is preferably 20 m. However, for example, when the thickness of the chip 1 is 150 mu m or more, the thickness of the tape 3 or the elastomer 2 should be reduced or the size of the first solder ball 9a should be increased.

Next, a method of manufacturing a stacked chip scale package according to the present invention will be described with reference to FIGS. 3A to 3C. The manufacturing method is roughly three steps: preparing the first and second chip scale packages 8a and 8b, preparing the third chip scale package 8c, and preparing the first and second chip scale packages 8a, 8b) is combined with the third chip scale package 8c.

First, as shown in FIG. 3A, in preparing the first and second chip scale packages 8a and 8b, the first step is to fabricate a chip scale package such as a conventional microball grid array (BGA) and then perform a test. Only the chip scale packages passed through are carefully selected. The first solder balls 9a attached to the first and second chip scale packages 8a and 8b thus prepared are larger than the second solder balls 9b. By testing the chip scale package in advance, the defect rate of forming the stacked chip scale package can be greatly reduced.

Next, as shown in FIG. 3B, the third chip scale package 8c is prepared in a second step. At this time, the third chip scale package 8c is manufactured to have a mirror type with the first and second chip scale packages 8a and 8b obtained in the first step. Solder balls are not formed in the third chip scale package 8c manufactured in this step, and only a plurality of solder ball lands 10 are provided to correspond to the plurality of second solder balls 9b.

As shown in FIG. 3C, as a final step, the first and second chip scale packages 8a and 8b are coupled to the third chip scale package 8c. At this time, the second solder balls 9b of the first and second chip scale packages 8a and 8b are fused with the solder ball lands 10 of the third chip scale package 8c by an IR rays reflow process. Combined. As a result, the first and second chip scale packages 8a and 8b and the third chip scale package 8c are electrically connected to each other through the second solder ball 9b.

In the stacked chip scale package obtained as described above, the first, second and third chip scale packages are separately manufactured by using a wire bonding / beam lead bonding method, etc., respectively, and then only a chip scale package is used. It is possible to reduce the lamination defects by, and thus can almost eliminate the defects in the finished state, which is very advantageous in terms of price competition. In addition, the stacking process of the package can also be stacked and assembled using chip mounting technology in the existing module process, so that mass production can be performed by the existing process with a small investment.

By using the stacked chip scale package structure according to the present invention, it is possible to achieve high integration, miniaturization, and thickness in a memory product, and this package structure is excellent in price competitiveness and can be mass-produced in an existing process without significant investment. There is an advantage.

Claims (4)

A semiconductor chip in which an electronic circuit is integrated, an elastomer for attaching the chip to an upper surface thereof, a polyimide tape coated with a copper pattern and a resistor for protecting the copper pattern on a lower surface thereof, and electrically connecting the chip and the copper pattern A wire for connecting a signal and a plurality of first and second solder balls fused to one surface of the copper pattern so as to be connected to the copper pattern to transmit a signal to the outside, and external oxidation and corrosion of the chip and other peripheral components. First and second chip scale packages comprising a resin encapsulation material wrapped therein to protect against A third chip scale package formed in a mirror type with the first and second chip scale packages and having a solder ball land corresponding to the second solder balls; The second solder balls of the first and second chip scale packages are coupled to the solder ball lands of the third chip scale package so that the first and second chip scale packages and the third chip scale packages are electrically connected to each other. Stacked chip scale package. The multilayer chip scale package of claim 1, wherein a height of the first solder ball is greater than a sum of thicknesses of the second solder ball and the third chip scale package. (a) preparing the first and second chip scale packages of claim 1, (b) preparing the third chip scale package of claim 1, (c) coupling the first and second chip scale packages to the third chip scale package. 4. The method of claim 3, wherein said bonding is accomplished by an infrared rays reflow process.