KR20030009039A - Memory with Call Out Function - Google Patents

Abstract

The present invention relates to a storage system consisting of an array of storage cells having a bit mask circuit provided in each storage cell, said storage system further comprising a set of address bus lines, a set of data bus lines, an origin. And a bus circuit having a set of bus lines, and a set of control lines, each memory cell being connected to each of the set of lines. The control line selectively enables operation of the system in one of three modes of operation. The control line also includes a means for selecting one of a predetermined set of relationships to be used for the search operation. In the first mode of operation, the system stores the data applied to the data bus in a storage cell having a location formed by the data applied to the address bus.

In the second mode of operation, the storage cell having a position formed by the address bus sets the data stored in the cell on the data bus. In the third mode of operation, the retrieved data is applied to the address bus, which is retrieved by the manner in which each storage cell having matching data applies a value representing the address of the storage cell to the data bus, the storage cell being Verify a preselected relationship with an address byte applied to the address bus by another storage cell having data that matches the retrieved data, after which bits of the cell have matching data in the direction in which the location of the particular storage cell is affected It is masked by the bit mask circuit so that it appears on the cell address data bus only if it is closest to the data set on the origin bus among all the cells.

Description

Memory with Call Out Function

In computer systems, a central processing unit (CPU) is generally connected to a storage device. One routine operation to be performed by the CPU operation program is to scan a predetermined portion of the storage location to retrieve a storage cell in which specific data is stored. Since the location of the retrieved data is not known in advance, a scanning operation is a long process that allows the CPU to scan the entire portion of the storage, address each cell, read the data from the cell and compare it with the retrieved data. .

The known technology may be demonstrated by an example of a computer system having a storage device that stores an extensive list of data of other individuals whose names, ages and names are arranged in alphabetical order. If a list of all ages of 20 is required, the computer system scans the entire storage, reads each age of each person on the list, and records each name in a new list if the age is 20. . For a list of 100,000 people, the program would need to perform 100,000 operations.

Thus, there is a need to design a new time saving process for placing data in the storage system without scanning each of the storage system data. Such processes have almost common applications that improve efficiency in many areas, including personal computers, Internet servers, computer production methods, data processing, and other technologies using computer systems.

It is known to use content addressable storage (CAM) in the known art. However, existing CAM devices differ from conventional storage devices, and existing CAM devices require the use of specially adapted interface circuits (US Pat. No. 4,850,593). The prior art also has the drawback that individual devices are required to enable the system to perform conventional read / write operations and CAM data searching. Thus, it is desirable to have a CAM device that can be connected to the central processing unit via a data bus and an address bus and thus can be used in most conventional computer systems. It would also be desirable to have a device that could otherwise be operated in standard and call out modes.

In some known CAM systems, the response time typically increases with the size of the memory being searched for, because the cells are connected by a signal passing each cell in turn (US Pat. No. 4,850,593) or the scanning function is scanned. (US Pat. No. 5,502,832). In other known systems, the match signal propagates through the cells and passes through each of the cells in turn, so that when the match cell is far from the origin, the response time is long due to some propagation delay occurring in all cells.

In some CAMs of the known art, the address of the data to be stored is not specified. The device stores data at an address determined by the device logic, and retrieval of the data may be accomplished only by content addressing. Therefore, it is desirable to have a storage device in which data storage is performed by specifying an address of a cell on an address bus and providing data to the data bus to be stored, and the data can be stored and retrieved in the same manner as in a conventional storage device. A callout search mode is provided as an additional feature.

In another known apparatus described in US Pat. No. 5,554,616, the CAM includes a plurality of storage cells, each of which is provided with a match output line, and all match output lines from all cells match the highest priority. It is connected to a priority encryptor that generates an address for the cell. In a known technique of this type, the priority encryptor needs to include a number of inputs, one for each of the cells. Thus, a number of gates and a large surface may require the matching of lines from each of the cells to the priority encryptor. Since the routing is required to be considered, the capacity of these CAMs is very limited.

Therefore, it is desirable to have a call out storage device that is not operated through the entire circuit, in which case a "Call Out" function is added to each of the cells separately. In such a memory having parallel organization in which each cell is connected independently to the address bus, data bus and origin bus, the response time is not only dependent on the size of the memory but also utilizes the "call out" function. It does not depend on the position of the search data and the number of logic gates required to do so. This type of device has the advantage that large storage may be implemented at low cost and may also be used to implement large storage due to some "call out" devices of parallel structure.

The present invention relates to a method of increasing the speed of operation of an electronic search system, such as a computer search system, and to increased speed storage and circuitry used in the implementation of storage devices beneficial to computers, electronic systems, and Internet servers.

The apparatus and method of the present invention greatly enhances the search order of the system, which provides a means of retrieving the location of certain data already stored in the storage device while eliminating the need to scan all data in the storage device. Despite the fact that many cells of the memory may respond to the request, only one address appears due to the new logic elements included in the circuit of the present invention. Thus, the time required to retrieve one storage containing the retrieved data is reduced for a single storage cycle.

Fig. 1 shows a schematic structure of a call out memory according to the present invention, Fig. 2 is a schematic block diagram of a call out memory cell, and Fig. 3 shows a bit mask circuit for a set bit of a cell address. 4 shows an "priority mask" circuit, FIG. 5 shows an example of a "priority mask" circuit, and FIG. 6 shows a "range" used to select a cell having an address inferior to the origin. 7 shows an example of a logic device that can be used to select an input to a comparator.

The present invention relates to a method for increasing the operation speed of an electronic search system such as a computer search system and to an increased speed memory and circuit for use in the implementation of a storage device beneficial to a computer, an electronic system and an internet server.

The apparatus and method of the present invention greatly enhances the search order of the system, providing a means of retrieving the location of a given data already stored in the storage device while eliminating the need to scan all data in the storage device. Despite the fact that many cells of the memory may respond to the request, only one address appears due to the new logic included in the circuit of the present invention. Thus, the time required to retrieve one storage containing the retrieved data is reduced for a single storage cycle.

A set of lines of additional storage cells is used to form an "origin" for retrieval, and the address of the cell with the matching data indicated is the address closest to the "origin" address in the predefined direction, and the retrieval is It can be repeated in this direction until all matching data is located.

The storage device includes an array of new storage cells, each of which includes a masking circuit that selectively suppresses the output of the search data in accordance with the cell's position relative to the origin and other matching cells.

The memory device has a parallel structure in which each cell is independently connected to a bus system consisting of an address bus, a data bus and an origin bus. Data storage is done by specifying the address of the cell on the address bus and then sending the data to be stored on the data bus, where the data can be stored and retrieved in the same manner as in conventional storage, and a callout search mode is added. It is provided as a function.

In comparison with the above-described embodiment of the known art, only 50 people illustrate a storage device that stores data for 10,000 people who are 20 years old. The storage device of the present invention first programs to set the origin address at the address of the top item of the list in the predetermined direction. The system is then operated in call out mode and data (age 20) is set on the address bus. The callout storage then sets the address on the data bus for the 20-year-old person at the top of the list in the intended direction. The processor then reads the data from the address in standard mode and writes it to a new list. The processor then first sets the origin to the address of the retrieved name and repeats the search in callout mode. After repeating this procedure five thousand times, you get a complete list of the retrieved data (age: 20). The known technique requires 100,000 operations to reach the same result, which shows that the present invention is 20 times faster than the known technique.

An important advantage of the present invention is that the device can be sculpted in two different modes, in which the function in the first mode (standard) is similar to that of normal storage, and in the second mode (call out) the device executes the call out function. do.

Another advantage of the present invention is that the device structure is compatible with commonly used computer devices, and can be used with or instead of different types of standard storage devices.

Another advantage of the present invention is that large memory can be implemented at low cost since the number of logic gates required to perform the "call out" function increases only linearly with the size of the memory.

It is an object of the present invention to overcome the determination of existing storage systems by providing a combined call out storage and conventional storage method implemented in novel storage devices that can be applied to conventional electronic systems such as computer systems.

The storage device of the present invention includes an array of new storage cells, each of which includes a new type of storage band and a new circuit that implements a so-called " call out " function. The storage device can be operated in two different modes, a "standard" mode and a "call out" mode. According to a preferred embodiment, the mode of operation of the device is determined by a dedicated connection line. However, of course, the call out mode may be started by another interface as known.

In a storage device, a plurality of data lines are provided and connected in parallel to each of the storage cells, and these data lines are means for setting the "origin" of the search address. In the first embodiment, these data lines are set internally in a constant state representing an "origin" address by one special memory cell. In the second embodiment, an external device is used to set the state of these data lines.

Each cell can store and retrieve data in a manner known from commonly used storage devices. Data is stored or retrieved by a data line (data bus) that carries data to or from a processor such as a CPU. Other sets of lines (address buses) are used to send data to special storage cells for read or write operations, and in general multiple control lines are also used to perform the operations of read or write. The collection of data buses, address buses and control lines is generally referred to as a system bus. The system bus may additionally contain output lines.

In the method and system of the present invention, means are provided for installing the storage device in a callout mode such as a control line. In the "call out" mode, the role of address and data is reversed. The processor sets the data to be fetched to the "address bus" or part of it if the "address bus" has a smaller size than the "data bus". In each cell, a common circuit for comparing the address data applied to the address bus with the address data stored in the storage cell is currently used to compare the data stored in the cell with the address bus data. This is done by adding an electronic module that replaces the cell address with cell data for input into the comparator. In this context a match is associated with any predetermined relationship, such as equal, greater or less than any logical combination as known.

Some cells may contain matching data, but only one cell's address must be set on the data bus.

Thus, a new circuit is used to mask data on several lines, and the data appearing on the data bus represents only one address of the storage cell containing the retrieved data. It is a unique feature of the present invention that a masking circuit is added to each of the storage cells to form a parallel storage structure.

The mask circuit receives a data bus as an input. According to one preferred embodiment, an internal output bus is used as the intermediate buffer. If the storage cell contains data that matches that shown on the address bus, the address of this cell is logically combined in the priority mask circuit to be output on the data bus. Several cells, each containing matching data, may apply their address to the priority mask. However, the resulting data output for the data bus will represent the address of the cell with the closest address value in the predetermined direction for the " origin " address set on the " origin " line.

Although the present invention has been described with respect to embodiments in which the cell address is output to the data bus, it will be appreciated that other means, such as additional line sets, may be used for the same purpose. In particular, the output bus may be used as an intermediate buffer. Such an output bus is, of course, a practical and useful way of achieving a module that interfaces with a computer system.

An advantage of the apparatus and method of the present invention is that the time required for retrieving one particular word stored in the storage device can be equal to the time required for recording / retrieving data in standard mode, whereas in a standard computer system, Retrieval of a storage address where constant data is stored is a long operation since the CPU must scan the entire portion of the storage device until constant data is retrieved.

Another advantage of the present invention is that the storage device can be used in existing standard computer systems, and can advantageously replace the commonly used storage device.

According to another advantage of the method of the present invention, the time required to retrieve specific data is not only dependent on the data location but also on the number of cells contained in the storage.

Yet another advantage of the present invention is that some devices can be added in a modular fashion to expand the capacity of the storage device because of the parallel structure of the storage device of the present invention. Due to the scalability and the parallel structure of the device of the present invention, a number of devices can be installed in the computer system according to the size requirements of the computer system.

In addition, due to the parallel structure of the device of the present invention, the number of logic gates required to execute the " call out " storage device is directly proportional to the size of the storage device. In some known systems, such as CAM storage, the number of gates increases at a fairly high rate with increasing storage size. As a result, the device of the present invention can save considerable time and space as well as considerable cost.

According to another advantage of the present invention, a computer system may be designed such that all of its operating memory is a call out memory. Such a system, combined with appropriate software, can greatly improve the overall performance of a computer.

The logical functions of the circuits included in the memory of the present invention may be implemented in different but equivalent ways known in the art.

The present invention will be described with reference to a preferred embodiment of the storage device of the present invention. Here, the search direction is defined as a downward direction from the origin, and the storage cell to be searched has an address value smaller than that of the origin. However, the present invention is large; Equal or small; Of course, this can be done by clarifying other relationships between the origin and storage cells, such as the same or larger.

Fig. 1 shows a schematic structure of a preferred embodiment of the call out storage device of the present invention. As shown in Fig. 1, the call out storage device is composed of an array of storage cells. Each storage cell is connected to a system bus, i.e., an address bus, a data bus and a control line. Each memory cell is also connected to a plurality of origin lines, which form a so-called " origin " address. These lines can be connected within the device or to an external system, and their logic states form the "origin" for the search function. According to a preferred embodiment, when the call-out storage is operated in the search mode, only storage cells having an address value smaller than the "origin" address are searched. Another line, labeled CO in FIG. 1, exits the bus controller and is used to set up storage in the " call out " mode.

In a preferred embodiment, the system bus consists of the following components. That is, it consists of a "data bus" composed of a plurality of data lines and an "address bus" composed of a plurality of address lines.

A bus controller consisting of a plurality of "control lines" is provided in the storage of the present invention for bus synchronization. It is known to apply similar control lines to conventional computer systems to communicate with external storage and devices.

In the configuration of the present invention, only the following control lines included in the preferred embodiment are mentioned. That is, the "read / memory line" used to select the read or write operation, the "CO" line used to select the "callout" mode, and other controls that perform various functions as known to the bus system. Line is mentioned.

Each memory cell can store a number (Z) of bits in the memory portion.

Each storage cell receives as input an " CO " control line. This control line determines whether the cell is operated in standard storage mode ("standard mode") or in a new mode ("call out mode").

If the CO line is not active, the device functions as a standard storage array. If the CO line is active, the device functions in the new "call out" mode.

According to a preferred embodiment, the call out memory is intended to be used jointly with a central processing unit (CPU). However, the call out storage of the present invention is faced with the need to be used in electronic systems that do not include a CPU. In order to communicate with callout storage in callout mode, the CPU must first activate the CO signal. This can be done in many ways commonly used in electronic systems to select different devices connected to the system bus (so-called "chip selection").

In a first preferred embodiment, the CO line is activated by a logical combination of levels of specific address lines. This method is possible when the size of the memory used to be dedicated to several address line addressing various devices is smaller than the addressable space formed by the number of address lines. In the storage of the present invention, these extra lines may be used to address the storage in the call out mode. In other words, the decimal number CS of the address lines in Fig. 1 is used to " chip select " the call out function of the storage device. Since these fractional lines cannot be used to provide data to the callout memory, the maximum width of the data words that can be retrieved in "callout" mode is reduced to A-CS. Of course, if the size of the address bus exceeds the size of the data bus, no limitation is placed on the size of the search data as determined by the size of the data bus. This method is advantageous to the system when the number of address lines is larger than the size of data to be searched.

In a second preferred embodiment, a logic circuit is executed in the bus controller such that a read or write to a dedicated address sets up a CO line. In this embodiment the bus controller circuit detects a write / read at the address, sets up the CO line, and keeps the CO line active for the next bus period. The use of a bus controller with CO line control is a common technique in computer systems. In this embodiment, the width of the data to be retrieved is not reduced due to the need to activate the call out function, but the call out period requires two bus periods instead of a single period of the first preferred embodiment.

According to the present invention, any existing storage cell can be used to store the data to be retrieved by the storage arrangement of the present invention, and a new call out function is made possible by adding to the storage cell of the circuit described later.

Fig. 2 is a schematic block diagram of a circuit for a call out memory cell of the present invention according to a preferred embodiment, in which case " data storage circuit " is a circuit used for storing data. Such circuits have a typical use in storage devices.

2 is a schematic block diagram of a circuit for a callout memory cell of the present invention according to a preferred embodiment, in which case a "data storage circuit" is a circuit used for storing data, and " address / content selector " Such circuits have common uses in storage devices.

The " address / content selector " block of Fig. 2 represents special components added to the memory circuit in accordance with the present invention. As shown in Figure 2, this logic module receives as input CO lines. The address / content selector module provides a switching function for selectively connecting one of two sets of inputs (storage cell address and stored data) to the comparator input. When the CO line is in standard storage mode state, the cell address is applied to the comparator, and when the CO line is in "call out" storage mode, it is stored data that is applied to the comparator.

The " comparator " block in Fig. 2 shows a circuit commonly used in storage cells to compare address data applied to an address bus with a particular cell address. In a preferred embodiment, the comparator simply checks for equality of both data. However, in other embodiments, the comparator may check other relationships selected from the predetermined set. Examples of such relationships include Greater Than, Smaller Then and Same Sign. A few dedicated control lines may be used to select related relationships from a series of predetermined relationships. If both address data and cell address are found to match (i.e. verify the formed relationship), the cell select line is activated and the data stored in the cell is connected to the output bus for read or write operations. In the call out mode, the same comparator is used, but in the "call out" mode, this is the data of the address bus that is compared with the data stored in the storage cell.

Of course, different comparators may be used to perform the call out function and the standard storage function.

The comparator circuit activates "cell selection" according to its input, which is the address bus line on one side and the output of the address / content selector on the other side. "Cell Select" is activated in two cases.

In the first case the CO line is in "standard" mode and the cell's address matches the data applied to the address bus.

In the second case the CO line is in "call out" mode and the stored data inside of the storage cell matches the data applied to the address bus.

Also with reference to Fig. 2, a "bit mask" circuit has been added to the cell circuit to enable the execution of callouts. As shown in Fig. 2, the "bit mask circuit" is composed of a logic circuit, an "priority mask" circuit, and a "range" circuit for connecting to the data bus.

According to the method of the present invention, when the CO line is active and "cell selection" is also active because the cell data matches the data applied to the address bus, the set bit of the cell address is connected to the "bit mask" circuit to mask do. As shown in Fig. 2, the "bit mask" circuit includes a "range" circuit and a "priority mask" circuit. In the first step, the range circuit compares the cell address with the " origin " address and is sent to the priority mask between signals R (N) only if the cell address is smaller than the " origin " address.

The " priority mask " circuit then stores " OR " such that all set bits of all storage cells that store the retrieved data and fulfill the requirement of cell addresses smaller than the " origin " address set the corresponding bits of the " data bus ". The bits that are output to the data bus are selected by way of coupling to the function. Only bits selected by the "Priority Mask" circuit pass through to the "Data Bus". The overall function of the "bit mask" circuit is to mask the bit output which alters the high address output detected on the data bus. The data obtained on the data bus is the same as the address of the cell having the best address but smaller than the origin and containing the data corresponding to the data applied to the address bus.

It goes without saying that the above procedure relates to a top-down search. If the system is configured to do a bottom-up search, the selected address will be the smallest address that is larger than the origin.

Fig. 3 shows the execution of the "bit mask" function. When N designates a number representing a cell address, the binary expression of N can be expressed as follows.

Where u (N, k) is the set bit of the address value and K is the set number of bits of N-1.

For example, cell address 37 has a binary 100101.

Therefore, the following relationship is established.

K = 3; Bit 0, 2, and 5 setting

u (37,0) = 0; First set bit at position 0

u (37,1) = 2; Second set bit at position 2

u (37,2) = 5; Third set bit at position 5

3, there is shown a bit mask circuit for the set bits of the cell with address N, in which case the "origin of the search address" is the respective memory for the range circuit of the cell, the designated "origin address line". It is set by a number of lines connected in parallel in the cell. The logic level of the origin address line represents the "origin" address. These lines may for example be set by an external device. According to a preferred embodiment, the "origin of search" line may be connected to data written to one dedicated storage cell.

The "range circuit" in Fig. 3 compares the "origin" with the cell address N. If the cell address is smaller than the origin address, the signal R (N) is output to the priority mask. An embodiment of the comparison circuit is shown in FIG. As will be appreciated by those skilled in the art, a comparison circuit of the prior art may be used to perform the comparison function of the range circuit.

3, a "priority mask" circuit is included in the bit mask circuit, which has a K output line P [N, u (k)]. The priority mask circuit is described in detail later with respect to FIG. The function of the priority mask circuit is to determine which bits of the cell address are to be output to the data bus [B ₁ ]. The decision is made by the logical combination of the data bus itself and the current ecology of the cell address. This circuit function can be described as a feedback system between the data bus and the memory cell circuit. The state of the data bus is detected by a priority mask that sets the feedback output on the line P [N, u (N, k)] affecting the data bus.

The feedback method determines whether another cell is outputting address data on the data bus at a high address, and at its highest address whether it masks its own bit so that it is the only one that outputs its address on the data bus. Should be detected.

The above relates to downlink search, which is of course the lowest address to be placed on the data bus if the system is configured to uplink search.

The operation of the priority mask circuit is described as follows.

The retrieved data is displayed on the address bus and the origin address is set. For each memory cell an AND logical combination of " cell selection ", R (N) and CO line is executed to output the empowering signal " E " to the " priority mask. &Quot; Thus, the "priority mask" resets all P [N, u (N, k)] to zero logic if one of the following conditions is not met.

The cell address is higher than or equal to the origin address.

The data stored in the cell is the same as the data shown on the address bus.

-The device is not in "call out" mode.

All P [M, u (N, k)] lines from all storage cells M having a set of bits u (N, k) are input to an OR logic circuit, and the output of the circuit is a bit u (N, k). k) is set on the data bus. M is a generic term representing the addresses of all cells of a device having a set of bits u (N, k).

At the beginning of the call out period, the data bus line is in an inactive (logical 0) initial state. When using negative logic, for example, all lines are "pulled up" to the plus of the system power supply by a resistor. In the first step, the priority mask detects all these lines as inactive and outputs P [N, u (N, k)]. In this first step, many other cells also establish data bus lines by OR circuits. This new state of the data bus is then detected by each of the cell priority mask circuits, in accordance with the law of the priority mask, and some of the P [N, u (N, k)] lines are deactivated. Finally, the bits P [N, u (N, k)] that are not set to the address of the highest cell storing the retrieved data are reset and the data bus is set to the highest cell address. This method is asynchronous, and the time required to stabilize the lines to their normal values is about the same as the rise time of the electronic components of the circuit. As a result, the time required to retrieve one data has the same degree as a standard read or write cycle.

The "Priority Mask" circuit is shown in detail in connection with FIG. The "priority mask" circuit outputs bits P [N, u (N, k)] when the following conditions are met.

For highest bit set: u (N, K)

a) "Cell Select" and "R (N)" signals are active.

b) AND if all bits of the data bus higher than u (N, K) are not set.

If there is no high bit, i.e. the highest bit is bit Z, this bit is set directly by the "E" signal.

For another bit set: u (N, k), k <K

a) The most significant bit u (N, k + 1) is set.

b) AND if all bits of internal bus B [u (N, k)] between current bit u (N, k) and high bit u (N, k + 1) are not set.

This prevents the bit k and the low bit of the current cell address from being output when another cell with a high address outputs its address on the data bus in bits not set in the current cell. Finally, only the bits set in the best matching memory are output.

The above is described with respect to the downlink search, which is of course the lowest matching memory that will be output to the data bus if the system is configured to perform an uplink search.

Three set bits u (0) = 1: u (1) = 3: u (2) = to generate three outputs P [N, 1]: P [N, 3]: and P [N, 7] A specific example of the priority mask circuit operation for the cell address N = 10001010 with 7 is shown in FIG. In this particular example, E is used because there is no higher bit.

When used in the "standard" mode (CO line inactive), the function of the call out memory is exactly the same as that of the memory normally used. The address data is applied to the address bus, the control line is set to form a read or write operation, and the data is moved from or to the storage cell through the data bus. The addressed cell is selected by the comparator. The address / content selector detects the "CO" line and outputs the cell address to the comparator. When the address is retrieved to match the address data set on the address bus, a cell select line is set. When the read / write line is in the " write " state, the storage data storage circuit outputs data to the data bus. When the read / write line is in the "read" state, the storage data writer circuit stores data from the data bus. While operating in the standard mode, the bit mask circuit is set to inactive by the inactive state of the CO line.

When operated in the "call out" mode (CO line active), the data value to be retrieved is placed on the address bus and the read / write line is set to the "read" state. The address / content selector then applies the stored data to the comparator input. If there is a match, the cell select line is set. The bit mask circuit is set active by the CO line, but the data storage circuit is deactivated so as not to set any bus lines. In this state, only the bit mask applies data to the data bus.

The cell select signal is input to the bit mask circuit together with the origin address data preset in the origin address line. The bit mask circuit masks each bit so that the obtained data applied to the data bus is the data of the smallest address closest to the origin. Individual bits of an address from one or more cells may be output to the data bus even if the cell address is not closest to the origin. However, the data obtained for the data bus is the data of the nearest address.

The cycle may be repeated for the highest address currently being used as the address of the origin until all addresses of the cells containing the retrieved data are represented on the bus in order from highest to lowest. The duration of the search is equal to the duration of the N read and write cycles if N is the number of cells containing the required data.

The above is described for downlink search, where the data obtained for the data bus will be the highest address closest to the origin after a single period, whereas the data after several repetitions will be lowest if the system is configured to perform uplink search. Of course you will be shown on the bus from top to top.

The present invention relates to a method for increasing the operating speed of an electronic retrieval system and to an increased speed memory and circuit for use in the implementation of a computer, an electronic system, a storage device, the apparatus and method of the present invention being a constant stored in the storage device. It greatly improves the retrieval order of the system, providing a means of retrieving the location of the data while eliminating the need to scan all the data from storage.

Claims (9)

An array of storage cells each having a bit mask circuit; A set of address bus lines, a set of data bus lines, a set of origin bus lines, and a control circuit having a set of bus circuits, each memory cell connected to each of the sets of lines, and the control lines A storage system comprising means for placing a system in one of three modes of operation and a means for selecting one of a predetermined set of relationships used for a search operation, wherein in the first mode of operation the system is configured to apply data to said address bus. Storing the data applied to the data bus in a storage cell having a position formed by the memory cell; in the second operation mode, the storage cell having a position formed by the address bus sets the data stored in the cell to the data bus; In the mode, the data retrieved is applied to the address bus and this is the matching data. Each storage cell having a memory cell is retrieved by applying a value representing the address of the storage cell to a data bus, and the storage cell is stored by an address bus by another storage cell having data matching the retrieved data. Verify the pre-selected relationship with the address byte applied to the cell, and then the bit of the cell is closest to the data bus only if the location of the particular storage cell is closest to the data set on the origin bus among all cells with matching data in the predetermined direction. And is masked by said bit mask circuitry so as to appear in. A storage cell connected to a set of address bus lines, a set of data bus lines, a set of origin bus lines, and a set of control lines, the memory cells having a comparator, an address / content selector, and a bit mask circuit. And a mode of operation of the storage cell is selected by the control line such that the cell comparator can receive an address for comparing with the cell address in the first mode or retrieved data for comparison with data stored in the second mode. When a matching cell data is found in the second mode, the bit mask circuit logically combines a cell address with a predetermined origin address and address bits of another matching cell, and the cell address is closest to the origin address in a predetermined direction. Only day Memory cells, characterized in that indicate the bus. Bit mask consisting of a "range" circuit and a "priority mask" circuit that enables the retrieval of addresses of storage cells connected in parallel to the storage device without scanning all storage cells in a storage device having a data bus. In the circuit, the range circuit masks the cell address when the origin address is exceeded in a predetermined direction, and prevents the cell address from being set on the data bus, even when it is found that the cell data matches the retrieved data, The priority mask circuit logically combines the addresses of all cells appearing in the storage data bus, including the address of the cells, so that the address of the cells is stored in the storage data bus only when the addresses are closest to the origin address in the predetermined direction. Features to be indicated Bit mask circuit that. By placing the retrieved data on the address bus, by setting the cell comparator in data compare mode, and by setting the origin address for retrieval, the storage cell containing the retrieved data is located in the storage without scanning each of the storage cells. In the designation method, (a) the comparator compares the retrieved data with the data stored in the cell; (b) if the cell data is found to match, the range circuit masks the cell address if it does not execute a condition that is in a predetermined relationship with the origin address; (c) when executing a condition in which the cell address is in a predetermined relationship with the origin address, the cell address is set in the data bus; (d) the priority mask circuit receives, as a feedback input, data generated on the data bus from the outputs of the plurality of storage cells executing the condition; (e) The cell address has matching data and is logically combined with the address bits and priority mask circuits of other storage cells which execute the above conditions so that only the address of the cell closest to the origin address is represented on the data bus and all other addresses. And a step of masking by said priority mask circuit. 5. The method of claim 4, wherein said predetermined relationship is that a cell address must be lower than an origin address in a predetermined direction. 5. The method of claim 4, wherein the predetermined relationship is that the cell address must be lower than or equal to the origin address in the predetermined direction. 5. The storage cell of claim 4, wherein steps (a-d) are repeated with the address of the last cell indicated in the data bus set as the origin address until all cells containing the requested data have been retrieved. How to position the. Memory as described in connection with the accompanying drawings. A method of locating a storage cell that matches the retrieved data as described in relation to the accompanying drawings.