KR20030008374A - Circuit for Refreshing of DRAM Micro-controller - Google Patents

Circuit for Refreshing of DRAM Micro-controller Download PDF

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KR20030008374A
KR20030008374A KR1020010038918A KR20010038918A KR20030008374A KR 20030008374 A KR20030008374 A KR 20030008374A KR 1020010038918 A KR1020010038918 A KR 1020010038918A KR 20010038918 A KR20010038918 A KR 20010038918A KR 20030008374 A KR20030008374 A KR 20030008374A
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refresh
clock
dram
signal
stop mode
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KR1020010038918A
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Korean (ko)
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KR100418926B1 (en
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정철수
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주식회사 하이닉스반도체
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A refresh circuit of micro controller for DRAM is provided to be capable of preventing data loss at a stop mode of operation. CONSTITUTION: A clock divider circuit(22) divides an external clock signal to output the first clock signal, when a system operates at a normal mode. A stop mode control part(23) disables the clock divider circuit so as to stop generating the first clock signal when the system enters a stop mode by interruption of the external clock signal, and then outputs a stop mode flag signal. A refresh control part(24) generates the second clock signal in response to the stop mode flag signal. The refresh control part(24) outputs a refresh signal for enabling a refresh operation in response to the first clock signal at the normal mode.

Description

디램　마이크로 콘트롤러의 리프레쉬 회로{Circuit for Refreshing of DRAM Micro-controller}Circuit for Refreshing of DRAM Micro-controller

본 발명은 반도체　회로에 관한 것으로 특히, 스탑　모드(Stop Mode)시 디램에 들어있는 데이터(Data) 손실을 방지하기 위한 디램 마이크로 콘트롤러의 리프레쉬 회로에 관한 것이다.The present invention relates to a semiconductor circuit, and more particularly, to a refresh circuit of a DRAM microcontroller for preventing data loss in a DRAM during a stop mode.

이하, 첨부된 도면을 참조하여 종래 기술에 따른 디램 마이크로 콘트롤러　리프레쉬 회로를 설명하면 다음과 같다.Hereinafter, a DRAM microcontroller refresh circuit according to the prior art will be described with reference to the accompanying drawings.

도 １은 종래 기술에 따른 디램 마이크로 콘트롤러의　리프레쉬 회로를 나타낸 도면이다.1 is a diagram illustrating a refresh circuit of a DRAM microcontroller according to the prior art.

종래의 디램 내장형 마이크로 콘트롤러는 클럭 분주 회로부(12)와, 스탑 모드 제어부(13)와, 리프레쉬 제어부(14)로 구성된다.The conventional DRAM embedded microcontroller is composed of a clock division circuit section 12, a stop mode control section 13, and a refresh control section 14.

상기 클럭 분주 회로부(12)는 정상 모드시에 XTAL 패드(Pad)(11)를통하여　공급되는 외부 클럭을 분주하여 시스템 메인 클럭으로 출력하고, 이를 상기 리프레쉬 제어부(14)및 패리(Peri)1, 2(15a, 15d)에 전달한다.The clock division circuit unit 12 divides the external clock supplied through the XTAL pad 11 in the normal mode and outputs the system clock to the system main clock, and the refresh control unit 14 and Peri 1, 2 (15a, 15d).

그리고, 상기 스탑 모드 제어부(13)는 스탑 모드(Stop Mode)시에 상기　클럭분주　회로(12)의　동작을　멈추게　하기　위한　제어　신호를　출력한다.The stop mode control unit 13 outputs a control signal for stopping the operation of the clock division circuit 12 in the stop mode.

여기서, 상기스탑 모드는 상기 정상 모드의 반대 개념으로 상기 XTAL패드(21)를 통한 상기 외부 클럭 공급이 중단되는 경우를 가리킨다.Here, the stop mode refers to a case in which the external clock supply through the XTAL pad 21 is stopped in the opposite concept to the normal mode.

그리고, 상기 리프레쉬 제어부(14)는 디램(16)의 데이터를 리프레쉬시키기　위한　블록으로，　리프레쉬시켜야　할　데이터의　어드레스　즉，　리프레쉬　어드레스를 생성하여 이를 어드레스 버스에 출력하고, 디램 리프레쉬 동작을 인에이블시키기 위한 디램 리프레쉬 신호를 상기 디램(16)에 출력한다.The refresh control unit 14 is a block for refreshing the data of the DRAM 16. The refresh control unit 14 generates an address of the data to be refreshed, that is, a refresh address, outputs it to the address bus, and enables the DRAM refresh operation. The DRAM refresh signal is output to the DRAM 16.

여기서, 상기 어드레스 버스는 상기 패리1, 2(15a, 15b)디램(16)과 데이터　버스 사이에서 교환되는 데이터의 어드레스를 상기 패리12(15a, 15) 디램(16)에　각각 출력하는 버스로, 리프레쉬 제어부(14)에서 생성된 상기 리프레쉬 어드레스를상기 디램(16)에출력한다.Here, the address bus is a bus that outputs the address of the data exchanged between the parity 1, 2 (15a, 15b) DRAM 16 and the data bus to the parry 12 (15a, 15) DRAM 16, respectively. The refresh address generated by the refresh control unit 14 is output to the DRAM 16.

그리고, 상기 리프레쉬 제어부(14)는 리프레쉬 어드레스 생성부(14a)와 리프레쉬 카운터부(14b)로 구성된다.The refresh control unit 14 includes a refresh address generation unit 14a and a refresh counter unit 14b.

상기 리프레쉬 어드레스 생성부(14a)는 상기 리프레쉬 어드레스를 생성하여이를 상기 어드레스 버스에 출력한다.The refresh address generator 14a generates the refresh address and outputs the refresh address to the address bus.

그리고, 상기 리프레쉬 카운터부(14b)는 상기 클럭 분주 회로부(12)로부터의시스템 메인 클럭을 받아 상기 디램(16)의 리프레쉬 동작을 인에이블시키기 위한　디램 리프레쉬 신호를 출력한다.The refresh counter 14b receives the system main clock from the clock division circuit 12 and outputs a DRAM refresh signal for enabling the refresh operation of the DRAM 16.

상기한　종래의　디램　내장　마이크로　콘트롤러는　칩의　클럭이　멈춘　 경우　즉, 스탑 모드인 경우에　상기　스탑　모드　제어부(13)의 제어 신호에 의하여 상기 리프레쉬 카운터부(14b)의 동작이　멈추게　되고, 상기 시스템 메인 클럭공급이 중단되게 된다.The conventional DRAM built-in micro-controller stops the operation of the refresh counter 14b by the control signal of the stop mode control unit 13 when the clock of the chip is stopped, i.e., in the stop mode. The clock supply will be interrupted.

이에 따라 상기 리프레쉬 카운터부(14b)의 동작이 중단되게　되므로　스탑　모드에서　디램　셀(16) 데이터가 리프레쉬 되지　않게　된다.As a result, the operation of the refresh counter 14b is stopped, so that the DRAM cell 16 data is not refreshed in the stop mode.

따라서, 상기와 같은 종래의 디램　마이크로　콘트롤러의　리프레쉬　회로는 스탑　모드(Stop Mode)시 디램 셀 데이터가 리프레쉬 되지 않으므로 디램에 저장되어 있는 데이터가 손실되는 문제점이 있다.Therefore, in the conventional refresh circuit of the DRAM microcontroller, the DRAM cell data is not refreshed in the stop mode, so that the data stored in the DRAM is lost.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 스탑　모드에서　디램　데이터의　손실을　방지하기　위한　디램　마이크로　콘트롤러의　리프레쉬　회로를 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a refresh circuit of a DRAM microcontroller for preventing loss of DRAM data in a stop mode.

도 １은 종래 기술에 따른 마이크로 콘트롤러의 리프레쉬 회로를 나타낸 도면1 is a view showing a refresh circuit of a microcontroller according to the prior art.

도 ２는 본 발명에 따른 마이크로 콘트롤러의 리프레쉬 회로를 나타낸 도면2 illustrates a refresh circuit of a microcontroller according to the present invention.

도 ３은 본 발명의 마이크로 콘트롤러 리프레쉬 회로의 동작 순서를 나타낸　블록도3 is a block diagram showing an operation procedure of the microcontroller refresh circuit of the present invention;

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings

21 : XTAL 패드22 : 클럭　분주　회로부21: XTAL pad 22: clock division part circuit

23 : 스탑　모드　제어부24 : 리프레쉬　제어부23: stop mode control unit 24: refresh control unit

24a : 리프레쉬　어드레스　생성부24a: Refreshing 드 address generation unit

24b : 링 오실레이터부24c : 먹스24b: ring oscillator section 24c: mux

24d : 리프레쉬 카운터부25a,25b : 패리1, 224d: Refresh counter 25a, 25b: Parry 1, 2

26 : 디램26: DRAM

상기와 같은 목적을 달성하기 위한 본 발명에 따른 디램　마이크로　콘트롤러의　리프레쉬　회로는　시스템이　정상　모드일 경우 외부 입력 클럭 신호를 분주하여 제 １ 클럭으로 출력하는 클럭 분주 회로부와, 상기 외부 입력 클럭 신호　공급이 중단되어 시스템이 스탑 모드가 되면 상기 클럭 분주 회로부를 디스인에이블시어 제 １ 클럭 발생을 중단시키고 스탑 모드 플래그 신호를 출력하는 스탑 모드 제어부와, 상기　스탑　모드　플래그　신호에　따라서　제　２　클럭을　생성하고　시스템이　정상　모드인　경우에는　상기　제　１　클럭에　의하여　디램의　리프레쉬　동작을　인에이블시키기　위한　디램　리프레쉬　신호를　출력하고　스탑　모드일　경우에는　제　２　클럭에　의하여　상기　디램　리프레쉬　신호를　출력하는　리프레쉬　제어부를　포함하여　구성됨을　특징으로　한다.The refresh circuit of the DRAM microcontroller according to the present invention for achieving the above object includes a clock divider circuit unit for dividing an external input clock signal to output the first clock when the system is in the normal mode, and supplying the external input clock signal. When the system is stopped and the system enters the stop mode, the clock division circuit unit is disabled so that the first clock generation is stopped and the stop mode control unit outputs a stop mode flag signal, and generates a second clock according to the stop mode flag signal. In this normal mode, the DRAM refresh signal for enabling the DRAM refresh operation is output in accordance with the above 1st clock, and in the stop mode, the above DRAM refresh signal is output by the second clock. It is characterized by the fact that it is configured including the refresh control unit.

이하, 첨부된 도면을 참조하여 본 발명에 따른 디램　마이크로　콘트롤러의　리프레쉬　회로를 설명하면 다음과 같다.Hereinafter, the "refresh" circuit of the DRAM micro controller according to the present invention will be described with reference to the accompanying drawings.

도　２는　본　발명에　따른　디램　마이크로　콘트롤러의　리프레쉬　회로를　나타낸　도면이고, 도　３은　본　발명의　디램　마이크로　콘트롤러　리프레쉬　동작　순서를　나타낸　블록도이다.FIG. 2 is a diagram showing the refresh circuit of the DRAM microcontroller according to the present invention, and FIG. 3 is a block diagram showing the DRAM microcontroller refresh operation sequence of the present invention.

본　발명의　실시예에　따른　디램　내장형　마이크로　콘트롤러의　리프레쉬　회로는　도　２에　도시된　바와　같이, 클럭　분주　회로부(22)와　스탑　모드　제어부(23)와　리프레쉬　제어부(24)로　구성된다．According to an embodiment of the present invention, a refresh circuit of a built-in DRAM microcontroller is composed of a clock divider circuit section 22, a stop mode control section 23, and a refresh control section 24, as shown in FIG.

상기　클럭　분주　회로부(22)는　XTAL　패드(21)통하여　외부에서　공급되는　클럭을　분주하여　시스템　메인　클럭을　생성하고, 이를 패리１, ２(25a, 25b) 와　상기　리프레쉬　제어부(24)에　출력한다.The clock dispensing circuit unit 22 divides the clock supplied from the outside through the XTAL pad 21 to generate a system main clock, and outputs them to par 1, 2 (25a, 25b) and the refresh control unit 24.

그리고, 상기　스탑　모드　제어부(23)는 마이크로 콘트롤러가 스탑 모드(Stop Mode)에 진입하면 상기 XTAL 패드(21)를 통한 클럭 공급이 중단되므로　상기 클록 분주 회로부(22)가　동작하지　않도록　제어　신호를　출력하고, 상기　리프레쉬　제어부(24)에　스탑　모드임을　알리는　스탑　모드　플래그(Flag)를　출력한다.When the microcontroller enters the stop mode, the stop mode of the clock mode stops supplying the clock through the XTAL pad 21 so that the clock division circuit 22 does not operate. And outputs a "stop mode" flag (Flag) informing the refresh control unit 24 of the "stop mode".

그리고, 상기　리프레쉬　제어부(24)는　상기　스탑　모드　플래그와　시스템　메인　클럭을　받아　시스템　모드에　관계없이　디램　리프레쉬　동작을　인에이블시키　위한　디램　리프레쉬　신호를　출력하고, 리프레쉬되는　디램　셀의　어드레스　즉, 리프레쉬　어드레스를　생성하여　이를　어드레스　버스에　출력한다The refresh control unit 24 receives the stop mode flag and the system main clock and outputs a DRAM refresh signal to enable the DRAM refresh operation regardless of the system mode, and refreshes the address of the refreshed DRAM cell. Create and print them to the address bus

상기　어드레스　버스는　상기　패리1, 2(25a, 25b) 디램(26)과　데이터 버스간에 교환되는 데이터의　어드레스를　상기　페리1, 2 (25a, 25b), 디램(26)에　각각　출력하며, 리프레쉬　동작시에는　상기　리프레쉬　제어부(24)로부터의　상기　리프레쉬　어드레스를　받아　디램(26)에　출력한다.The address bus outputs the addresses of data exchanged between the parity 1, 2 (25a, 25b) DRAM 26 and the data bus to the ferry 1, 2 (25a, 25b), and the DRAM 26, respectively, and performs a refresh operation. At this time, the refresh refresh address from the refresh control unit 24 is received and output to the DRAM 26.

상기　리프레쉬　제어부(24)는　리프레쉬　어드레스　생성부(24a)와, 링　오실레이터부(24b)와, 먹스(24v)와, 리프레쉬　카운터부(24d)로　구성된다.The refresh control unit 24 is composed of a refresh address generating unit 24a, a ring oscillator unit 24b, a mux 24v, and a refresh counter unit 24d.

상기　리프레쉬　어드레스　생성부(24a)는　회로가　리프레쉬　동작을　하는　경우　상기　리프레쉬　어드레스를　상기　어드레스　버스에　출력한다．The refresh address generating section 24a outputs the refresh address to the address bus when the circuit performs a refresh operation.

그리고, 상기　링　오실레이터부(24b)는　상기　스탑　모드　제어부(23)로부터의　스탑　모드　플래그에　의해　인에이블（Enable)되어　서브　클럭(Sub Clock)을　출력한다．The ring oscillator unit 24b is enabled by the stop mode flag from the stop mode control unit 23 and outputs a sub clock.

그리고, 상기　먹스(24c)는　상기　스탑　모드　플래그　값에　따라서, 상기　서브　클럭과　상기　시스템　메인　클럭　중　어느　하나를　선택하여　출력한다The mux 24c selects and outputs one of the sub clock and the system main clock according to the stop mode flag value.

이때, 정상　모드에서는　상기　시스템　메인　클럭만이　출력되고　스탑　모드에서는　상기　서브　클럭만이　출력되므로　상기　먹스(24c)는　반드시　상기서브　클럭과　시스템　메인　클럭　중　어느　하나만을　선택하게　된다．At this time, since only the main system clock is output in the normal mode and only the sub clock is output in the stop mode, the mux 24c must select only one of the sub clock and the system main clock.

그리고, 상기　리프레쉬　카운터부(24d)는　상기　먹스(24c)로부터의　신호에　의하여　리프레쉬　동작을　인에이블시키기　위한　디램　리프레쉬　신호를　상기　디램(26)에　출력한다．The refresh counter unit 24d then outputs a DRAM refresh signal to the DRAM 26 for enabling the refresh operation in response to the signal from the mux 24c.

상기와　같이　구성되는　디램　마이크로　콘트롤러　리프레쉬　회로의　동작은　도　３에　도시된　바와　같이, 마이크로　콘트롤러의 동작이 개시되어(3a) 마이크로　콘트롤러에 전원이 공급되게 되면(3b), 마이크로　콘트롤러에　리셋　신호를　인가하여　초기화시키어(3c), 마이크로　콘트롤러의　정상　동작(3d)을　수행하게된다．The operation of the microcontroller refresh controller circuit configured as described above is similar to that shown in Fig. 3, when the operation of the microcontroller is started (3a) and the microcontroller is supplied with power (3b), and the reset signal is applied to the microcontroller. In this case, it initializes (3c) and performs the normal operation (3d) of the microcontroller.

정상 동작에서는　상기　클럭　분주　회로부(22)에서　출력되는　시스템　메인　클럭에　의한　디램　리프레쉬　신호가　출력되게　된다．In normal operation, the DRAM refresh signal by the system main clock output from the clock division circuit 22 is outputted.

이후, 상기 마이크로 콘트롤러의 모드를 관찰하여(3e), 상기　마이크로　콘트롤러가 　스탑　모드로　들어가면　상기　스탑　모드　제어부(23)에서　스탑　모드　플래그　신호를　발생시키고(3g), 그렇지　않으면　즉, 정상　모드이면　마이크로　콘트롤러　정상　동작을　수행(3f)한다．Then, by observing the mode of the microcontroller (3e), when the microcontroller enters the stop mode, the stop mode control unit 23 generates a stop mode flag signal (3g), otherwise it is a normal microcontroller. Perform normal operation (3f).

시스템이　스탑　모드인　 경우에는　상기　스탑　모드　플래그　신호에　의하여　링　오실레이터(24b)가　동작하게　되고(3h), 상기　링　오실레이터(24b)로부터　서브　클럭이　발생되게　된다(3i)．When the system is in the stop mode, the ring oscillator 24b is operated in response to the stop mode flag signal (3h), and a sub clock is generated from the ring oscillator 24b (3i).

따라서, 정상 모드에서 상기 시스템　메인　클럭이 서브 클럭으로 대체되게　되어(3j) 시스템이 스탑 모드의　리프레쉬 동작을 수행하게 된다(3k)．Therefore, in the normal mode, the system main clock is replaced by the sub clock (3j), so that the system performs the stop mode of the refresh operation (3k).

상기와 같은 본 발명의 디램　마이크로　콘트롤러의　리프레쉬　회로는　스탑　모드에서도　디램　리프레쉬　동작을　수행할　수　있으므로　시스템　오프시에도　데이터　손실을　방지할　수　있는　효과가 있다.As described above, the refresh circuit of the DRAM microcontroller of the present invention can perform the DRAM refresh operation even in the stop mode, so that data loss can be prevented even when the system is turned off.

Claims (4)

시스템이 정상 모드일 경우 외부 입력 클럭 신호를 분주하여 제 １ 클럭으로 출력하는 클럭 분주 회로부와,A clock division circuit unit for dividing an external input clock signal and outputting the first clock when the system is in a normal mode; 상기 외부 입력　클럭 신호　공급이　중단되어　시스템이　스탑　모드가　되면　상기　클럭　분주　회로부를　디스인에이블시어 제１클럭 발생을 중단시키고，스탑 모드 플래그 신호를출 력하는 스탑 모드 제어부와，A stop mode control unit which stops the generation of the first enable clock signal and outputs a stop mode flag signal when the external input clock signal supply is stopped and the system enters the stop mode; 상기　스탑　모드　플래그　신호에　따라서　제　２　클럭을　생성하고，　시스템이　정상　모드인　경우에는　상기　제　１　클럭에　의하여　디램의　리프레쉬　동작을　인에이블시키기　위한　디램　리프레쉬　신호를　출력하고　스탑　모드일　경우에는　제　２　클럭에　의하여　상기　디램　리프레쉬　신호를　출력하는　리프레쉬　제어부를　포함하여　구성됨을　특징으로　하는　디램　마이크로콘트롤러의　리프레쉬　회로．According to the Stop mode flag signal, the second clock is generated and when the system is in normal mode, the clock refresh mode for outputting the DRAM refresh signal to enable the clock refresh operation in case of the system is in the normal operation mode. The refresh circuit of the DRAM microcontroller is characterized by being configured to include a refresh control section for outputting the DRAM refresh signal. 제　１　항에　있어서，　상기　리프레쉬　제어부는　The refresh control unit described in Clause 11 is 상기　스탑　모드　플래그　신호에　의해　인에이블되어　제　２　클럭을　발생시키는　오실레이터와，An oscillator enabled by the stop mode flag signal to generate a second clock; 스탑　모드　플래그　신호에　따라서　상기　제　１　클럭　또는　제　２　클럭　중　어느　하나를　선택하는　스위치부와，A switch section for selecting either the above first clock or second clock according to the stop mode flag signal; 상기　스위치부의　신호를　받아　상기　디램　리프레쉬　신호를　출력하는　리프레쉬　카운터부로　구성됨을　특징으로　하는　디램　마이크로　콘트롤러의　리프레쉬　회로．A refresh circuit of a DRAM microcontroller, characterized in that it is composed of a refresh counter unit for receiving the signal of the switch unit and outputting the DRAM refresh signal. 제　１　항에　있어서，　상기　리프레쉬　제어부는　　리프레쉬되는　디램의　어드레스를　생성하여　출력하는　리프레쉬　어드레스　생성부를　더　포함하여　구성됨을　특징으로　하는　디램　마이크로　콘트롤러의　리프레쉬　회로．The refresh circuit of the DRAM microcontroller according to claim 11, wherein the refresh control unit is configured to include a refresh address generator which generates and outputs an address of the refreshed DRAM. 제　２　항에　있어서，　상기　스위치부는　제　１　클럭과　제　２　클럭을　입력으로　하는　２－입력（Input)　먹스인　것을　특징으로　하는　디램　마이크로　콘트롤러의　리프레쉬　회로．2. The refresh circuit of the DRAM microcontroller, which is characterized in that the switch unit is a 2-input mux for inputting the first clock and the second clock as inputs.
KR10-2001-0038918A 2001-06-30 2001-06-30 Circuit for Refreshing of DRAM Micro-controller KR100418926B1 (en)

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