KR20030003874A - Semiconductor package using tape thermal interface material and the method of manufacturing for the same - Google Patents

Semiconductor package using tape thermal interface material and the method of manufacturing for the same Download PDF

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Publication number
KR20030003874A
KR20030003874A KR1020010039726A KR20010039726A KR20030003874A KR 20030003874 A KR20030003874 A KR 20030003874A KR 1020010039726 A KR1020010039726 A KR 1020010039726A KR 20010039726 A KR20010039726 A KR 20010039726A KR 20030003874 A KR20030003874 A KR 20030003874A
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South Korea
Prior art keywords
tim
tape
chip
semiconductor package
lid
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KR1020010039726A
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Korean (ko)
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김대영
김희석
오선주
송근호
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삼성전자 주식회사
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Priority to KR1020010039726A priority Critical patent/KR20030003874A/en
Publication of KR20030003874A publication Critical patent/KR20030003874A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29618—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83418—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/83424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor package using a tape thermal interface material(TIM) is provided to easily optimize heat radiation of the semiconductor package by uniformly forming the tape TIM of an optimum thickness. CONSTITUTION: A TIM is prepared. The TIM of a predetermined thickness is screen-printed on one surface of both-sided tape to form the tape TIM(1). The tape TIM is punched to correspond to the size of the rear surface of a chip(3) to which the tape TIM is to be attached. The punched tape TIM is transferred and attached to the rear surface of the chip flip-bonded to a substrate(5). A chip mounting part is sealed by a lid(22). The lid is attached to the upper surface of the tape TIM on the rear surface of the chip and to the upper surface of the substrate in the outer of the chip.

Description

테입 ＴＩＭ을 사용하는 반도체 패키지 및 그 제조 방법 {Semiconductor package using tape thermal interface material and the method of manufacturing for the same}Semiconductor package using tape thermal interface material and the method of manufacturing the same {Semiconductor package using tape thermal interface material and the method of manufacturing for the same}

본 발명은 스크린 인쇄 방식에 의해 TIM(thermal interface material)이 테입에 부착되어 형성된 테입 TIM을 사용하는 반도체 패키지 및 그것의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package using a tape TIM formed by attaching a thermal interface material (TIM) to a tape by screen printing, and a method of manufacturing the same.

플립 칩 기술은 솔더 범프, 금속 야금 범프, 컴플라이언트(compliant) 범프를 이용하여 칩표면을 기판에 마주보게 실장하는 것으로서, 1960년대 초반의 IBM사의 솔더 범프 플립 칩 기술인 C4(Controlled Collapse Chip Connection)가 대표적인 기술로 알려져 있다. 본 기술에 따른 제조 공정에서 고속 CPU(>1GHz, EV68-CU이후 제품)에 0.18㎛ 공정이 사용되고 있다. 상기 공정에서는 CPU의 고속 동작으로 인해 전력 소비가 증가하게 되며, 이로 인해 FC CPU(EV68)의 동작 주파수는 1GHz 이상이고, 전력은 65~100와트 이상이며, 접합(junction) 온도가 상승하게 된다.Flip chip technology uses solder bumps, metal metallurgy bumps, and compliant bumps to mount the chip surface directly to the substrate.In the early 1960s, IBM's Controlled Collapse Chip Connection (C4) solder bump flip chip technology was used. It is known as a representative technique. In the manufacturing process according to the present technology, a 0.18 μm process is used for a high speed CPU (> 1 GHz, products after EV68-CU). In the above process, the power consumption increases due to the high speed operation of the CPU. As a result, the operating frequency of the FC CPU EV68 is 1 GHz or more, the power is 65 to 100 watts or more, and the junction temperature is increased.

이에 따라, 접합 온도를 감소시키기 위해서 2.78~3.18w/m,k의 열전도성을 지니는 TIM을 칩 바닥면에 디스펜싱(dispensing)하여 부착하게 되었다. 또한, 접합 온도를 가장 낮게 하기 위해서는 50㎛ 두께의 TIM을 사용한 경우가 가장 좋은 열방출 특성을 갖는 것으로 확인되었다.Accordingly, in order to reduce the junction temperature, a TIM having a thermal conductivity of 2.78 to 3.18 w / m, k was dispensed and attached to the bottom surface of the chip. In addition, in order to minimize the junction temperature, it was confirmed that the case of using a TIM having a thickness of 50 µm had the best heat dissipation characteristics.

종래에는 접합 온도의 상승을 방지하기 위하여 TIM을 기판상의 칩에 도포하는데 도포기를 사용한 노즐 토출 방식이 사용되었다.Conventionally, a nozzle ejection method using an applicator has been used to apply a TIM to a chip on a substrate in order to prevent an increase in the junction temperature.

상술한 노즐 토출 방식에 의해 칩에 도포된 TIM을 사용한 반도체 패키지 및그것의 제조 방법을 도 8a 내지 도 10을 참조로 설명한다.A semiconductor package using a TIM coated on a chip by the nozzle ejection method described above and a manufacturing method thereof will be described with reference to FIGS. 8A to 10.

도 8a 내지 도 8c는 종래 도포기의 구조, 도 9는 종래의 도포기를 사용하여 칩후면에 TIM을 도포한 상태, 그리고 도 10은 칩에 도포된 TIM의 상부를 리드(lid)로 덮어서 형성된 패키지를 각각 나타낸다.8A to 8C are structures of a conventional applicator, FIG. 9 is a state in which a TIM is applied to the rear surface of a chip using a conventional applicator, and FIG. 10 is a package formed by covering a top of a TIM applied to a chip with a lid. Respectively.

도 8a 내지 도 8c에 도시된 바와 같이, 종래 도포기는 엔코더(encoder)(12), 모터(13), 젤상태의 유체로된 TIM(도 9의 11)이 저장된 시린지(syringe)(14), 상하 운동이 가능한 어거 스크류(auger screw)(15) 및 디스펜싱 니들(dispensing needle)(16)로 구성된다. 여기서 모터(13)는 어거 스크류(15)의 상하 운동을 실행시켜 주기 위한 것이고, 시린지(14)는 내부에 저장된 TIM을 어거 스크류(15)로 보내며, 디스펜싱 니들(16)은 보내진 TIM을 칩후면에 디스펜싱하는 기능을 한다.As shown in Figs. 8A to 8C, a conventional applicator includes an encoder 12, a motor 13, a syringe 14 in which a TIM (11 in Fig. 9), which is a fluid in a gel state, is stored; It consists of an auger screw 15 and a dispensing needle 16 capable of vertical movement. Here, the motor 13 is for carrying out the up and down motion of the auger screw 15, the syringe 14 sends the TIM stored therein to the auger screw 15, and the dispensing needle 16 chips the sent TIM. Dispensing on the back.

젤(gel) 상태의 유체로 된 TIM은 시린지(14)에 저장되어 있다가 어거 스크류(15)로 방출되어 나사산을 따라 아래쪽으로 내려와서 모터(13)에 의해 상하 운동이 반복되는 과정중에 디스펜싱 니들(16)로 공급되게 되며, 디스펜싱 니들(16)로 공급된 TIM은 소정의 두께로, 바람직하게는 50㎛ 두께로 칩후면에 균일하게 디스펜싱되게 된다.The gel fluid TIM is stored in the syringe 14 and is released by the auger screw 15 to descend downward along the thread, dispensing during the up-and-down movement by the motor 13. The TIM is supplied to the needle 16, and the TIM supplied to the dispensing needle 16 is uniformly dispensed on the rear surface of the chip to a predetermined thickness, preferably 50 mu m thick.

상술한 방법에 의해 TIM(11)이 칩(3)에 도포된 상태가 도 9에 도시되어 있다.The state in which the TIM 11 is applied to the chip 3 by the above-described method is shown in FIG. 9.

이렇게 도포된 TIM은, 도 10에 도시된 바와 같이, TIM(11) 위에 실장된 리드(lid)(22)에 의해 눌려져 일정한 두께로 평평하게 된다. 실장된 리드(22)는 패키지(5)와 각 가장자리가 맞닿으며 밀봉제(23)에 의해 밀봉되어, 패키지가 형성된다.The thus applied TIM is pressed by a lid 22 mounted on the TIM 11 and flattened to a constant thickness, as shown in FIG. 10. The packaged lead 22 is abutted with the package 5 and its edges are sealed by a sealant 23 to form a package.

그러나, 상술한 TIM 도포 공정시에는 칩후면에 도포되는 TIM의 두께를 최적으로 조절하기 위해서 시린지에서 토출되는 유체의 디스펜싱양을 매 작업을 진행할 때 마다 조절해야한다. 또한, 작업 진행 중 어거 스크류는 상하 운동을 반복하게 되고, 100,000cps 정도의 점도를 갖는 TIM이 어거 스크류를 타고 내려와 디스펜싱 니들을 통해 분사되기 때문에, 작업을 마친 후 장시간 시린지를 방치하게 되면 TIM이 어거 스크류에 잔존하게 된다. 따라서, 추가 작업 공정이 진행되는 경우 경화된 유체에 의해 디스펜싱이 방해를 받거나, 최악의 경우 시린지가 경화된 유체에 의해 작동되지 않는 경우가 발생하게 된다. 이를 방지하기 위하여 종래에는 주기적으로 시린지를 클리닝(cleaning)하고 노즐 교체를 실시해야만 했다.However, in the above-described TIM coating process, in order to optimally adjust the thickness of the TIM applied to the rear surface of the chip, the amount of dispensing of the fluid discharged from the syringe should be adjusted at every operation. In addition, the auger screw repeatedly moves up and down while the work is in progress, and the TIM having a viscosity of about 100,000 cps descends through the auger screw and is injected through the dispensing needle. It remains in the auger screw. Thus, dispensing is hindered by the cured fluid when further work processes are underway, or, in the worst case, the syringe is not operated by the cured fluid. In order to prevent this, conventionally, the syringe had to be periodically cleaned and nozzle replacement performed.

또한, 도 10에 도시된 바와 같이, 종래의 유체 토출 방식은 리드(22)를 TIM 위에 덮어야만 칩후면(3a)에 디스펜싱된 TIM(11)의 두께를 조절할 수 있는 단점이 있었으며, 최적의 열방출 특성을 높이기 위해서, 즉 TIM의 두께를 50㎛로 하기 위해서 리드(22)의 두께를 제작 오차인 ±20㎛를 감안해서 설계해야 하는 번거로움이 있었다.In addition, as shown in FIG. 10, the conventional fluid discharging method has a disadvantage in that the thickness of the TIM 11 dispensed on the rear surface 3a of the chip 22 must be covered only by covering the lid 22 over the TIM. In order to increase the heat dissipation characteristics, that is, to make the thickness of the TIM 50 μm, it was troublesome to design the thickness of the lead 22 in consideration of ± 20 μm, which is a manufacturing error.

또한, 리드 제작시 공차가 ±20㎛로 크기 때문에 50㎛ 이하의 얇은 두께의 TIM을 요하는 경우에는 기존 방식으로 적용할 수 없다는 문제점이 있었다.In addition, there is a problem that can not be applied to the conventional method in the case of requiring a thin thickness of less than 50 ㎛ TIM because the tolerance is large ± 20 ㎛ when manufacturing the lead.

따라서, 본 발명의 목적은 상술한 문제점을 해결할 수 있는 테입 TIM을 사용하는 반도체 패키지 및 그것의 제조 방법을 제공하는 것이다.Accordingly, it is an object of the present invention to provide a semiconductor package using a tape TIM and a method for manufacturing the same, which can solve the above problems.

도 1은 본 발명에 따른 바람직한 실시예의 반도체 패키지를 나타내는 개략도,1 is a schematic diagram showing a semiconductor package of a preferred embodiment according to the present invention;

도 2는 도 1의 본 발명의 반도체 패키지를 제조하기 위한 장치의 전체 구조를 나타내는 개략도,2 is a schematic diagram showing an overall structure of an apparatus for manufacturing the semiconductor package of the present invention of FIG.

도 3는 본 발명의 바람직한 실시예에 따라 TIM이 테입에 접착된 상태를 나타내는 도면,3 is a view showing a state in which the TIM is bonded to the tape according to a preferred embodiment of the present invention,

도 4은 도 3에서 형성된 본 발명의 테입 TIM이 릴(reel) 형태로 감겨져 있는 모습을 나타내는 개략도,4 is a schematic view showing a tape TIM of the present invention formed in FIG. 3 wound in a reel form;

도 5는 본 발명의 테입 TIM이 펀칭되는 모습을 나타내는 개략도,5 is a schematic view showing a state in which the tape TIM of the present invention is punched out,

도 6a는 도 5에서 펀칭된 테입 TIM이 콜렛에 의해 픽업(pick up)되는 상태를 나타내는 개략도,6A is a schematic diagram showing a state in which the tape TIM punched in FIG. 5 is picked up by a collet;

도 6b는 도 6a의 콜렛부분의 확대 단면도,6B is an enlarged cross-sectional view of the collet portion of FIG. 6A;

도 7a는 기판 상에 실장된 칩의 후면을 나타내는 개략도,7A is a schematic diagram illustrating a rear surface of a chip mounted on a substrate;

도 7b는 칩에 테입 TIM이 부착된 상태를 나타내는 단면도,7B is a cross-sectional view illustrating a state in which a tape TIM is attached to a chip;

도 8a는 종래 도포기 구조를 나타내는 개략도,8A is a schematic diagram showing a conventional applicator structure,

도 8b는 도 8a의 도포기 구조의 어거 스크류 및 니들 부분의 확대도 중 어거 스크류가 하강된 상태를 나타내는 개략도,FIG. 8B is a schematic view showing the auger screw being lowered out of an enlarged view of the auger screw and the needle portion of the applicator structure of FIG. 8A;

도 8c는 도 8a의 도포기 구조의 어거 스크류 및 니들 부분의 확대도 중 어거 스크류가 상승된 상태를 나타내는 개략도,FIG. 8C is a schematic view showing the auger screw in a raised state of the auger screw and the needle portion of the applicator structure of FIG. 8A, FIG.

도 9는 종래 기술에 의해 칩후면에 TIM이 도포된 상태를 나타내는 개략도, 및9 is a schematic view showing a state in which the TIM is applied to the rear surface of the chip by the prior art, and

도 10은 종래 반도체 기판상에 리드(lid)가 부착된 상태를 나타내는 개략도이다.10 is a schematic view showing a state in which a lid is attached to a conventional semiconductor substrate.

<도면의 주요부호에 대한 간단한 설명><Brief description of the major symbols in the drawings>

1; 테입 TIM 2; 콜렛(collet)One; Tape TIM 2; Collet

3; 칩(3a; 칩후면) 4; 언더필(underfill) 재료3; Chip 3a (back of chip) 4; Underfill material

5; 기판 6; 솔더 범프5; Substrate 6; Solder bump

10; 이송암 11; TIM10; Transfer arm 11; TIM

12; 엔코더(encoder) 13; 모터12; Encoder 13; motor

14; 시린지(syringe) 15; 어거 스크류(auger screw)14; Syringe 15; Auger screw

16; 디스펜싱 니들(dispensing needle)16; Dispensing needle

20; 펀칭기 21; 양면 테입20; Punching machine 21; Double sided tape

22; 리드(lid) 23; 밀봉제22; Lid 23; Sealant

24; 콘덴서24; Condenser

상기 목적을 달성하기 위해서, 본 발명은 기본적으로 열전도성이 2.78~3.18w/m,k, 충전양은 87±5%, 최대 충전 두께가 70㎛인 특성을 가지며, 실리콘, 아연 및 알루미늄으로 이루어진 그룹으로부터 선택된 TIM을 허용오차가 ±5㎛인 스크린 인쇄 방식에 의해 테입에 도포되어 형성된 테입 TIM을 사용하는 반도체 패키지를 제공한다.In order to achieve the above object, the present invention basically has a thermal conductivity of 2.78 ~ 3.18w / m, k, the filling amount of 87 ± 5%, the maximum filling thickness of 70㎛, a group consisting of silicon, zinc and aluminum Provided is a semiconductor package using a tape TIM formed by applying a TIM selected from the tape to a tape by a screen printing method having a tolerance of ± 5 μm.

본 발명은 또한 전술된 테입 TIM을 사용하는 반도체 패키지의 제조 방법을 제공한다. 즉, TIM을 준비하는 단계, TIM을 테입에 스크린 인쇄하여 테입 TIM을 형성하는 단계, 테입 TIM을 부착될 칩후면 크기에 맞게 펀칭하는 단계, 펀칭된 테입 TIM을 이송하여 패키지 기판에 플립칩 본딩된 칩후면에 부착하는 단계, 및 테입 TIM이 부착된 칩을 리드(lid)로 덮어 패키지를 형성하는 단계로 이루어지는 패키지 제조 방법을 제공한다.The present invention also provides a method of manufacturing a semiconductor package using the tape TIM described above. That is, preparing a TIM, screen-printing the TIM on the tape to form a tape TIM, punching the tape TIM according to the size of the chip back surface to be attached, and transferring the punched tape TIM to flip chip bonding to the package substrate. It provides a package manufacturing method comprising the step of attaching to the back of the chip, and forming a package by covering the chip with the tape TIM attached with a lid (lid).

본 발명의 바람직한 실시예에 따른 테입 TIM을 사용한 반도체 패키지 및 그것의 제조 방법을 도 1 내지 도 7b를 참조로 설명한다. 도 1은 본 발명에 따른 테입 TIM을 사용하여 형성된 반도체 패키지의 개략도이다. 도 2는 도 1의 반도체 패키지를 제조하기 위한 장치의 전체 구조를 나타내는 개략도이다. 도 3은 TIM(11)이 양면 테입(21)에 도포된 상태, 도 4는 테입 TIM(1)이 릴(reel) 형태로 장착된 상태, 도 5는 본 발명에 따른 펀칭기(20), 도 6a 및 도 6b는 펀칭된 테입 TIM(1)이 픽업되는 상태, 그리고 도 7a 및 도 7b는 테입 TIM(1)이 칩후면(3a)에 부착된 상태를 각각 나타내는 도면들이다.A semiconductor package using a tape TIM according to a preferred embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS. 1 to 7B. 1 is a schematic diagram of a semiconductor package formed using a tape TIM according to the present invention. FIG. 2 is a schematic diagram illustrating an overall structure of an apparatus for manufacturing the semiconductor package of FIG. 1. 3 is a state in which the TIM 11 is applied to the double-sided tape 21, FIG. 4 is a state in which the tape TIM 1 is mounted in a reel form, and FIG. 5 is a punching machine 20 according to the present invention. 6A and 6B show the punched tape TIM 1 being picked up, and FIGS. 7A and 7B show the tape TIM 1 attached to the chip back surface 3a, respectively.

우선, 본 발명의 테입 TIM(1)을 사용하는 반도체 패키지에 대해 살펴보도록 한다. 본 발명의 바람직한 실시예에 따른 반도체 패키지에 사용된 테입 TIM(1)은, 도 3에 도시된 바와 같이, 양면 테입(21)의 상부에 TIM(11)을 도포함으로써 만들어진다. 이때 사용되는 TIM(11)은 열전도성이 2.78~3.18w/m,k, 충전양은 87±5%, 최대 충전 크기가 70㎛이며, 실리콘, 아연 및 알루미늄으로 이루어진 그룹으로부터 선택되어지고, 도포 작업은 허용오차가 ±5㎛인 스크린 인쇄 방식에 의해 이루어진다. 이렇게 형성된 테입 TIM(1)은 TIM(11)이 도포되지 않은 양면 테입(21)의 다른면에 의해 나중에 칩후면에 부착되게 된다.First, a semiconductor package using the tape TIM 1 of the present invention will be described. The tape TIM 1 used in the semiconductor package according to the preferred embodiment of the present invention is made by applying the TIM 11 on top of the double-sided tape 21, as shown in FIG. 3. The TIM 11 used at this time has a thermal conductivity of 2.78 to 3.18 w / m, k, a filling amount of 87 ± 5%, a maximum filling size of 70 µm, and is selected from the group consisting of silicon, zinc and aluminum, and the coating operation. Is achieved by screen printing with a tolerance of ± 5µm. The tape TIM 1 thus formed is later attached to the rear surface of the chip by the other side of the double-sided tape 21 to which the TIM 11 is not applied.

상술한 테입 TIM은 전체적으로 균일한 소정의 두께, 바람직하게는 50㎛를 갖기 때문에 종래에 젤형 TIM을 칩에 디스펜싱할 때 마다 디스펜싱하는 양을 조절해야했던 번거로움을 없앨 수 있다.Since the tape TIM described above has a uniform uniform thickness as a whole, preferably 50 μm, it is possible to eliminate the inconvenience of having to adjust the amount of dispensing each time a gel-type TIM is dispensed onto the chip.

또한, 테입 TIM을 사용하여 TIM을 칩에 부착하기 때문에 젤형태의 TIM이 어거 스크류에 잔존하여 경화되거나 경화된 유체에 의해 디스펜싱에 방해를 받는 등 종래에 발생했던 상술한 문제점이 발생하지 않는다.In addition, since the TIM is attached to the chip by using the tape TIM, the above-described problems, which occur in the past, do not occur such that the gel-type TIM remains on the auger screw and is interrupted by the hardened or hardened fluid.

따라서, 칩상의 TIM을 리드로 눌러 TIM의 두께를 조절하지 않아도 되므로 리드 두께를 소정의 두께를 고려하여 설계하지 않고 반도체 패키지를 형성할 수 있다.Therefore, since it is not necessary to adjust the thickness of the TIM by pressing the TIM on the chip with the lead, the semiconductor package can be formed without designing the lead thickness in consideration of a predetermined thickness.

또한, 상술한 테입 TIM 제작시 TIM을 테입에 도포할 때 허용오차가 ±5㎛인 스크린 인쇄 방식을 사용하기 때문에, 50㎛ 이하의 얇은 두께의 TIM을 요하는 경우에도 바람직하게 사용될 수 있다.In addition, since the screen printing method having a tolerance of ± 5 μm is used when the TIM is applied to the tape when the above-described tape TIM is manufactured, it may be preferably used even when a thin TIM of 50 μm or less is required.

다음으로, 상술한 테입 TIM을 사용하는 본 발명의 반도체 패키지를 제조하는 방법에 대해 살펴보도록 한다.Next, a method of manufacturing the semiconductor package of the present invention using the above-described tape TIM will be described.

도 2는 본 발명의 바람직한 실시예에 따른 반도체 패키지를 형성하는 장치의 전체 구조를 나타내며, 참조 부호 1은 테입 TIM, 참조 부호 2는 콜렛(collet), 참조 부호 3a는 칩후면 및 참조 부호 10은 이송암을 각각 나타낸다. 이송암(10) 중 콜렛(2)이 장착된 부분은 상하 운동이 가능하고, 이송암(10) 자체는 직선 왕복 운동이 가능하며, 이송암(10)이 고정된 부분 또한 직선 왕복 운동이 가능하여 콜렛 (2)이 원하는 위치로 이동될 수 있는 구성을 하고 있다.2 shows the overall structure of an apparatus for forming a semiconductor package according to a preferred embodiment of the present invention, wherein reference numeral 1 denotes a tape TIM, reference numeral 2 denotes a collet, reference numeral 3a denotes a chip back surface, and reference numeral 10 denotes Each transfer arm is shown. The portion where the collet 2 is mounted in the transfer arm 10 is capable of vertical movement, the transfer arm 10 itself is capable of linear reciprocating movement, and the portion where the transfer arm 10 is fixed is also capable of linear reciprocating movement. Thus, the collet 2 is configured to be moved to a desired position.

도 4 내지 도 7b는 도 1에 나타난 구성 요소와 패키지 제조 과정을 차례로 나타낸 도면들로써, 도 4는 테입 TIM(1)이 릴(reel) 형태로 장착된 상태, 도 5는 본 발명에 따른 펀칭기(20), 도 6a 및 도 6b는 펀칭된 테입 TIM(1)이 픽업되는 상태, 그리고 도 7a 및 도 7b는 테입 TIM(1)이 칩후면(3a)에 부착된 상태를 각각 나타낸다.4 to 7b are views sequentially showing the components and the package manufacturing process shown in Figure 1, Figure 4 is a tape TIM (1) is mounted in a reel (reel) state, Figure 5 is a punching machine ( 20), FIGS. 6A and 6B show the punched tape TIM 1 being picked up, and FIGS. 7A and 7B show the tape TIM 1 attached to the chip back surface 3a, respectively.

상술한 바와 같이 스크린 인쇄 방식에 의해 형성된 상술한 테입 TIM(1)은, 도 4에 도시된 바와 같이 릴형으로 감겨져 있어 지속적으로 공급될 수 있다. 감겨져 있던 테입 TIM(1)은, 도 5에 도시된 바와 같이 소정의 간격으로 펀칭기(20)로 공급되며, 펀칭기(20) 내부에 장착된 펀칭 수단(도시되지 않음)에 의해 자동으로 펀칭된다. 이 과정에서 펀칭된 테입 TIM(1)은 나중에 부착될 칩후면의 크기와 실질적으로 동일한 것이 바람직하다.As described above, the above-described tape TIM 1 formed by a screen printing method is wound in a reel shape as shown in FIG. 4 and can be continuously supplied. The wound tape TIM 1 is supplied to the punching machine 20 at predetermined intervals as shown in FIG. 5, and is automatically punched out by punching means (not shown) mounted inside the punching machine 20. The tape TIM 1 punched in this process is preferably substantially the same as the size of the chip back surface to be attached later.

다음으로, 펀칭된 테입 TIM(1)은, 도 6a 및 도 6b에 도시된 바와 같이 이송암(도 2의 10)의 한쪽 말단에 장착되어 있는 콜렛(2)에 의해 픽업(pick up)되게 된다. 픽업은 콜렛(2) 내부가 진공인 상태로 이루어진다.Next, the punched tape TIM 1 is picked up by a collet 2 mounted at one end of the transfer arm 10 of FIG. 2 as shown in FIGS. 6A and 6B. . The pickup is made in a state where the inside of the collet 2 is in a vacuum.

상술한 바와 같이 픽업된 테입 TIM(1)은, 도 2에 도시된 이송암(10)에 의해 펀칭기(20)의 뒤쪽에 배치된 컨베이너에 실장된 기판(5)으로 이송되며, 이렇게 이송된 테입 TIM(1)은, 도 7a에 도시된 상술한 기판(5)에 실장된 칩후면(3a)에 부착된다. 도 7b는 테입 TIM(1)이 칩후면 3a에 부착된 상태를 나타내는 단면도이며, 참조 부호 4는 언더필 재료, 참조 부호 6는 솔더 범프를 각각 나타낸다.The tape TIM 1 picked up as described above is transferred to the substrate 5 mounted on the conveyor disposed at the rear of the punching machine 20 by the transfer arm 10 shown in FIG. 2. The tape TIM 1 is attached to the chip back surface 3a mounted on the above-described substrate 5 shown in FIG. 7A. FIG. 7B is a cross-sectional view showing a state in which the tape TIM 1 is attached to the chip back surface 3a, 4 is an underfill material, and 6 is a solder bump, respectively.

도 7b에 도시된 테입 TIM에 접하게 상부에 리드를 덮어 기판(5)과 리드를 밀봉제를 사용하여 부착함으로써, 도 1에 도시된 최종 반도체 패키지를 얻게된다.By attaching the lid on top of the tape TIM shown in FIG. 7B and attaching the substrate 5 and the lead with a sealant, the final semiconductor package shown in FIG. 1 is obtained.

본 발명을 바람직한 실시예를 참조로 설명하였으나, 본 발명의 취지 내에서 다양한 변형 실시예가 가능하다.While the invention has been described with reference to preferred embodiments, various modifications are possible within the spirit of the invention.

본 발명에 따른 반도체 패키지에 사용된 테입 TIM은 최적의 두께로 일정하게 (50㎛) 형성되기 때문에 패키지의 최적 열방출을 용이하게 이룰 수 있다. 또한 테입 TIM을 사용하면 펌프 클리닝 및 노즐 교환 등을 할 필요가 없어진다. 아울러, 허용오차가 ±5㎛인 스크린 인쇄 방식에 의해 테입 TIM이 형성되기 때문에, 50㎛ 이하의 TIM의 두께를 요하는 경우에도 바람직하게 사용될 수 있다.The tape TIM used in the semiconductor package according to the present invention is formed at a constant (50 μm) at an optimum thickness, thereby easily achieving optimal heat dissipation of the package. Tape TIM also eliminates the need for pump cleaning and nozzle replacement. In addition, since the tape TIM is formed by a screen printing method with a tolerance of ± 5 μm, it can be preferably used even when a thickness of a TIM of 50 μm or less is required.

Claims (3)

기판상에 플립칩 본딩된 칩상에 리드(lid)를 부착하여 형성되는 반도체 패키지에 있어서, 상기 반도체 패키지는,A semiconductor package formed by attaching a lid onto a chip bonded to a flip chip on a substrate, the semiconductor package comprising: 열전도성이 2.78~3.18w/m,k, 충전양은 87±5%, 최대 충전 두께가 70㎛의 기본 특성을 가지며, 실리콘, 아연 및 알루미늄으로 이루어진 그룹으로부터 선택되는 TIM(thermal interface material)을 허용오차가 ±5㎛인 스크린 인쇄 방식으로 양면 테입에 도포하여 형성된 테입 TIM을 기판에 부착된 칩후면에 도포하고, 상기 리드를 상기 테입 TIM과 접하고 상기 기판과 부착하도록 덮어서 밀봉제로 상기 기판과 상기 리드를 밀봉함으로써 형성되는 것을 특징으로 하는 테입 TIM을 사용하는 반도체 패키지.The thermal conductivity is 2.78 ~ 3.18w / m, k, the filling amount is 87 ± 5%, the maximum filling thickness is the basic characteristic of 70㎛, and it allows TIM (thermal interface material) selected from the group consisting of silicon, zinc and aluminum. A tape TIM formed by applying to a double-sided tape by a screen printing method having an error of ± 5 μm is applied to the back surface of the chip attached to the substrate, and the lid is covered to contact the tape TIM and attached to the substrate, and the substrate and the lid are sealed with a sealant The semiconductor package using a tape TIM, characterized in that formed by sealing. TIM을 준비하는 단계,Preparing the TIM, 상기 TIM을 양면 테입의 한쪽면에 소정의 두께로 스크린 인쇄하여 테입 TIM을 형성하는 단계,Screen printing the TIM on one side of the double-sided tape to a predetermined thickness to form a tape TIM; 상기 테입 TIM을 부착될 칩후면 크기에 대응되게 펀칭하는 단계,Punching the tape TIM corresponding to the size of the chip back surface to be attached; 펀칭된 상기 테입 TIM을 이송하여 기판에 플립칩 본딩된 칩후면에 부착하는 단계, 및Transferring the punched tape TIMs and attaching the chip backs to flip chip bonded chips on a substrate; and 상기 칩이 실장된 부분을 리드(lid)로 덮어 밀봉하는 단계를 포함하며,Covering the chip-mounted part with a lid to seal the lid; 상기 리드는 상기 칩후면의 테입 TIM의 상부면과 상기 칩 외곽의 기판 상부면에 부착되는 것을 특징으로 하는 패키지 제조 방법.The lid is attached to the upper surface of the tape TIM of the chip back and the upper surface of the substrate outside the chip package manufacturing method. 제 2항에 있어서, 상기 테입 TIM의 두께가 50㎛로 균일하게 형성되는 것을 특징으로 하는 패키지 제조 방법.The method of claim 2, wherein the tape TIM is uniformly formed in a thickness of 50 μm.
KR1020010039726A 2001-07-04 2001-07-04 Semiconductor package using tape thermal interface material and the method of manufacturing for the same KR20030003874A (en)

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