KR20030003092A - Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device - Google Patents

Abstract

PURPOSE: To decrease the probability that memory control by data transfer operation competes with memory control from outside. CONSTITUTION: A semiconductor memory device 190 has memory blocks 130, 131 of fast write operation, a memory block 150 of slow write operation and a memory control means (switching circuits 110, 120, 140, a WSM 160 and a control bus and a data bus between them) that permits data transfer operation between one of the memory blocks 130, 131 and the memory block 150, and performs the memory operations of read/write/erase operation or the like regarding the another of the memory blocks 130, 131 based on an access operation from outside. Thus, the memory control means permits access operation for the memory blocks 130, 131 of two divided small individual storage areas respectively and independently.

Description

Method of setting access period of semiconductor memory device, information device, and semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE, INFORMATION APPARATUS, AND METHOD FOR DETERMINING ACCESS PERIOD FOR SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor memory device in which high speed data transfer is performed. The present invention also relates to an information apparatus using the semiconductor memory device and a method for setting an access period of the semiconductor memory device.

Semiconductor memory devices such as EEPROM (flash memory) require longer time to write data than static random access memory (SRAM) and dynamic random access memory (DRAM). Conventionally, in order to speed up the writing speed of such a semiconductor memory device, data is first accumulated in a buffer area composed of other types of memory elements such as SRAM embedded in the semiconductor memory device, and then the accumulated data is stored in the semiconductor memory device ( EEPROM, etc.)

This method has the following drawbacks. For example, the buffer area is used only for the buffering function, and there is a big limitation when the buffer area is used for other purposes. In general, since data written to the buffer area is previously developed in a separate memory, the use efficiency of the memory is low.

In order to solve this drawback, the inventors of the present invention previously disclosed in Japanese Laid-Open Patent Publication No. 2000-176182, a non-volatile memory such as a memory capable of high-speed write and a non-volatile memory such as an EEPROM and a data transfer unit can be written. Disclosed is a semiconductor memory device capable of further improving the write speed and the memory usage efficiency by being provided between semiconductor memory devices.

According to such a device, data can be transferred from the RAM used for a normal task to the EEPROM or the like, whereby the write data is developed in advance in another area or the EEPROM or the like is separately controlled to write the data to the buffer. It is not necessary to be. In order to use the built-in high-speed writeable memory in a system task or the like, it is essential to simultaneously execute an external memory operation and a data transfer operation. For this purpose, it is preferable that a dual port memory is used as a memory capable of high-speed writing.

However, the dual port memory has problems such as large increase in cell area and deterioration of characteristics of the memory device. In addition, as the memory capacity increases, disadvantages such as an increase in cost, an area occupied by the device, and a decrease in performance are caused.

The term " external memory operation " as used herein denotes that the memory is operated by instructions issued from the outside of the memory such that data is input into the memory issued from the outside of the memory or outputted to the outside of the memory.

As used herein, the term "externally" in the terms "reading from the outside", "written from the outside", "indicated from the outside", etc., means that data or instructions are transmitted from the outside of the memory or transferred out of the memory. This operation is preferably controlled by commands issued from the outside.

Fig. 10 is a block diagram showing an example of the configuration of main parts of a conventional semiconductor memory device. The semiconductor memory device has a memory operation of a conventional first memory composed of a memory element having a high writing speed and a conventional second memory composed of a memory element having a slow writing speed, and transfers data (contents of the memory) between the memory. A data transfer operation is performed. The semiconductor memory device will be described with reference to FIG. In the data transfer operation, data is mainly transferred from a memory having a high write speed to a memory having a slow write speed. In addition, reverse data transmission is also useful because it can reduce the burden on an external control device or the like. There is no substantial difference in the data transfer operation between the two directions. Here, only data transfer from a memory with a high write speed to a memory with a slow write speed will be described.

As shown in Fig. 10, the semiconductor memory device 490 includes: a control bus 401 and a data bus 402 connected from the outside; A switching circuit 410 (MUX0) for transmitting information to each unit according to an external control instruction; A write state machine (WSM) 460 for controlling data transfer operations and the like; Memory 430 (MEMl) such as an SRAM composed of a memory device capable of high-speed writing; A switching circuit 420 (MUX1) for switching between control of the memory 430 indicated by the WSM 460 and control of the memory 430 indicated from the outside; A memory 450 (MEM2) such as a flash memory composed of a rewritable memory element; And a switching circuit 440 (MUX2) for switching between the control of the memory 450 indicated by the WSM 460 and the control of the memory 450 indicated from the outside.

The control information is input from the outside to the semiconductor memory device 490 via the control bus 401 and the data bus 402 including the address bus. If the control information is for the memory 430, the switching circuit 410 is used to transfer the control information to the switching circuit 420 via the control bus 411 and the data input / output bus 412. If the control information is for the memory 450, the control information is transferred to the switching circuit 4410 via the control bus 413 and the data input / output bus 414. In addition, if the control information relates to a data transmission operation, the control information is transmitted to the WSM 460 via the control bus 415 and the data input / output bus 416.

However, the write operation to the memory 450 requires the WSM 460 when complicated control such as writing to the EEPROM is required. In this case, the switching circuit 410 gives a rewrite instruction to the WSM 460 via the control bus 415 and the data bus 416 as in the data transmission operation.

Next, the specific operation of the semiconductor memory device 490 will be described.

When data read from the memory 430 is executed from the outside, the switching circuit 410 is instructed through the control bus 401 to read data from the memory 430. When the control information received through the control bus 401 indicates a read operation from the memory 430, the switching circuit 410 gives a read instruction to the switching circuit 420 through the control bus 411, and switches. The circuit 420 gives a read instruction to the memory 430 through the control bus 421.

When the memory 430 is instructed through the control bus 421 to perform a read operation, the memory 430 reads out data stored in the target memory device and switches the data through the data bus 422. Output at 420. The switching circuit 420 receives data from the data bus 422 and transfers the data to the switching circuit 410 through the data bus 412.

The switching circuit 410 outputs the data received from the data bus 412 to the outside of the storage device 490 via the data bus 402. The above-described series of operations enable reading from the memory 430 from the outside.

Next, the case where data is written to the memory 430 from the outside will be described. The write instruction to the memory 430 is transmitted to the switching circuit 410 through the control bus 401. The data to be written is input to the switching circuit 410 via the data bus 402.

If the control information received through the control bus 401 is a write operation to the memory 430, the switching circuit 410 gives a write instruction to the switching circuit 420 via the control bus 411 to write the data to be written. Input to the switching circuit 420 via the data bus 412.

The switching circuit 420 gives a write instruction to the memory 430 through the control bus 421 and inputs the data to be written to the memory 430 through the data bus 422.

When the memory 430 is instructed via the control bus 421 to perform a write operation, the data input through the data bus 422 is written to the target memory element. By the series of operations described above, the write operation to the memory 430 from the outside can be realized.

However, since the operation of reading data from the memory 450 from the outside is similar to that of reading data from the memory 430 from the outside, the description thereof is omitted here.

Next, the case of writing data to the memory 450 from the outside will be described. If the memory elements constituting the memory 450 enable a simple write operation, this write operation can be realized by a control operation similar to the write operation to the memory 430. However, if a memory requiring complex control is used, for example, EEPROM, the WSM 460 is needed to control the write operation.

In this case, a write control instruction is given to the memory 450 from the outside via the control bus 401. When data to be written is designated by the data bus 402, the switching circuit 410 instructs the WSM 460 via the control bus 415 and the data bus 416 to perform a write control operation.

The write control instruction is transmitted to the switching circuit 440 via the control bus 463, and the data to be written is input to the memory 450 or is written directly from the switching circuit 410 through the data bus 414. Data is input via data bus 416, then WSM 460, and then data bus 464.

The switching circuit 440 controls the write operation to the memory 450 using the control bus 441, and inputs the data to be written to the memory 450 through the data bus 442.

When the WSM 460 is used, even if the memory 450 requires a complicated control operation such as an EEPROM, the write operation to the memory 450 is enabled by the above-described series of operations.

Next, a data transfer operation from the memory 430 to the memory 450 will be described. The data transfer operation is mainly necessary when data is transferred from a memory having a high write speed to a memory having a slow write speed. This case will be described. However, the data transfer function from the memory having a slow writing speed to the memory having a high writing speed is useful for reducing the burden on the external control apparatus and can be realized by the prior art. The control method thereof is similar to the case where data is transferred from a memory having a high writing speed to a memory having a slow writing speed, and thus description thereof is omitted here.

When a data transmission operation instruction (control instruction by control instruction) is externally given to the switching circuit 410 via the control bus 401 and the data bus 402, the switching circuit 410 sends the control bus to the WSM 460. Through 415 and data bus 416, information necessary for data transmission, such as reception of a data transmission operation instruction, an area in which data is transmitted, is transmitted.

When the WSM 460 is instructed via the control bus 415 and the data bus 416 to perform a data transfer operation from the memory 430 to the memory 450, the WSM 460 is transferred to the memory 430. Reading of data is instructed to the switching circuit 420 via the control bus 461.

The switching circuit 420 reads data from the memory 430 designated by the control bus 461 through the control bus 421 and the data bus 422, and reads the read data through the data bus 462. Send to 460.

The WSM 460 which receives data transmitted from the switching circuit 420 instructs the switching circuit 440 to write data to the memory 450 using the control bus 463.

The data to be written is transferred to the switching circuit 440 via the data bus 464. The switching circuit 440 uses the control bus 441 and the data bus 442 to perform a write operation to the memory 450 which is an instruction given through the control bus 463 and the data bus 464.

When a plurality of pieces of data are transmitted, the WSM 460 completes the data transfer operation by executing the above data transfer operation on all data to be targeted.

Here, when the read operation from the memory 430 designated by the WSM 460 conflicts with the external control command issued to the memory 430, the switching circuit 420 determines the contention of the control command information and determines the determination signal. 425 is used to inform the WSM 460 of the contention of control command information.

If the semiconductor memory device 490 is designated to allow access to the memory 430 during the data transfer operation, there is a possibility that external control information for the memory 430 and control information from the WSM 460 are contended. When such contention occurs, the operation of the switching circuit 420 is changed in accordance with the specifications of the semiconductor memory device 490. If the external memory operation is designated to take precedence over the data transfer operation, the switching circuit 420 controls the memory 430 using the control bus 421 and the data bus 422, such as the data bus 412 in the case of a read operation. The read data is transmitted to the switching circuit 410 through.

Conversely, if the data transfer operation takes precedence over the external control command, when contention occurs in the control information, the switching circuit 420 uses the control bus 421 and the data bus 422 to transfer the data (designated memory). Access operation 430), and the cancellation of the external memory operation is transmitted to the WSM 460 using the determination signal 425. In this situation, since external access may not be executed normally, a means for confirming from the outside whether or not control has been completed normally is necessary. In this case, the confirmation operation instruction is given to the WSM 460 from the outside via the control bus 415 and the data bus 416. The WSM 460 transmits the contents indicating the result of the determination signal 425 to the switching circuit 410 by using the control bus 415 and the data bus 416, and the contents are transmitted through the data bus 402. It is output from the switching circuit 410 to the outside of the memory device 490.

Alternatively, other means for confirming completion of the memory operation from the outside may be realized as follows. The determination signal 425 is not transmitted to the WSM 460, but instead the determination signal 425 is transmitted to the switching circuit 410, only the switching circuit 410 to confirm the completion of the memory operation from the outside Used.

The control command for the memory 450 may be designated such that the external memory operation and the data transfer operation from the WSM 460 are executed independently. Since this operation is the same as the control of the memory 430, the description thereof is omitted here.

As described above, in the prior art, the data transfer operation and the external memory operation can be executed independently. However, when the data transfer operation takes precedence over the external memory operation, the external memory operation becomes more complicated than the general memory. When the external memory operation takes precedence over the data transfer operation, it affects the data transfer operation and the time required for the data transfer operation is extended. In particular, when the external memory operation is complicated or when the external memory operation takes a long time, the probability that the external memory operation is contended with the data transfer operation is greatly increased. In such a situation, the data transfer operation is greatly affected.

In a conventional semiconductor memory device having a function of transferring data between a memory having a high writing speed and a memory having a slow writing speed, a memory having a high writing speed can be used for a working memory or the like of a system. In addition, during the data transfer operation, once the next data transferred to the memory having a slow writing speed is stored in a separate area of the memory having a high writing speed, an improvement in the performance of the data transfer can be expected.

In SRAMs and DRAMs, which are representative of high write speed memories, reads and writes are executed at high speed in almost equal cycles. The read and write can be controlled regardless of the state of the device except in special circumstances. In this case, read or write verification is not performed. If read or write is likely to fail due to the limitation of the state of the device, it is necessary to output the success or failure of the control to the outside, for example, by an external control device to receive and display the success signal.

To avoid this complexity, a memory with a high write speed often takes precedence over an external memory operation, whether or not a data transfer operation is being executed.

However, interrupting the data transfer operation during the external memory operation may cause a decrease in the data transfer rate. In particular, when the external memory operation is frequent or when one control operation (memory operation) takes a long time, the decrease in the data transfer rate becomes remarkable.

To avoid this, dual port memory can be used as the memory at the data transfer end. However, the dual port memory cannot avoid an increase in cell area and the like, and is directly linked to an increase in cost or an area occupied by an element.

It is an object of the present invention to solve the above problems.

The semiconductor memory device of the present invention, the first and second memory unit including a plurality of memory elements; And a memory controller for enabling a data transfer operation between the first and second storage units according to an external control command, and for enabling a memory operation for at least one of the first and second storage units. At least one of the first and second storage units may include a plurality of small storage areas, and the memory control unit may perform an access operation independently and simultaneously for each of the plurality of small storage areas. This achieves the above object. As used herein, access operations include read operations, write operations, verification operations, and the like, as well as write and read operations to memory in data transfer.

In one embodiment of the present invention, the memory controller is configured such that one small storage area is used for a data transfer operation while another small storage area is used for a memory operation, and / or the other small storage area is used for another memory operation. The plurality of small storage areas are controlled so that one small storage area is used for a memory operation while being used separately, whereby the data transfer operation and the memory operation and / or memory operations are simultaneously executed.

In one embodiment of the present invention, the first and second storage portions include different memory elements, and one of the first and second storage portions having a high speed writing portion includes a plurality of small storage regions.

In one embodiment of the present invention, the memory control section includes: an access operation section for limiting an access period for at least one of the first and second storage sections to a minimum required for each access operation; and access restricted by the access operation section. And a third storage section for storing predetermined memory data within the period.

According to another aspect of the present invention, a semiconductor memory device includes: first and second memory units including a plurality of memory elements; And a memory controller for enabling a data transfer operation between the first and second storage units according to an external control command and enabling a memory operation for at least one of the first and second storage units. The memory control section has an access operation section for limiting an access period for at least one of the first and second storage sections to a minimum required for each access operation. Thereby, the said objective is achieved.

In one embodiment of the present invention, the apparatus further comprises: an access completion signal generator for generating an access completion signal upon completion of the access, wherein the access operation receives the access completion signal and ends the access period initiated by the access permission signal, Thereby, the said objective is achieved.

In one embodiment of the present invention, the memory control section has a third storage section for storing predetermined memory data within an access period limited by the access operation section, and the memory control section further comprises the first and second memories. When data is read from at least one of the parts, a data read operation is performed within the access period limited by the access operation unit, and the read data is stored in the third storage unit. Thus, for example, data read by the read operation required for the high speed write speed memory is latched, so that the operation of the high speed write speed memory can be efficiently performed.

In one embodiment of the present invention, the memory elements included in the first and second storage units have different forms, and the memory control unit reads data from one of the first and second storage units having a fast writing speed.

In one embodiment of the present invention, the memory control unit writes data to at least one of the first and second storage units within an access period limited by the access operation.

In one embodiment of the present invention, the semiconductor memory device is integrated on a single semiconductor chip.

According to another aspect of the present invention, there is provided an information device that uses the semiconductor memory device to perform at least one of a data transfer operation and a memory operation, or performs at least two memory operations within an access period.

According to another aspect of the present invention, a method for setting an access period of a semiconductor memory device is provided. Upon completion of the access, an access complete signal is generated, and upon receipt of the access complete signal, the access initiated by the access grant signal ends.

Hereinafter, the operation of the present invention will be described. One of the first and second memory sections having a high writing speed is constituted of a plurality of small storage areas in which memory operations and data transfer operations are independently executed. The present invention includes a memory control section that enables memory operation simultaneously for an area in which another area is performed separately from an external access operation while one area is used for data transmission. Therefore, the memory operation by the control command from the outside and the data transfer operation by the other control command can be executed simultaneously. In addition, it is possible to execute each memory operation simultaneously by a separate control command from the outside in parallel.

In addition, by limiting the access period to the period during which the memory array is actually activated, the memory control unit can efficiently perform the memory operation, the data transfer operation, or the separate memory operation in the minimum limited access period required for each access operation. . Thus, for example, the high-speed write memory can be operated efficiently by latching the data read from the memory having the high write speed in accordance with the read operation.

In addition, a portion having a plurality of regions in which the fast write region can be operated independently and a portion for limiting the period so that the memory array in the fast write memory portion is activated are required to the minimum, and at the same time, the access operation is further enhanced. It can be performed efficiently.

In any of the above cases, it is possible to reduce the probability of contention between the external memory operation and the data transmission operation, thereby suppressing the decrease in the speed of the data transmission operation or giving priority to the data transmission operation while preferentially processing the external memory operation. As a result, the probability that the memory operation from the outside is disturbed can be reduced.

Accordingly, the present invention provides a semiconductor memory device capable of reducing the possibility of contention between an external memory operation and a data transfer operation, an information device using the semiconductor memory device, and a method for setting an access period for the semiconductor memory device. .

Many advantages of the present invention will be apparent to those skilled in the art from the following detailed description with reference to the accompanying drawings.

Fig. 1 is a block diagram showing an example of the configuration of main parts of a semiconductor memory device according to the first embodiment of the present invention.

Fig. 2 is a block diagram showing an example of the configuration of main parts of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration example of the control circuit of FIG.

4 is a signal waveform diagram of an input terminal and an output terminal of the control circuit of FIG.

FIG. 5 is a circuit diagram showing another specific configuration example different from the control circuit of FIG.

6 is a signal waveform diagram of an input terminal and an output terminal of the control circuit of FIG.

7A and 7B are timing charts showing the state of the internal activation signal when the disable signal CE # and the internal transmission signal overlap.

Fig. 7C is a timing chart showing the state of the internal activation signal when the second memory operation is executed a plurality of times while the first memory operation is performed.

Fig. 8 is a block diagram showing an example of the configuration of main parts of a semiconductor memory device according to the third embodiment of the present invention.

9 is a block diagram showing the basic configuration of an information apparatus to which the semiconductor memory device of the present invention is applied.

Fig. 10 is a block diagram showing an example of the configuration of main parts of a conventional semiconductor memory device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the accompanying drawings.

(Example 1)

Fig. 1 is a block diagram showing an example of the configuration of main parts of a semiconductor memory device according to the first embodiment of the present invention. 1 shows only a portion of the semiconductor memory device of the present invention necessary for explaining the present invention. The configuration of the semiconductor memory device 190 shown in FIG. 1 is an example of the configuration of the semiconductor memory device of the present invention. For example, at least a part of the data bus may be divided into a data input bus and a data output bus, the contents of the data passing through the data bus may be used as a control signal, and the data may be written to a write state machine (hereinafter referred to as WSM) during the transfer operation. May be transmitted without the need for a), and other configurations are possible. Embodiment 1 of the present invention is not limited to the configuration of FIG. Among the specific operations of the semiconductor memory device 190, operations different from those described in the conventional semiconductor memory device 490 are mainly described.

In Fig. 1, the semiconductor memory device 190 according to the present invention includes the memory blocks 130 and 131 as the first memory section having a fast writing speed, the memory block 150 as the second memory section having a slow writing speed, and a memory controller (switching circuit). 110, 120, 140, WSM 160, and control buses and data buses therebetween. The memory controller may execute a data transfer operation between one of the memory blocks 130 and 131 and the memory block 150 based on an external access operation. In addition, the memory controller performs memory operations such as read, write, and erase operations on the other of the memory blocks 130 and 131. Here, the memory control unit simultaneously uses the memory block 130 for the data transfer operation (or the data read operation) and the memory block 131 for the memory operation (ie, the read or write operation) to simultaneously perform the data transfer operation and the memory operation. You can run

Hereinafter, the semiconductor memory device 190 of the present invention will be described in more detail.

When the switching circuit 120 is instructed by the switching circuit 110 through the control bus 111 to perform an access operation from the outside to the memory (memory blocks 130 and 131) having a high writing speed, the control bus 111 Based on the address signal of the address bus included in the switch, the switching circuit 120 determines whether or not the memory element designated by the access operation is included in the memory block 130 or the memory block 131. If the access operation is for the memory block 130, using the control bus 121 and the data bus 122, the contents of the access operation are executed for the memory element designated by the access operation. If the access operation is for the memory block 131, using the control bus 123 and the data bus 124, the contents of the control command are executed for the memory element designated by the access operation.

If the designated access operation is a read operation (memory operation), read data is transferred from the switching circuit 120 to the switching circuit 110 via the data bus 112, so that the switching circuit 110 via the data bus 102. The read data is output to the outside. Therefore, the access operation to the memory (memory blocks 130 and 131) with a high writing speed can be executed from the outside.

Next, during the data transfer operation, if the switching circuit 120 is instructed by the control signal 161 to perform an access operation to the memory having a high writing speed, it is based on the address signal of the address bus included in the control bus 161. Thus, the switching circuit 120 determines whether the memory element designated by the access operation is included in the memory block 130 or the memory block 131.

If the access operation is for the memory block 130, using the control bus 121 and the data bus 122, the specified operation is executed for the memory element designated by the access operation. If the access operation is for the memory block 131, using the control bus 123 and the data bus 124, the specified operation is executed for the memory element designated by the access operation.

If the designated access operation is a read operation, read data is transferred from the switching circuit 120 to the WSM 160 via the data bus 162. Therefore, the access operation to the memory with a high writing speed can be executed during the data transfer operation.

The memory blocks 130 and 131 may operate independently. Thus, while any of the memories (e.g., memory block 130) is being accessed by the WSM 160 during a data transfer operation, the other memory (e.g., memory block 131) is a control bus. An external access operation can be received using the 101 and data bus 102.

If there is contention between access operations (data transfer operation, read operation, etc.) to any of the memory blocks 130 and 131, the access operation may conflict with the access operation from the conventional semiconductor memory device 490 to the memory 430. It can't run at the same time as usual. However, the switching circuit 120 uses the control bus 121 and the data bus 122 (memory block 130), or the control bus 123 and the data bus 124 (memory block 131). The WSM 160 is executed by executing a control command having a high priority (for example, a data transfer operation or a memory operation) and using a determination signal 125 that may not normally complete the operation having a low priority. ).

As described above, in the semiconductor memory device 190 of the first embodiment, for example, an external access operation (memory operation) is performed to the memory block 131 while the memory block 130 is used for the data transfer operation. Thus, for example, a memory having a high writing speed without affecting the data transfer operation can be used as the working memory. Further, by writing the next data transferred to the memory having a high write speed together with the data transfer operation, the semiconductor memory device can easily start the next data transfer operation immediately after the previous data transfer operation is completed.

As described above, in a semiconductor memory device having a function of transferring data between two memory areas (memory blocks 130 and 131 and memory block 150), a memory having a high writing speed in addition to the general use of the device (memory) More efficient access operation for the blocks 130 and 131 and more efficient data storage for the memory (memory block 150) with a slower writing speed can be realized.

In the first embodiment, the first storage section is a memory having a high writing speed including a plurality of independently operable regions (memory blocks 130 and 131). However, the second storage unit, i.e., the memory having a slow writing speed (memory block 150) may have a similar configuration. According to this configuration, at least one of an external memory operation to the memory having a slow writing speed, that is, reading and writing, can be executed without affecting the data transfer operation.

In the first embodiment, the first storage section having a high writing speed is divided into two small memory areas, that is, memory blocks 130 and 131 that can be operated independently, but may be divided into three or more memory blocks.

(Example 2)

Fig. 2 is a block diagram showing an example of the configuration of main parts of the semiconductor memory device according to the second embodiment of the present invention. 2 shows only a portion of the semiconductor memory device of the present invention necessary for explaining the present invention. The configuration of the semiconductor memory device 290 shown in Fig. 2 is an example of the configuration of the semiconductor memory device of the present invention. Embodiment 2 of the present invention is not limited to the configuration of FIG. Among the specific operations of the semiconductor memory device 290, operations different from those described in the conventional semiconductor memory device 490 will be mainly described.

In Fig. 2, the semiconductor memory device 290 of the present invention includes a memory block 230 as a first storage unit with a high write speed, a memory block 250 as a second memory unit with a slow write speed, and a memory controller. . The memory controller may execute a data transfer operation between the memory block 230 and the memory block 250 based on an external control command. In addition, the memory controller performs a memory operation such as a read, write, and erase operation on the memory block 230.

The memory controller includes switching circuits 210, 220, 240, WSM 260, and control and data buses therebetween. The memory controller controls the timing of the control circuit 270 as the time setting unit for controlling the timing of the delay and the like, the data latch circuit 271 as the third storage unit between the switching circuit 220 and the switching circuit 210 and the delay. It further includes a control circuit 272 as a time setting section to control, and a data latch circuit 273 as a third storage section between the switching circuit 220 and the WSM 260. When a memory control addition is instructed to perform an access operation to the memory block 230, the access operation ends internally after an arbitrary period of time (access period limited to the minimum required for each access operation) has elapsed. Even if the next access operation follows continuously, in the present invention, the next access operation can be executed. To this end, peripheral circuitry is used to allow the semiconductor memory device 290 to behave in such a way that the next access operation is pseudologically continued to the previous access operation.

Hereinafter, specific examples of the control circuit 270 or 272 which are unique features of the present invention will be described.

FIG. 3 is a circuit diagram showing a specific configuration example of the control circuit 270 or 272 of FIG. FIG. 4 is a diagram showing signal waveforms at input and output terminals of the control circuit of FIG. As shown in Figs. 3 and 4, the control circuit 270 or 272 is synchronized with the fall of the disable signal CE # (i.e., the memory is enabled at the low level) from the external or WSM 260, Outputs an internal activation signal maintained at a high level for a predetermined period of time. The predetermined period (delay time: minimum value of the required access period) during which the internal activation signal is maintained at a high level is determined by the delay of the transistor included in the circuit. Therefore, the delay of the transistor must be adjusted so that a sufficient period (access period is limited to the minimum required for each access operation) to complete the access operation to the memory. However, the external disable signal CE # is transmitted from the switching circuit 210 to the control circuit 270, and the disable signal CE # from the WSM 260 is transmitted from the WSM 260 to the control circuit 272.

However, another example of the control circuit 270 or 272 of FIG. 2 will be described with reference to FIGS. 5 and 6. Here, the access period is set as follows. When the access is completed, an access complete signal is generated. When the access completion signal is received, the access period started by the access permission signal ends. In this case, the access completion signal generation unit may be provided to the memory block 230 (at least one of the first storage unit and the second storage unit) or the switching circuit 220. The access completion signal may be generated by monitoring the activation state of the memory block 230.

FIG. 5 is a circuit diagram showing another specific configuration example different from that of the control circuit of FIG. FIG. 6 is a diagram showing signal waveforms at input and output terminals of the control circuit of FIG. The control circuit 270 or 272 having the circuit shown in Fig. 5 is called the control circuit 270A or 272A. As shown in Figs. 5 and 6, the control circuit 270A or 272A is configured to disable signal CE # (i.e., memory is enabled at low level) as an access permission signal from an external or WSM 260. An internal activation signal is output in synchronization with the rising of the standby signal of the internal memory which is raised in synchronism (high level) and in synchronism with the falling of the disable signal CE #. When the internal enable signal becomes high level, access to the internal memory is started, and at the same time the standby signal is lowered. When the access is complete, the standby signal is raised. However, the external disable signal CE # is transmitted from the switching circuit 210 to the control circuit 270, and the disable signal CE # from the WSM 260 is transmitted from the WSM 260 to the control circuit 272. The standby signal of the internal memory is transmitted from the memory block 230 to the switching circuit 220 and then to any control circuits 270A and 272A. The standby signal is used as an access complete signal.

In the control circuit 270 or 272 of Fig. 3, it is necessary to use a delay to secure a period in which the access is surely completed. Therefore, in order to secure sufficient margin, it is necessary to activate a sufficient period (access period limited to the minimum required for each access operation) with respect to the access time. However, in the control circuit 270A or 272A of Fig. 5, the period in which the internal memory is activated (an access period limited to the minimum value required for each access operation) can be further reduced to a minimum value, thereby further improving the efficiency of data transmission. Can be improved. However, unlike the circuit of Fig. 3, the delay circuit shown in Fig. 5 at the rear end side of the inverted circuit generates the time required for the flip-flop (two NOR gate circuits at the right end of the circuit of Fig. 5). Is enough.

Hereinafter, the semiconductor memory device 290 of the present invention will be described in more detail.

When a data read operation from the memory block 230 is executed from the outside, the switching circuit 210 is instructed to read data from the memory block 230 through the control bus 201.

If the designated data read operation is for the memory block 230, the switching circuit 210 instructs the control circuit 270 through the control bus 211 to perform a read operation.

The control circuit 270 instructs the switching circuit 220 to perform a read operation from the memory block 230 through the control bus 282, and outputs the data latch control signal 281 to the data latch circuit 271. do.

When the switching circuit 220 is instructed to perform a read operation from the control bus 282 by the control circuit 270, the switching circuit 220 controls the data read operation to the memory block 230. In this case, the read data from the memory block 230 is received through the data bus 222, and the read data is transmitted to the data latch circuit 271 through the data bus 283.

The data latch circuit 271 is controlled using the data latch signal 281 generated by the control circuit 270. When the read operation is performed from the outside, the read data is transmitted to the switching circuit 210 via the data bus 212. After a predetermined period has elapsed since the start of the read operation, the data transferred from the data bus 283 is latched. The latched data is transmitted to the switching circuit 210 via the data bus 212 at least until the external read operation is completed. The switching circuit 210 outputs the received data to the outside via the data bus 202.

The series of operations described above enable data read operations from memory block 230. In this read operation, the period in which data is actually read after activation of the memory block 230 is a predetermined period (an access period limited to the minimum required for each access operation) from the start of the read. After this period has elapsed, the read operation from the memory block 230 ends, and the control bus 221 and the data bus 222 are released.

However, after the memory block 230 is deactivated, the data latch circuit 271 latches the read data, and the switching circuit 210 receives the read data while the external read is continued and outputs data to the outside. Therefore, while the semiconductor memory device 290 is instructed from the outside to perform a read operation, the external memory is always in a state where data read is performed.

By this operation, even when the storage device 290 is instructed from the outside to perform a read control operation for a long time, the period for activating the memory block 230 with a high read speed can be actually reduced and limited. Thus, the probability of contention occurring between the access operation from the WSM 260 and the data transfer operation can be reduced.

Hereinafter, the effects of the present invention for reducing the normal contention possibility between the memory operation including the read operation and the data transfer operation, or the normal contention possibility between the memory operation will be described.

As shown in Figs. 7A and 7B, when the disable signal CE # (memory operation) and the internal transfer signal (data transfer operation) are contended, or as shown in Fig. 7C, the memory operation (external operation and WSM) is performed. When another memory operation is executed a plurality of times while one of the operations is performed, even if the disable signal CE # is set to a low level period (high level period of the enable signal CE), for example, an internal activation signal for the disable signal CE #. And an internal activation signal for the internal transmission signal (similar to the disable signal CE #, which is at a LOW level during the period requiring access) to be used for successively activating the memory block 230 in time series. An access operation may be performed on block 230. In this case, conventionally, the internal activation signal cannot be activated (high level) during the period in which the disable signal CE # and the internal transmission signal are contended. In the present invention, even when the disable signal CE # and the internal transmission signal are contended as described above, the internal activation signal can be activated (high level), thereby reducing the contention probability.

In this case, the external disable signal CE # is transmitted from the switching circuit 210 to the control circuit 270, and the disable signal CE # from the WSM 260 is transmitted from the WSM 260 to the control circuit 272. . In addition, the internal transmission signal is transmitted from the WSM 260 to the switching circuit 220 through the control circuit 272. The internal activation signal is raised by any of the disable signal CE # and the internal transmission signal, and after a predetermined period has elapsed (or by the edge of the standby signal in Fig. 6 from the memory block 230), the internal activation signal is raised. By lowering, the access period is limited to the minimum required for each access operation. Hereinafter, each of FIGS. 7A to 7C will be described in detail.

As shown in Fig. 7A, when the disable signal CE # precedes the internal transmission signal but overlaps, the internal activation signal is raised for a predetermined period in synchronization with the fall (memory operation) of the disable signal CE #. The internal activation signal is raised in synchronization with the fall of the internal transmission signal (data transmission operation). If the period T1, which is the time gap between the disable signal CE # and the internal transmission signal, is longer than the predetermined activation period T2 of the internal activation signal, the internal activation signal for the disable signal CE #, and the internal activation signal for the internal transmission signal are The memory block 230 may be used to continuously activate time series. In this case, assuming that the high-level period T2 of the internal activation signal is about 1/5 of the low level period of the disable signal CE # and the internal transmission signal, another disable signal CE # or the internal transmission signal is the disable signal CE. Even in the case of overlapping or competing with # and the remaining 4/5 of the low-level period of the internal transmission signal, the present invention can be used to realize a memory operation or a data transmission operation. Thus, the success rate can be determined to be approximately 80%.

As shown in Fig. 7B, when the internal transmission signal precedes the disable signal CE # but overlaps, the internal activation signal is raised for a predetermined period in synchronization with the rise of the internal transmission signal, and the internal activation signal is disabled. It is raised for a predetermined period in synchronization with the falling of the signal CE #. In this case, if the period of the gap between the internal transmission signal and the disable signal CE # is longer than the predetermined activation period of the internal activation signal, the internal activation signal for the disable signal CE # and the internal activation signal for the internal transmission signal are stored in memory. Block 230 may be used to continuously activate time series.

As shown in Fig. 7C, when one memory operation (external disable signal CE # in this example) is performed and other memory operations (in this example, internal transfer signal from WSM) are executed a plurality of times, The first internal activation signal is raised for a predetermined period in synchronization with the fall of the disable signal CE #, and the second and third internal activation signals are raised for a predetermined period in synchronization with the subsequent falling of two internal transmission signals. . In this case, the operation of the internal transmission signal during the period in which the operation using the disable signal CE # is executed cannot be executed by the prior art even if several requests are received if the external access has precedence over the transmission operation. In the above embodiment of the present invention, the memory block 230 may be continuously activated in time series.

Next, when a data write operation to the memory block 230 is executed from the outside, the switching circuit 210 is instructed through the control bus 201 to write data to the memory block 230, and the written data is written to the data. It is input to the switching circuit 210 via the bus 202.

If the designated write operation is for the memory block 230, the switching circuit 210 instructs the control circuit 270 via the control bus 211 to perform the write operation, and writes the data to be written to the data bus 212. It transfers to the data latch circuit 271 through.

The control circuit 270 instructs the switching circuit 220 to perform a write operation via the control bus 282, so that the data latch control signal 281 is output to the data latch circuit 271, and the data bus ( Data input from the data latch circuit 271 from 212 is transferred to the switching circuit 220 via the data bus 283.

When the switching circuit 220 is instructed by the control circuit 270 through the control bus 282 to perform a write operation, the switching circuit 220 uses the control bus 221 and the data bus 222 to store the memory. Data is written to the memory device as the target of block 230. The series of operations constitutes an external write operation for memory block 230.

In this write operation, the period during which the memory block 230 is actually activated and the data operation is executed is limited to a predetermined period from the start of the write operation (access period limited to the minimum required for each access operation). After this period has elapsed, the write operation of the memory block 230 ends. Thereafter, the control bus 211 or the data bus 212 are released.

Therefore, after the internal write operation is finished, a write operation such as writing of next data from the outside, writing of transmission data read from the memory block 250, and the like can be started. It is possible to perform a write operation not using the WSM 260 and a read operation from the memory block 250.

However, the data write operation is executed when the data bus 212 and the data bus 283 are shared by the data read operation. In the case of the external write operation, a simple configuration may be used in which data to be written is transferred directly from the switching circuit 210 to the switching circuit 220 without passing through the data latch circuit 271.

Next, the access operation to the memory block 230 during the data transfer operation period will be described.

The data transfer operation is mainly necessary when transferring data from a memory having a high writing speed (memory block 230) to a memory having a slow writing speed (memory block 250). In Embodiment 2, data is transferred from memory block 230 to memory block 250. First, such an operation will be described.

When the WSM 260 is instructed via the control bus 215 and the data bus 216 to perform a data transfer operation from the memory block 230 to the memory block 250, the WSM 260 is moved from the memory block 230. The control circuit 272 is instructed via the control bus 261 to read the transmitted data.

The control circuit 272 instructs the switching circuit 220 through the control bus 285 to read data from the memory block 230, outputs the latch control signal 284 to the data latch circuit 273, and outputs the data. The data latch circuit 273 is instructed to transfer data output from the switching circuit 220 to the data latch circuit 273 via the bus 286 to the WSM 260 via the data bus 262.

When the switching circuit 220 is instructed through the control bus 285 to perform a read operation, the switching circuit 220 accesses the memory element to be the object of the memory block 230 through the control bus 221, and the data. Data is received from the bus 222, and data is transmitted to the data latch circuit 273 through the data bus 286.

The data latch circuit 273 first latches data transmitted from the data bus 286 by the latch control signal 284, and transfers the data to the WSM 260 via the data bus 262.

The WSM 260 receives the transmitted data via the data bus 262 and writes the data to the memory block 250. Since this writing operation can be realized by the conventional method, the description thereof is omitted.

After a predetermined period has elapsed since the read instruction was received, the control circuit 272 latches the read data transferred through the data bus 286 to the latch circuit 273 using the data latch control signal 284. The latched data is output to the WSM 260 through the data bus 262 until the read control through the control bus 261 ends.

In addition, even when the specified read control continues, when a predetermined period of time has elapsed, the control circuit 272 ends the read operation designated to the switching circuit 220 via the control bus 285.

Subsequently, the data output operation to the WSM 260 is executed by the data latch circuit 273 using the data bus 262. The timing of latching data by the data latch circuit 273 is executed using the latch control signal 284 generated by the control circuit 272.

According to this operation by the control circuit 272, the WSM 260 can be treated as if the read operation continues for a specified period, and even if the period required for the access operation from the WSM 260 is long, The period in which the 221 and the data bus 222 are used for the read operation from the WSM 260 (access period limited to the minimum required for each access operation) is suppressed to any level or less.

Therefore, even when the access operation from the WSM 260 to the memory block 230 and the external access operation to the memory block 230 occur at the same time, two operations may proceed pseudo-simultaneously, thereby It is possible to realize a data transfer operation that does not depend on external circumstances.

Next, a case in which the data transmission direction is reversed will be described. Specifically, the data transfer operation from the memory block 250 to the memory block 230 will be described. Since this operation differs only in that a path different from the external data write operation to the memory block 230 is used, the description thereof is omitted. The data written to the memory block 230 is latched by the data latch circuit 273 to be different merit.

In the write operation, the period in which the memory block 230 is activated so that data is actually written to it is only a predetermined period from the start of writing. After this period has elapsed, the write operation to the memory block 230 is terminated, and the control bus 221 and the data bus 222 are released.

However, since the data to be written is latched by the data latch circuit 271 when a predetermined period has elapsed, the period in which the WSM 260 activates the memory block 250 for the data transfer operation is the minimum value necessary for the read operation. Can be shortened. After the read operation, since the control bus 241 and the data bus 242 are released, the external access operation to the memory block 250 becomes possible.

In this way, by latching the data to be written, the access operation to the memory 250 becomes efficient.

As described above, according to the second embodiment, in the semiconductor memory device 290 having a function of transferring data between two memory areas (memory blocks 230 and 250), a more general use and a faster writing speed are achieved. An efficient access operation for the memory block 230 and more efficient data storage for the memory block 250 having a slow writing speed can be realized.

However, in the second embodiment, although not specifically described, the period in which the control circuit 270 and the control circuit 272 actually executes the access operation to the memory block 230 is a time sufficient for the access operation. However, accurate timing is not required. However, if the period is longer than necessary, the timing margin can be reduced, but the merit obtained by the present invention is reduced. Therefore, it is necessary to set the period within an appropriate range.

In addition, in Embodiment 2, although the present invention has been described in an example in which the memory block 230 has a high writing speed, the configuration limiting the period in which the memory block 230 is accessed is actually a memory block 250 having a slow writing speed. Applicable to

(Example 3)

Fig. 8 is a block diagram showing the main parts of a semiconductor memory device according to the third embodiment of the present invention. 8 shows only portions necessary for explanation of the semiconductor memory device of the present invention. The configuration of the semiconductor memory device 390 shown in FIG. 8 is an example of the semiconductor memory device according to the present invention, but is not limited to the configuration of the third embodiment similarly to the first and second embodiments. The memory blocks 330 and 331 with the correct writing speed included in the semiconductor memory device 390 are two memory areas that can be operated independently, similarly to the semiconductor memory device 190 described in the first embodiment. In addition, as with the semiconductor memory device 290 described in the second embodiment, the memory having the high write speed included in the semiconductor memory device 390 can be reduced in the period in which the memory having the high write speed is actually accessed in control. It is configured to be.

As in the first embodiment, when the memory block 330 is used for a data transfer operation, an external access operation to the memory block 331 can be executed independently of the data transfer operation. Therefore, the data transfer operation is not affected by the external access operation. In addition, when the memory block 330 is used for the data transfer operation, if the memory block 330 is also controlled from the outside (memory operation), similarly to the second embodiment, both operations can be controlled pseudo-simultaneously. According to this configuration, the external access operation (memory operation) is less likely to affect the data transfer operation.

As described above, according to the third embodiment, in the semiconductor memory device 390 having a function of transferring data between two memory areas (memory blocks 330 and 331), more general use and writing speed are achieved. More efficient access operations for the faster memory blocks 330 and 331, and more efficient data storage for the memory block 350 with a slower writing speed can be realized.

As described above, according to the present invention, there is provided a data transfer operation for transferring stored data to a separate address, and a memory operation for controlling a storage area used for the data transfer operation using instructions from the outside of the semiconductor memory device. In the semiconductor memory device to be executed, in the case where data transfer operation and external memory operation or memory operations are executed in parallel, even if there is contention (contrast between disable signal CE # and internal transfer signal) between the operations, The operation can be controlled efficiently.

However, although not specifically described in the third embodiment, as described in the first embodiment, the memory block 350 having a slow writing speed may be composed of a plurality of areas that can be operated independently. As described in Embodiment 2, the period for the memory block 350 with a slow writing speed may be limited. The extent to which the present invention is applied to which memory block is a trade off between performance and circuit scale, which is a problem that should be considered based on the specification or application of the device.

Although not specifically described in the third embodiment, in order to realize higher speed operation, the semiconductor memory devices shown in Figs. 1, 2 and 8 may be integrated on a single semiconductor chip.

In addition, although the semiconductor memory device has been described in the first to third embodiments, the semiconductor memory device of the present invention can be easily embedded in an information device such as a cellular phone device, a computer, etc., and the effect of the present invention can be obtained. have. For example, as shown in Fig. 9, the information apparatus 100 stores information storage units such as RAM (e.g., SRAM, DRAM) or ROM (e.g., flash memory), an operation input unit such as an initial screen, or an information processing result. Receives control commands from a display unit such as a liquid crystal display to display and an operation input unit, and performs information read / write operation (memory operation) or data transfer operation to the information storage unit in accordance with a predetermined information processing program or the data. In the case of including a CPU (central processing apparatus) that executes various information processing while performing the processing, the semiconductor memory device of the present invention can be easily used as an information storage section (RAM or ROM).

For example, the effect when the semiconductor memory device of the present invention is applied to a cellular phone device will be described below. In this case, such a mobile phone device is a stacked package memory that includes flash memory and SRAM, which are frequently adopted recently, in a single package, or a Japanese public disclosure regarding a mobile phone device having a flash memory and an SRAM. Qualitatively describes that the efficiency of memory access is improved based on the system in the case of employing a memory including SRAM and flash memory described in Patent Publication No. 2000-176182, which is incorporated herein by reference. .

In Japanese Patent Laid-Open No. 2000-176182, for example, by providing a data transfer function from an SRAM to a flash memory, the SRAM can be operated even during a data transfer operation.

The present invention improves convenience when the memory of Japanese Patent Laid-Open No. 2000-176182 is used in an actual system.

In recent years, portable telephone apparatuses perform advanced functions such as mail functions, web browsing, and execution of Java (registered trademark of Sun Microsystems, Inc., USA).

Such applications frequently transfer data temporarily stored in SRAM to flash memory, for example, for storing mail, for caching at web browsing time, for downloading Java.

In the case of the conventional stack package memory, when the data stored in the SRAM is stored in the flash memory in this manner, the CPU reads the data stored in the SRAM and writes the read data into the flash memory. This operation is repeated until all data is preserved.

Access to the SRAM is possible while the flash memory is being written. However, at the end of the write operation, in order to save the data, the operation of reading the stored data from the SRAM again and writing it to the flash memory must be repeated until all the data is written to the flash memory. Therefore, in order to simultaneously perform data storage and execution of other applications, advanced task management is required, which leads to a decrease in performance.

When using a memory capable of background transfer from SRAM to flash memory described in Japanese Laid-Open Patent Publication No. 2000-176182, reading of the SRAM and writing of the flash memory need not be performed one by one. In this case, when the transfer command is input to the memory, the SRAM can be accessed even after the data transfer operation, and data transfer is performed from the SRAM to the flash memory.

For example, a situation in which the Java application is executed is conceived while the Java application temporarily downloaded to the SRAM is preserved in the flash memory.

Running a Java application requires a working RAM area. SRAM in which Java applications are stored is likely to be used as a RAM area and is frequently accessed.

By the data transfer operation, a Java application stored in the SRAM is transferred to the flash memory. At the same time, the Java application must be read from SRAM for its execution. In addition, access to the working RAM is required if a Java application is to be executed.

According to the memory of the invention of Japanese Patent Laid-Open No. 2000-176182, such simultaneous operation can be realized, but there is a possibility that the operation of reading out the SRAM for execution may affect the data transfer operation.

That is, since the operation of the external SRAM is prioritized, the read operation of the internal SRAM due to the data transfer operation may be hindered.

In the present invention, even when the read operation of the internal SRAM in the data transfer operation is in conflict with the memory operation of the external SRAM, it is possible to reduce the probability that the time required for the data transfer operation is increased.

That is, if the frequency of the read operation of the SRAM for data storage to the flash memory is in conflict with the operation (memory operation) of the SRAM from outside the memory by another application, the data transfer operation is required by the execution of the application. The increase in time can be suppressed.

In the above Java application example, there is a possibility that the preservation of the Java application, the read operation for executing the Java application, or the operation of the working RAM may compete. Therefore, the time required for the data transfer operation may increase. However, the frequency of this situation is reduced by the present invention, which alleviates the degradation of the performance of the preservation operation of the Java application caused by the execution of the Java application.

With this feature, in the memory using the present invention, compared to the conventional stack package memory or the memory described in Japanese Patent Laid-Open No. 2000-176182, an application in which data is stored in a flash memory is executed a plurality of times, or data is stored. It is easy to run a separate application while being kept in flash memory.

As described above, according to the present invention, either a memory controller capable of independently accessing a small storage area or a memory controller in which an access period is limited to a minimum required for activating a memory array of a storage unit is provided. In at least one, it is possible to reduce the probability of contention between the external memory operation and the data transfer operation or the external memory operations. Thus, for example, it is possible to suppress the slowing down of the data transfer operation while preferentially processing the memory operation from the outside, or reduce the probability that the external memory operation is interrupted while preferentially processing the data transfer operation.

Various other changes may be readily made by those skilled in the art without departing from the scope and spirit of the invention. Accordingly, the appended claims should not be limited to the content described herein, but should be construed broadly.

Claims (20)

First and second storage units including a plurality of memory elements; And A memory control section for enabling a data transfer operation between the first and second storage sections according to a control command from the outside, and for enabling a memory operation for at least one of the first and second storage sections. As a semiconductor memory device, At least one of the first and second storage units includes a plurality of small storage areas, The memory control section is a semiconductor memory device in which the access operation can be performed independently and simultaneously for each of the plurality of small storage areas. The memory controller of claim 1, wherein the memory controller is configured to use one small memory area for a data transfer operation while another small memory area is used for a memory operation, or to use another small storage area separately for another memory operation. And controlling a plurality of small storage areas so that one small storage area is used for a memory operation, thereby simultaneously executing data transfer operations and memory operations and / or memory operations. 3. The semiconductor memory device according to claim 2, wherein said first and second storage portions comprise different memory elements, and one of said first and second storage portions having a high writing speed includes a plurality of small storage regions. The access control unit according to claim 2, wherein the memory control unit includes: an access operation unit for limiting an access period for at least one of the first and second storage units to a minimum required for each access operation, and within a predetermined access period by the access operation unit. A semiconductor memory device having a third storage unit for storing memory data of the memory. 2. The semiconductor memory device according to claim 1, wherein said first and second storage portions comprise different memory elements, and one of said first and second storage portions having a high writing speed includes a plurality of small storage regions. The access control unit according to claim 3, wherein the memory control unit includes an access operation unit for limiting an access period for at least one of the first and second storage units to a minimum required for each access operation, and within a predetermined access period by the access operation unit. A semiconductor memory device having a third storage unit for storing memory data of the memory. The access control unit according to claim 1, wherein the memory control unit comprises: an access operation unit for limiting an access period for at least one of the first and second storage units to a minimum required for each access operation, and within a predetermined access period by the access operation unit. A semiconductor memory device having a third storage unit for storing memory data of the memory. The method of claim 7, further comprising: an access complete signal generator for generating an access complete signal upon completion of the access; And the access operation receives an access complete signal and ends the access period initiated by the access grant signal. 8. The memory controller according to claim 7, wherein the memory control unit has a third storage unit that stores predetermined memory data within an access period limited by the access operation unit, and the memory control unit is at least one of the first and second storage units. And a data storage operation for performing data read operation within the access period limited by the access operation unit when data is read from the memory, and storing the read data in the third storage unit. The memory device of claim 9, wherein the memory elements included in the first and second memory units have different shapes. And the memory control section reads data from one of the first and second storage sections with a high writing speed. 8. The semiconductor memory device according to claim 7, wherein the memory control unit writes data to at least one of the first and second storage units within an access period limited by the access operation. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is integrated on a single semiconductor chip. First and second memory units including a plurality of memory elements; And According to an external control command, a semiconductor memory including a memory control unit for enabling a data transfer operation between the first and second storage unit, and at least one memory operation for at least one of the first and second storage unit As a device, And the memory control unit has an access operation unit for limiting an access period for at least one of the first and second storage units to a minimum required for each access operation. The apparatus of claim 13, further comprising an access complete signal generator for generating an access complete signal upon completion of the access. And the access operation receives an access complete signal and ends the access period initiated by the access grant signal. The memory controller according to claim 13, wherein the memory control unit has a third storage unit that stores predetermined memory data within an access period limited by the access operation unit, and the memory control unit is at least one of the first and second storage units. And a data storage operation within the access period limited by the access operation unit when data is read from the memory, and storing the read data in the third storage unit. The memory device of claim 15, wherein the memory elements included in the first and second memory units have different shapes. And the memory control section reads data from one of the first and second storage sections with a high writing speed. The semiconductor memory device according to claim 13, wherein the memory control unit writes data to at least one of the first and second storage units within an access period limited by the access operation. The semiconductor memory device according to claim 13, wherein said semiconductor memory device is integrated on a single semiconductor chip. An information device using the semiconductor memory device according to claim 1 to perform at least one of a data transfer operation and a memory operation, or to perform at least two memory operations within an access period. And the access completion signal is generated upon completion of the access, and upon reception of the access completion signal, the access initiated by the access permission signal is terminated.