KR20030002467A - Nonvolatile memory device and method of forming the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a method for forming the same are provided to maintain a coupling constant as a high value in a stack gate type transistor and prevent leakage of carrier due to a dense electric filed in a peripheral part of a gate stack. CONSTITUTION: An isolation layer is formed on a substrate(100). A gate insulating layer(103) is formed on an active region of the substrate(100). A thin gate insulating layer(105) is formed on a tunneling region. A floating gate layer(107) is deposited on the gate insulating layer(103) and the thin gate insulating layer(105). A line pattern is formed by patterning the floating gate layer(107). An insulating layer is formed on the line pattern. A dielectric layer is formed on the whole surface of the substrate(100). A conductive layer is stacked on the dielectric layer. A conductive layer pattern(141) is formed by patterning the conductive layer. A plurality of gate lines(300,200) are formed by removing selectively the line patterns of the dielectric layer, the remaining insulating layer, and the floating gate layer(107). The gate lines(300,200) are formed with the conductive layer pattern(141), a dielectric layer pattern(131), an insulating layer pattern(123), and the floating gate(107).

Description

Nonvolatile Memory Device and Formation Method {NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE SAME}

The present invention relates to a nonvolatile memory device such as EEP ROM (Electrically Erazable Programmable Read Only Memory) and a method of forming the same. More specifically, the present invention relates to a stack gate type in which floating and control gates are stacked. A nonvolatile memory device and a method of forming the same.

EPROM is an electrically erasable and programmable memory device among nonvolatile memories. In EPROM, as with other nonvolatile memories, it is common to have a floating gate in a memory transistor and store data by injecting or releasing a carrier using a tunneling phenomenon.

In the conventional EPI, each memory cell has one memory transistor and one selection transistor. The gate of the memory transistor is a stacked gate type, which is divided into a floating gate and a regulating gate for nonvolatile characteristics. The floating gate and the regulating gate are insulated and coupled with an oxide of Nitride Oxide (ONO) dielectric film. In this case, the floating gate surrounds the dielectric film and the control gate in a word line direction. In addition, there is a portion where the gate insulating film is thinly formed to facilitate turnneling in a portion between the floating gate and the substrate.

However, in the peripheral portion of the gate electrode of the memory transistor, the floating gate 13 and the control gate 17 have their vertical cross-sections etched as shown in I of FIG. 1 through etching during patterning. Electrically, the edge portion has a curvature effect of an electric field, so that a flat dielectric film 15 that can maintain insulation between the floating gate 13 and the regulating gate 17 is typically a corner portion. The problem arises in that the increased electric field results in insufficient insulation. Therefore, there is a high possibility that carrier detachment occurs in which charge carriers accumulated in the floating gate 13 escape to the control gate 17.

Carrier escape from the floating gate is the loss of data stored in the memory transistor. Therefore, if the carrier departure continues, the data retention characteristic, which is an important characteristic of the nonvolatile memory, is deteriorated and the reliability of data restoration is deteriorated.

Electrically Programmable Read Only Memory (EPROM), which is one of nonvolatile memories, also has a relatively small voltage difference. It has the problem of carrier departure mentioned in pyrom.

In order to solve the problem of carrier departure in a nonvolatile memory device having such a stacked gate transistor, the thickness of the dielectric film between the floating gate and the regulating gate may be thick enough to withstand electric field density. However, when the dielectric film is thick, the capacitance of the capacitor formed by the floating gate and the regulating gate is decreased, and the degree of coupling decreases, thereby causing a problem of increasing the voltage applied to the regulating gate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and in the stack gate type transistor of a nonvolatile memory device, a ratio of preventing carrier leakage due to the electric field density at the periphery of the gate stack while maintaining a high coupling constant. An object of the present invention is to provide a volatile semiconductor device and a method of forming the same.

Accordingly, an object of the present invention is to provide a nonvolatile memory device and a method for forming the same, which can lower the voltage used for the nonvolatile memory device and at the same time increase data retention and reliability.

1 is a cross-sectional view showing a problem of a stack gate transistor of a conventional nonvolatile memory;

2 through 5 are cross-sectional views of the cell region cut in the gate line direction to illustrate important process steps up to the formation of a gate line in accordance with one embodiment of the present invention;

6 through 10 are cross-sectional views of cell regions cut perpendicular to gate lines to illustrate important process steps according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided a nonvolatile memory device including a stacked gate type transistor in which a floating gate and a control gate are separated and stacked by a dielectric layer. The dielectric film is characterized in that the relatively thick formed.

The present invention can be applied to both pyroms and EPROMs, but may be particularly well applied to EPROMs that are susceptible to high voltages.

In the present invention, the insulating film between the floating gate and the substrate may have a region that is partially thinned. The periphery of the floating gate refers to an area extending from the boundary with a meaningful width at the boundary of the floating gate.

A method of the present invention includes forming a gate insulating film in an active region of a substrate, stacking and patterning a floating gate film over the gate insulating film to form a floating gate pattern in the form of a line in one direction, and stacking the insulating film over the floating gate pattern. Removing the insulating film from a central region of a predetermined floating gate electrode, stacking a dielectric film over the substrate, stacking a control gate layer, and intersecting the control gate layer, the dielectric film and the floating gate pattern with the one direction. And selectively etching the line to form a gate line.

In the method of the present invention, in the forming of the gate line, the floating gate pattern is etched to form the floating gate electrode. The center region of the floating gate electrode generally means the whole region excluding a predetermined width inward from the boundary of the floating gate electrode. In this case, the constant width does not necessarily mean that the width becomes a predetermined value, and it is satisfied that the width exists meaningfully.

In the present invention, the dielectric film is usually formed of an ONO film, and the insulating film is generally formed of a gate oxide film.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 through 5 are cross-sectional views of the cell region cut in the gate line direction to illustrate important process steps up to the formation of a gate line according to one embodiment of the present invention.

6 through 10 are cross-sectional views of cell regions cut perpendicular to gate lines to illustrate important process steps according to an embodiment of the present invention.

2 and 6, first, an element isolation layer 101 is formed on a substrate 100 to perform element isolation. The gate insulating layer 103 is formed in the active region through substrate thermal oxidation. In this case, the gate insulating layer 105 having a thickness thinner than that of other regions should be formed in the region for turningneling. In order to form the gate insulating layer 105 having a thin thickness, a method of partially etching the gate insulating layer 103 or reoxidizing the entire surface may be used.

A floating gate layer 107 such as a polysilicon layer is stacked on the gate insulating layers 103 and 105 and patterned to form a line pattern extending in the same direction as the active region.

3 and 7, an insulating film 120 made of a silicon oxide film is formed mainly over a line pattern formed of the floating gate film 107. At this time, the silicon oxide film can be normally formed by CVD. The thickness is considered to be sufficient to withstand the electric field integrated in the periphery of the floating gate, taking into account the thickness of the dielectric film to be subsequently formed.

4 and 8, an insulating film 121 made of a silicon oxide film is formed at a periphery of a region in which a floating gate electrode is to be formed, including both side portions of a line pattern formed of a floating gate film 107 that will be finally left through a patterning operation. ) And the insulating film in the center portion is removed.

5 and 9, a dielectric film 130 is stacked over the entire surface of the remaining insulating film 121. The dielectric film 130 is typically made of an oxide nitride oxide (ONO) film. The oxide film in the dielectric film 130 may be formed by stacking a silicon oxide film by CVD or by oxidizing silicon forming the floating gate film 107 at high temperature, and the nitride film is formed by stacking a silicon nitride film by CVD or by nitriding silicon and a silicon oxide film at high temperature. can do. In order to increase the coupling ratio between the floating gate and the regulating gate, a thin ONO film should be formed, but if too thin, insulation will be a problem, so that the ONO film should be formed to the smallest possible thickness.

After the dielectric layer 130, a conductive layer 140 for forming a control gate is stacked on the entire surface of the substrate. The conductive film 140 is usually formed of a polysilicon layer or a polysilicon layer and a metal silicide layer.

9 and 10, after forming the conductive layer 140 for forming the control gate used in the memory transistor of the cell, the conductive layer is selectively removed through a patterning process to form the conductive layer pattern 141. Subsequently, the line pattern composed of the dielectric film 130, the remaining insulating film 121 and the floating gate film 107 is selectively removed to form the conductive film pattern 141, the dielectric film pattern 131, the insulating film pattern 123, and the like. Gate lines 300 and 200 formed of floating gates 107 are formed. In this case, together with the gate line 300 for the memory transistor of the cell, the gate line 200 for the selection transistor is also formed through the same etching step.

Subsequently, ion implantation into the active region is performed using the gate line as an ion implantation mask, followed by lamination of an interlayer insulating layer, contact hole formation through patterning, and formation of bit lines and bit line contacts.

In the above-described embodiment of the present invention, the dielectric film is thickened in the periphery of the floating gate electrode. Before the ONO dielectric film is formed, the oxide film is first stacked and the oxide film is removed from the floating gate electrode center. However, for example, the ONO dielectric film is formed first, and the top oxide film is removed from the center of the floating gate electrode, and the oxide film is generally stacked again, or the dielectric film is formed first, and the oxide film is laminated later. The use of various modifications, including removal of some, will not need to be mentioned to those skilled in the art.

According to the cell memory gate electrode of FIG. 10 obtained through the above steps, an insulating film pattern 123 is formed on both sides of the gate line 300 of the memory transistor based on the top surface of the floating gate 107 in addition to the dielectric film pattern 131. do. As a result, the dielectric film between the floating gate and the conductive film pattern 141, that is, the control gate, is thickly formed at the periphery of the floating gate film pattern constituting the floating gate electrode, and insulation is enhanced in this region. Therefore, the carrier of the floating gate electrode can be prevented from escaping toward the control gate electrode even in a region around the floating gate electrode where the electric field is concentrated between the floating gate electrode and the control gate electrode.

According to the present invention, in a nonvolatile memory device having a stacked gate type transistor, the top and side surfaces of the gate electrode form corners in the peripheral region of the gate electrode according to gate line patterning, and this portion of the dielectric film between the floating gate and the control gate is formed. It is possible to prevent the dielectric film from becoming relatively weak. In other words, due to the concentration of the electric field in the corner portion, the dielectric film having the same thickness becomes relatively fragile in this portion, thereby preventing the charge carriers stored in the floating gate from escaping to the control electrode.

Claims (9)

A nonvolatile memory device comprising a stacked gate type transistor in which a floating gate and a control gate are stacked with a dielectric film interposed therebetween. When viewed in plan view, the thickness of the dielectric film is relatively thicker in the periphery of the floating gate than in the center of the floating gate. The method of claim 1, The dielectric layer is a non-volatile memory device, characterized in that consisting of ONO (Oxide Nitride Oxide) film. The method of claim 1, The nonvolatile memory device is an EEPROM. The method of claim 3, wherein And a gate insulating layer between the floating gate and the substrate is thinly formed in a portion for turningneling. Forming a gate insulating film in an active region of the substrate, Stacking and patterning a floating gate layer on the gate insulating layer to form a floating gate pattern having a line shape in one direction; Stacking an insulating film over the floating gate pattern, and forming a residual insulating film pattern for removing the insulating film from a center region of the floating gate electrode to be formed; Depositing a dielectric film over the substrate; Stacking a control gate layer, And selectively etching the control gate layer, the dielectric layer, the residual insulating layer pattern, and the floating gate pattern in a line shape crossing the one direction to form a gate line. The method of claim 5, Forming the gate insulating film First forming a relatively thick gate insulating film, Removing the thick gate insulating layer in a portion of the region where the floating gate pattern is to be formed; And forming a relatively thin gate insulating film in a portion of the region where the floating gate pattern is to be formed. The method of claim 5, And the dielectric layer is formed of an oxide nitride oxide (ONO) layer. The method of claim 7, wherein The floating gate layer is formed of polysilicon, And forming a lower oxide layer under the ONO layer by thermally oxidizing the floating gate layer. The method of claim 5, And forming said dielectric film precedes forming said residual insulating film pattern.