KR20030002228A - DDR memory for high data write speed - Google Patents

Abstract

PURPOSE: A DDR memory for writing rapidly data is provided to reduce a time for a data write process and lower a peak current value and increase a data alignment margin when a bank write enable signal is in an active state by improving a writing speed. CONSTITUTION: A data buffer(100) is used for storing temporarily write data. A data strobe buffer is used for storing temporarily the first to the fourth data strobe signals. A divider portion receives output signals of the data strobe buffer and generates the first to the fourth data strobe signals. A latch portion(400) latches an output signal of the data buffer(100) in response to the first to the fourth data strobe signals of the divider portion. A bank write enable signal generation portion(500) receives a plurality of rising and falling edge bank write enable signals(bwen-r,bwen-f) and generates four bank write enable signals(bwen1 to bwen4). A write driver portion(600) transmits an output signal of the latch portion(400) to a local input/output line(Lio) in response to the bank write enable signals(bwen1 to bwen4).

Description

DDR memory for high data write speed

The present invention relates to a memory device, and more particularly, to a DDR memory device with improved write speed.

DDR memory is a memory that processes two data in one clock cycle. Data can be input and output on the rising and falling edges of an externally input clock. It is possible to realize twice the bandwidth compared to), which is a memory capable of high speed operation.

Meanwhile, as described above, the DDR memory inputs and outputs data at the rising edge and the falling edge of the external clock to be input. When the data is inputted and outputted to inform the memory controller or the central processing unit of the precise timing of the input and output data, In addition, a data strobe signal (hereinafter referred to as DQS) is output.

1 shows a write driver of a conventional DDR memory.

The conventional DDR memory latches the data of the input buffer by an input buffer 10 for inputting write data, a data strobe buffer 20 for inputting a data strobe signal DQS, and the data strobe signal. A latch unit 30 to align, a data align unit 40 to align the output of the latch unit 30, a global input / output line unit 50 to load the aligned data into a global input / output line, and write The driver unit 60 is formed.

2 illustrates a timing diagram of an input / output signal according to a conventional write method of a DDR memory. Hereinafter, a write operation of the DDR memory will be described with reference to the drawing.

First, in the DDR memory, data can be written at the rising edge and the falling edge of the clock, respectively, and the data strobe signal DQS is 0.75 × tCK ~ 1.25 × tCK (clock cycle time) after a command (read or write) is input. ) And the control signal DQS appears only within the range of 0.5 x tCK.

Here, the clock cycle time (tCK) means a time taken for one cycle of the clock supplied to the DDR memory to proceed.

In FIG. 1, data can be aligned in two places after a write command during data write.

The first is to align the write data when 0.75 x tCK or 1.25 x tCK, and the second is to synchronize the aligned data to the data strobe DQS, which is the waveform output to the global input / output line.

Thereafter, the write data aligned twice in the global input / output line GIO is local input / output line by a control signal bwen (bank write enable) which allows writing to a target bank among a plurality of banks existing in the memory. After being loaded into (LIO), it is written to the memory cell.

Here, referring to the data write process of the conventional DDR memory, two alignment processes and the aligned data are loaded to the local input / output line LIO in synchronization with the control signal bwen.

This means that when writing data to the DDR memory, it is necessary to consume several steps of clock until the actual data is written to the memory cell, and as the operating frequency of the DDR memory gradually increases, the data alignment margin decreases gradually. When writing data to the DDR memory, a large amount of time is lost.

In addition, since all data is simultaneously loaded into the global I / O line by one data input strobe signal, and all of the loaded data is simultaneously transmitted to the local I / O line by the bank write enable signal, peak current during write operation is increased. There is a problem that flows.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and reduces the time required to write the data of the DDR memory while reducing the peak current value when the bank write enable signal is activated and increasing the data alignment margin. The purpose is to provide.

1 is a block diagram of a DDR memory using a conventional write method.

2 is a timing diagram of a DDR memory using a conventional write method.

3 is a block diagram of a DDR memory using the write method according to the present invention.

4 is a timing diagram of a DDR memory using the write method according to the present invention.

* Explanation of symbols for the main parts of the drawings

100: data buffer 200: data strobe buffer

300 Divider part 400 Latch part

500: bank write enable signal generator 600: write driver

The present invention relates to a DDR memory device, to which the present invention relates to a write driver in a memory for writing data into a DDR memory, comprising: a data buffer for temporarily storing input write data; A data strobe buffer for temporarily storing a data strobe signal generated by sensing the input write data; A divider unit configured to generate a first data strobe signal to a fourth data strobe signal by using an output of the data strobe buffer; A latch unit configured to latch an output of the data buffer for a predetermined time in response to the first to fourth data strobe signals generated by the divider unit; A bank write enable signal generator configured to generate four bank write enable signals by inputting a bank write enable signal generated by sensing an output of the latch unit; And a write driver unit transmitting the output of the latch unit to a local input / output line in response to the plurality of bank write enable signals.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 shows an embodiment of a write driver of a DDR memory according to the present invention.

Referring to FIG. 3, a data buffer 100 temporarily storing input write data in a write path in a memory for writing data in a DDR memory, and first and second signals generated by sensing the input write data. The data strobe buffer 200 temporarily storing the data strobe signals dsr1, dsf1, dsr2, and dsf2, and the output of the data strobe buffer 200 as inputs for the first data strobe signal to the fourth data strobe signal. The output of the data buffer 100 is latched for a predetermined time in response to the generated divider 300 and the first to fourth data strobe signals dsr1, dsr2, dsf1, and dsf2 generated by the divider 300. The latch unit 400 and the rising and falling edge bank write enable signals bwen_r and bwen_f generated by sensing the output of the latch unit 400 as inputs to the four bank write-ins. In response to the bank write enable signal generator 500 generating the enable signals bwen1 to bwen4 and the four bank write enable signals bwen1 to bwen, the output of the latch unit 400 is output to a local input / output line ( And a write driver 600 for transmitting to Lio.

In detail, the bank write enable signal generator 500 separates the rising edge bank write enable signal bwen_r, which is generated to align data loaded on the global input / output line GIO, into two signals. A falling edge generated to align the data loaded in the first bank write enable signal generator 510 and the global input / output line GIO to generate the first and second bank write enable signals bwen1 and bwen2. And a second bank write enable signal generator 520 for generating the third and fourth bank write enable signals bwen3 and bwen4 by separating the bank write enable signal bwen_f into two signals. ,

The latch unit 400 includes four latches 410 to 440 for inputting the outputs of the four divider units 300, and includes a first data strobe signal dsr1 detected upon rising edge of the first clock. A first latch 410 latching the first data d1 and a second latch latching the second data d2 by the second data strobe signal dsf1 detected at the falling edge of the first clock. 420, a third latch 430 latching the third data d3 by the third data strobe signal dsr2 detected when the rising edge of the second clock is detected, and a fourth data strobe detected when the falling edge of the second clock is detected. And a fourth latch 440 which latches the fourth data d4 by the signal dsf2.

The write driver 600 may include a first write driver 610 which transmits the output of the first latch 410 to a local input / output line Li by the first bank write enable signal bwen1; The second write driver 620 transmits the output of the second latch 420 to a local input / output line by the third bank write enable signal bwen2, and the second bank write enable signal bwen3. Output of the fourth latch 440 by the third write driver 630 and the fourth bank write enable signal bwen4 that transmit the output of the third latch 430 to the local input / output line Lio. And a fourth write driver 640 for transmitting the data to a local input / output line.

The operation of the present invention having the above configuration will be described in detail with reference to FIGS. 3 and 4.

First, two data strobe signals input to the data strobe buffer 200 are data strobe signals dsr1 and dsr2 for detecting two rising edges and two falling edges for the divider 300. It is divided into signals dsf1 and dsf2.

Next, the first data (d1) output when the rising edge of the first clock of the data input to the data buffer 100, the second data (d2) output when the falling edge of the first clock, the rising edge of the second clock The third data d3 output at the time of output and the fourth data d4 output at the falling edge of the second clock are outputted from the data buffer 100 to be respectively configured to the first, second, third, and fourth latches 410,. 420, 430, and 440.

Here, the first and fourth data d1 to d4 are input to the latch unit 400 in synchronization with the first and fourth data strobe signals dsr1 to dsf2, respectively, and then to the global input / output line GIO. Loaded.

On the other hand, the rising edge bank write enable signal bwen_r and the falling edge bank write enable signal bwen_f to write data to the bank in the memory when the data loaded in the global input / output line is applied to the write driver unit 600. ) Is sequentially activated to become a control signal for controlling the output of the write driver 600. The first bank write enable signal generator 510 receives the rising edge bank write enable signal bwen_r. The first bank write enable signal bwen1 for outputting the input data d1 on the rising edge of the first clock to the local input / output line via the first write driver 610 and the data input on the rising edge of the second clock are input. Generates a third bank write enable signal bwen3 for outputting to the local input / output line via the third write driver 630, The second bank write enable signal generator 520 generates the second and fourth bank write enable signals bwen2 and bwen4 upon the falling edge in the same manner as the first bank write enable signal generator.

Finally, the write drivers 610 to 640 sequentially load data into the local input / output lines according to the first and fourth bank write enable signals bwen1 to bwen4.

So far, the schematic operation of the present invention has been described with reference to FIG. 3.

The operation of the present invention will now be described in more detail with reference to FIG.

First, since the data d1 to d4 input to the data buffer 100 are latched by the first and fourth data strobe signals dsr1, dsf1, dsr2, and dsf2, the strobe signal is doubled as compared with the related art. The data width inputted to each of the latches 410 to 440 is doubled.

Since the widths of the first and fourth data d1 to d4 are doubled, the data width of the data input to each of the latches 410 to 440 is increased, so that data inputted at the rising edge of the data is stored in the data. When the strobe signal is aligned by the strobe signal (first and fourth data strobe signals), the latched data becomes the latched data and appears to be 0.75 × tCK delayed and when the latched data appears to be 1.25 × tCK delayed. When the data latched when loaded to the global input / output line by the first and fourth data strobe signals dsr1 to dsf2 is 0.75 x tCK delay and 1.25 x tCK delay, the data is loaded on the global input / output line.

Therefore, in the data inputted at the first 0.75 x tCK (clock cycle time) and the latest incoming condition 1.25 x tCK, it is easy to align data in the case of 0.75 x tCK and 1.25 x tCK. In the first data strobe signal for data alignment, the distance from the next strobe signal is more than doubled.

Subsequently, when the first data is latched by the first data strobe signal dsr1, the first bank write enable signal bwen1 is activated and one clock delayed to activate the third bank write enable signal bwen3. When the third data d3 is latched by the third data strobe signal dsf2, the second and fourth bank write enable signals bwen2, like the first and third bank write enable signals are generated. bwen4) is activated.

Accordingly, since the first and fourth bank write enable signals do not appear at the same timing on the local input / output line Li at the same timing as shown in FIG. 4, the first and fourth bank write enable signals are delayed for a predetermined time. peak current) does not occur.

In addition, since the data strobe signal and the bank write enable signal are doubled in comparison with the prior art, the width of the data input to the data buffer 100 is doubled, thereby increasing the margin for data alignment. do.

Therefore, even if the operation clock of the DDR memory rises more than twice, it is possible to generate a data strobe signal for data alignment.

According to the present invention, even if the operating frequency of the DDR memory is increased by more than two times, the data alignment margin is increased so that the operation can be performed at high frequency, and the data strobe signal is again aligned after the alignment of the falling edge data strobe signal. In this case, the data write operation is faster than the conventional method since the method does not use the two-level alignment method, and the peak current can be lowered because data is not simultaneously loaded from the global input / output line to the local input / output line.

Claims (5)

In a DDR memory device, A data buffer for temporarily storing input write data; A data strobe buffer for temporarily storing a data strobe signal generated by sensing the input write data; A divider unit configured to generate a first data strobe signal to a fourth data strobe signal by using an output of the data strobe buffer; A latch unit configured to latch an output of the data buffer for a predetermined time in response to the first to fourth data strobe signals generated by the divider unit; A bank write enable signal generator configured to generate first and fourth bank write enable signals by inputting a bank write enable signal generated by sensing an output of the latch unit; And A write driver unit transmitting the output of the latch unit to a local input / output line in response to the plurality of bank write enable signals DDR memory device having a. The method of claim 1, The bank write enable signal generator, A first bank for synchronizing the rising edge of the clock and aligning the odd bank write enable signal generated to align the data loaded on the global input / output line into two signals to generate the first and second bank write enable signals. A write enable signal generator; And A second bank for synchronizing the falling edge of the clock and for generating the third and fourth bank write enable signals by separating the even bank write enable signal generated to align the data loaded on the global input / output line into two signals. DDR memory device comprising a write enable signal generation unit. The method of claim 1, The divider unit, A rising edge detection signal and a falling edge detection signal output from the data strobe buffer are input to generate a first data strobe signal and a second data strobe signal for detecting rising edges and falling edges of the first clock, and rising of the second clock. And a third data strobe signal and a fourth data strobe signal for detecting edges and falling edges. The method of claim 1, The latch unit, It consists of four latches as inputs to the output of the four dividers, A first latch for latching the first data by the first data strobe signal detected upon the rising edge of the first clock; A second latch for latching the second data by the second data strobe signal detected upon the falling edge of the first clock; A third latch for latching the third data by a third data strobe signal detected upon rising edge of the second clock; And And a fourth latch for latching the fourth data by the fourth data strobe signal detected at the falling edge of the second clock. The method of claim 1, The light driver unit, A first write driver transmitting an output of the first latch to a local input / output line according to the first bank write enable signal; A second write driver configured to transmit an output of the second latch to a local input / output line according to the second bank write enable signal; A third write driver configured to transmit an output of the third latch to a local input / output line according to the third bank write enable signal; And And a fourth write driver configured to transmit an output of the fourth latch to a local input / output line by the fourth bank write enable signal.