KR20030002167A - Circuit for generation column select signal - Google Patents

Abstract

PURPOSE: A column selection signal generation circuit is provided to secure a write recovery time by outputting a width of a column selection signal only when a final data before an auto precharge is written, thereby improving tDPL characteristics. CONSTITUTION: A column selection signal generation circuit includes a first logical operator(OR1) for implementing an OR operation by receiving a first clock(YCLK1) and a second clock(YCLK2), a self pulse generator for generating a self pulse having a first width(t1) by receiving a signal of the first logical operator(OR1), a pulse width expander for outputting t1+t2 by extending a column selection signal(YS) by a second width(t2) only when the final data before the precharge is written when a last data recognition, i.e., a burst end agreement, signal(WAP) is a high level during a burst write operation, a first inverter(IN1) for outputting by receiving a signal of the pulse width extender and a column selection decoder for outputting a plurality of column selection signals(YS0-YSn) by receiving the signal of the first inverter(IN1) and the address signal(Y<0:n>) by receiving the signal of the pulse width expander.

Description

Circuit selection signal generation circuit {Circuit for generation column select signal}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit, and more particularly, to a column select signal generation circuit capable of compensating for a last data-in to precharge before a precharge in a memory circuit.

A conventional memory circuit will be described with reference to the accompanying drawings.

1 is an array circuit diagram of a general memory cell.

FIG. 2 is an operation waveform diagram in the conventional light mode, and FIG. 3 is an operation waveform diagram in the write mode for performing conventional auto precharge.

1 is a circuit diagram of a memory cell array of a general DRAM, in which a memory cell transistor and a capacitor are included, a word line connected to a gate of a memory cell transistor, and a column selection for switching data transmission of an IO line according to a column selection signal. A first bit line B / L (T) and a second bit line B / L (B) connected to a switching unit, a drain of the memory cell transistor, and one IO line, respectively, and first and second bit lines And a sense amplifier S / A that is connected between and senses data stored in the memory cell.

In the case of DRAM, the operation of the write function among the read and write functions, which are main operations, as shown in FIGS. 1 and 2, the word line is turned on and data of the memory cell is transferred through the memory cell transistor. The charge line is loaded on the bit line and then the bit line sense amplifier is operated to sense the bit line at the ground voltage VSS or the supply voltage VDD level.

After the write command, external data enters the memory array through the IO line, is transferred from the IO line to the bit line through the selected column select transistor, and is accumulated in the capacitor through the memory cell transistor.

The word line is then turned off by the precharge function, whereby the memory cell transistor is turned off and the data of the memory cell is stored in the memory cell node, and the bit line is precharged. At this time, the precharge is mainly at the VDD / 2 level.

The time to perform the precharge function after the write command depends entirely on the time of restoring the data to the memory cell after the write command. The longer this time, the tDPL (Last Data-in to Pre-charge) Lengthens the product properties.

The tDPL parameter is sensitive to the contact resistance during the memory cell process in addition to the circuit timing margin. As the design rule becomes smaller, the tDPL parameter becomes one of the main causes of yield loss and yield loss.

In FIG. 2, among the functions of the DRAM in relation to the tDPL, there is a function called write with Auto precharge, which is a function of automatically precharging after writing only with a write command, which is a burst. It is a built-in function in the chip that writes and changes the columns in sequence, and then turns off the word line (W / L) internally after writing the last column. A separate precharge command is required from the outside. It is not there.

FIG. 3 is an operation waveform showing auto precharge after writing, and shows that the column selection signal is always output with the same width.

The conventional memory circuit as described above has the following problems.

The time to perform the precharge function after the write command depends entirely on the time of restoring the data to the memory cell after the write command. Since this time is difficult to adjust, tDPL (Last Data-in to Pre-) charge) (light recovery time) is prolonged, resulting in deterioration of product characteristics.

The present invention has been made to solve the above-mentioned problems. In particular, since the pulse width of the column selection signal is extended and output only during the last data write before auto precharge, the tDPL (Last Data-In to Pre-charge) characteristic It is an object of the present invention to provide a column select signal generating circuit which can improve the (light recovery time).

1 is an array circuit diagram of a typical memory cell

2 is an operation waveform diagram of a conventional light mode.

3 is an operation waveform diagram in a write mode for performing a conventional auto precharge;

4 is a configuration diagram of a column selection signal generating circuit according to an embodiment of the present invention.

5 is an operation waveform diagram in a light mode for performing auto precharge according to an embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

41: self pulse generator 42: pulse width expander

43: column decoder

The column selection signal generating circuit of the present invention for achieving the above object includes a first logical operator OR1 for receiving and combining the first clock YCLK1 and the second clock YCLK2, and the first logical operator OR1. A self-pulse generator for generating a self pulse having a first width t1 in response to a signal of &lt; RTI ID = 0.0 &gt;, < / RTI > and last data recognition (burst end agreement) during a burst write operation receiving the signal of the self pulse generator. A pulse width expander which extends the last column select signal YS before the word line auto precharge by the second width t2 and outputs t1 + t2 only when the signal WAP is at the "high" level; A first inverter IN1 that receives and outputs the signal of the pulse width expander, and receives a signal of the first inverter IN1 and a column address signal Ya <0: n> after receiving the signal of the pulse width expander And a column select decoder for outputting selection signals YS0 to YSn. The features.

The column selection signal generation circuit of the present invention will be described with reference to the accompanying drawings.

4 is a configuration diagram of a column selection signal generation circuit according to an exemplary embodiment of the present invention, and FIG. 5 is an operation waveform diagram of a light mode in which auto precharge is performed according to an exemplary embodiment of the present invention.

The present invention provides a memory product, in particular a product that requires a write recovery time and supports a write with auto precharge function, wherein the column selection circuit is a self-generated pulse. It is used in the field of memory circuit which uses generatec pulse method and is advantageous for synchronous high speed products.

The operation of the conventional column selection circuit is self-generated due to the clock cycle time (tCK) and column address access time (tAA) during burst operation (e.g., burst length is 4). It took the form of a pulse generator.

This pulse width must be kept at the minimum width necessary to perform reads or writes, so that the structure is suitable for high speed.

At this time, in terms of tDPL (Last Data-In to Precharge), a large width of column selection YS is advantageous in terms of securing a write recovery time.

According to the present invention, a circuit for extending only the last YS width by using a "WAP" signal that recognizes the last data is added.

As shown in FIG. 4, the column selection signal generating circuit of the present invention having such a function includes a first logic operator OR1 that receives and combines the first clock YCLK1 and the second clock YCLK2, and the first logic operator OR1. A self pulse generator 41 receiving a signal of the logic operator OR1 and generating a self pulse, and a signal of the last data (burst end recognition) signal during the burst write operation and the signal of the self pulse generator 41 ( Pulse width expander 42 for inverting the width of the last column selection (YS) signal before auto precharge only when the WAP) outputs a " high " level, and inverting the signal of the pulse width expander 42; A column select decoder (y-dec) unit 43 which receives a first inverter IN1, a signal of the first inverter, and a column address signal Ya <0: n>, and outputs column select signals YS0 to YSn. ).

The self pulse generator 41 receives the signal of the first logical operator OR1 and inverts and outputs the signals of the second inverter IN2 and the signals of the first logical operator OR1 and the second inverter IN2. The second logical operator NAND, which is logically inverted, and the third inverter IN3 that receives and outputs a signal from the second logical operator NAND.

As described above, the self pulse generator 41 is output with a pulse width equal to the width "t1" when one of the first and second clocks YCLK1 and YCLK2 represents a "high" pulse.

In addition, the pulse width expander 42 includes a third logic operator OR2 that logically combines the output signal YAEi and the WAP signal of the self pulse generator 41, the output signal YAEi of the self pulse generator 41, and And a fourth logical operator NOR that inverts and then inverts the signal of the third logical operator OR2.

The pulse width expander 42 extends t1 by the pulse width of t2 only when the WAP outputs a "high" signal as shown in FIG.

As described above, the column selection signal YS3 determined by the width of t1 + t2 is determined by the output of the pulse width expander 41 that receives the WAP signal of “high” which recognizes and outputs the last data by the burst write operation. Output

That is, only the column select signal (e.g., YS3) extends the width by t2 when the burst end agreement signal (WAP) is at the "high" level before starting the internal auto precharge operation (t1 + t2). And print it out.

As described above, according to the present invention, in the write with Auto Precharge function associated with tDPL, the self-generated column selection circuit performs the last write function during the column burst write operation. The pulse width was differentiated only at the time of the last data write, i.e., the width was larger than that at the time of writing except the read or the last data write to improve the tDPL characteristic.

Improving the tDPL characteristic in the above means that the memory cell is sufficiently charged by maintaining a long time that the write data of the IO line is conducted with the transistor of the memory cell through the bit line.

The column selection signal generation circuit of the present invention as described above has the following effects.

By extending the width of the column select signal only when writing the last data immediately before the auto precharge, the write recovery time can be ensured to improve the tDPL characteristic.

In other words, it is possible to maintain a long time that the write data of the IO line is connected to the memory cell transistor through the bit line, thereby ensuring sufficient time for the memory cell to be sufficiently charged.

Claims (3)

A first logical operator OR1 that receives and logically combines the first clock YCLK1 and the second clock YCLK2, A self pulse generator for generating a self pulse having a first width t1 in response to the signal of the first logical operator OR1; When the last data recognition (burst end agreement) signal (WAP) is at the "high" level when the burst write operation is received by the self-pulse generator signal, only when the last data before the auto precharge is written. A pulse width expander for extending the column selection YS signal by a second width t2 and outputting t1 + t2; A first inverter IN1 receiving and outputting the signal of the pulse width expander; And a column select decoder unit receiving the signal of the pulse width expander and receiving the signal of the first inverter IN1 and the column address signal Ya <0: n> and outputting column selection signals YS0 to YSn. A column selection signal generating circuit, characterized in that. The method of claim 1, The self pulse generator includes a second inverter IN2 receiving the signal of the first logical operator OR1, A second logical operator NAND for performing an AND operation on the signals of the first logical operator OR1 and the second inverter IN2, and inverting the signals; And a third inverter (IN3) for receiving and outputting the signal of the second logical operator (NAND). The method of claim 1, The pulse width expander includes: a third logic operator OR2 for ORing the output signal YAEi and the WAP signal of the self pulse generator; And a fourth logic operator (NOR) for inverting and then inverting the output signal (YAEi) of the self-pulse generator and the signal of the third logic operator (OR2).