KR100295663B1 - Semiconductor memory apparatus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In the related art, an area is increased by attaching a static RAM cache to a memory cell array to implement a hidden word line precharge. Accordingly, the present invention provides a memory cell array unit in which data is read or written; A plurality of sense amplifier array units enabled by a first sense amplifier enable signal and configured to sense data of the memory cell array unit; A static RAM cache unit configured to enable an idle sense amplifier array unit designated by a mode register among the plurality of sense amplifier array units according to a second sense amplifier enable signal to temporarily store accessed data of the memory cell array unit; Sense amplifier driver for outputting the first and second sense amplifier enable signal for enabling the sense amplifier array and the static RAM cache unit to precharge the word line during the data read operation of the memory without increasing the area Implemented a hidden precharge feature to reduce the low operating cycle of memory.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, by using a sense amplifier without access by a memory controller for a long time, the word line can be precharged during a memory read operation, thereby reducing memory malfunction cycles without increasing the area. The present invention relates to a semiconductor memory device.

In general, semiconductor devices are divided into two parts, a memory device and a logic device. As the semiconductor devices develop, the two devices have developed in different directions.

In other words, memory devices have been developed toward higher integration, while logic devices have been developed at higher speeds.

As a result, the speed difference between the memory device and the logic device is widening now, which is an important obstacle to improving the performance of the entire system.

FIG. 1 is a block diagram showing a configuration of a general semiconductor memory device. As shown therein, a chip including a logic device 100 operating at a high speed and a dynamic memory device 102a, 102b and 103a, 103b operating slowly. The high speed static ram cache 101 is inserted in between to store the information frequently used in the logic device 100 in the static ram cache 101 to improve the performance of the system.

Recently, in order to reduce the cost of board production and improve the performance of semiconductor process technology, the one-chip of a system consisting of the logic device 100, the memory devices 102a, 102b, and 103a, 103b has been studied. In this case, the static ram cache 202 operating at high speed as shown in FIG. 2 is also implemented in the chip 200 together with the slow dynamic memories 203a and 203b.

3 is a block diagram showing an embodiment of a conventional semiconductor memory device using a static RAM cache, and includes a plurality of sense amplifier arrays 11 to 14 for sensing data as shown therein; A plurality of memory cell array sections 21 to 23 through which data is read or written; The static ram cache array unit 30 temporarily stores data, and the operation of the conventional apparatus configured as described above will be described.

First, the memory device is a dynamic memory, and the operation of the memory device is divided into a row operation and a column operation. In the row operation, an external low address signal is applied to the memory cell array units 21 to 23 so that the memory cell array unit 21 is operated. The word line of ˜23) is opened.

On the other hand, when the external column address signal is input, the column selector (not shown) selects a bit line corresponding thereto and reads or writes data of the selected bit line to the data input / output line.

In this case, since the low operation cycle time in the dynamic memory is much longer than the column operation cycle time, the low operation cycle time is reduced by using the static RAM cache (CACHE).

First, when a low address signal is input to the memory, the low address signal is decoded and one word line is opened accordingly. At this time, data in a cell (not shown) connected to the word line is slightly opened by charge coupling. Then, the corresponding sense amplifiers SA of the sense amplifier array units 11 to 14 operate to spread the bit lines.

At this time, the switch of the column line (COLUMN LINE) is opened so that the data of the bit line is transferred to the corresponding static RAM cache (CACHE) of the static RAM cache unit 30. Then, the open word line is closed again and the bit line is freed. I can charge it.

Here, since the data is read from the static RAM cache, the open word line can be precharged while the data is read. In this way, the pre-charge of the word line during the memory read operation is hidden. It is called.

However, the conventional apparatus operating as described above has a problem in that an area is increased by attaching a static ram cache to a memory cell array separately to implement a hidden word line precharge.

Accordingly, the present invention devised in view of the above problems uses the same structure of the bit line sense amplifier and the static RAM cache so that the word is read during the memory read operation using the sense amplifier which is not accessed by the memory controller for a considerable time. It is an object of the present invention to provide a semiconductor memory device capable of precharging lines so as to reduce memory malfunction cycles without increasing the area.

1 is a block diagram showing a configuration of an embodiment of a general semiconductor memory device.

Fig. 2 is a block diagram showing the configuration of Fig. 1 in a single chip.

3 is a block diagram showing the configuration of an embodiment of a semiconductor memory device using a conventional static ram cache;

Fig. 4 is a block diagram showing the configuration of one embodiment of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram showing the configuration of a sense amplifier driver in FIG. 4; FIG.

***** Description of the symbols for the main parts of the drawings *****

11-14: Sense amplifier array part 21-24: Memory cell array part

100: Idle sense amplifier array part

The present invention for achieving the above object is a memory cell array unit in which data is read or written; A plurality of sense amplifier array units enabled by a first sense amplifier enable signal and configured to sense data of the memory cell array unit; A static RAM cache unit configured to enable an idle sense amplifier array unit designated by a mode register among the plurality of sense amplifier array units according to a second sense amplifier enable signal to temporarily store accessed data of the memory cell array unit; And a sense amplifier driver for outputting first and second sense amplifier enable signals for enabling the sense amplifier array unit and the static ram cache unit.

Hereinafter, operations and effects of the semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a block diagram showing the structure of the semiconductor memory device of the present invention. As shown in FIG. 4, the structure of the semiconductor memory device is substantially the same as the conventional structure, except that one idle sense amplifier array designated in advance by a mode register (not shown) is shown. It is different that the 100 replaces the static ram cache unit, and this operation of the present invention will be described.

First, an idle sense amplifier array unit 100 to be used as a static RAM cache unit is designated in advance by a mode register, and when a low address is input from the outside, a word line is opened by decoding it.

Then, after the data in the cell in which the word line is opened is slightly opened by the charge coupling, the sense amplifier SA of the corresponding sense amplifier array parts 11 to 14 is operated by the sense amplifier driver (not shown). When the bit line is opened to some extent, the column line switch is opened so that the corresponding idle sense amplifier (ISA) of the idle sense amplifier array unit 100 is designated so that the data of the bit line is used as the static RAM cache (CACHE) by the mode register. And then open wordlines are closed again and the bitlines can be precharged.

Thereafter, data is read from the idle sense amplifier (ISA). During the data read operation, an open word line can be precharged, and another word is read immediately after reading all data from the idle sense amplifier (ISA). You can open the line.

Therefore, since the word line precharge cycle can overlap the read operation cycle of the memory, the low cycle of the existing memory can be reduced by the word line precharge cycle.

When the data of the bit line is written to the idle sense amplifier (ISA), since the transistor size of the sense amplifier (SA) to write data is the same as that of the written idle sense amplifier (ISA), the data is transferred from the idle sense amplifier (ISA) to the bit line. It can be written as, but to remove this, the sense amplifier driver (not shown) is configured unlike the prior art.

In this case, as illustrated in FIG. 5, the sense amplifier driver (not shown) includes a first yen at a drain of the first PMOS transistor PM1 to which the power supply voltage VDD is applied to the source and the SP2b signal is applied to the gate. A first PMOS transistor connected to a common connection point of a drain and a gate of the MOS transistor NM1, a power supply voltage VDD is applied to a source, and an SP1b signal is applied to a gate of the first NMOS transistor NM1. A drain of the first PMMOS transistor PM1 is connected to a drain of the fourth NMOS transistor NM4 to which a VBLP signal is applied to a gate thereof, and the fourth NMOS transistor NM4 is connected to the drain of the first PMOS transistor PM1. Is connected to the source of the third NMOS transistor NM3 to which the VBLP signal is applied to the gate, and the VBLP signal is applied to the gate of the third NMOS transistor NM3 and the drain is applied to the first P. A second connected to the MOS transistor PM1 A drain of the MOS transistor NM2 is connected, and an SN signal is applied to the gate of the third NMOS transistor NM3, and a drain of the fifth NMOS transistor NM5 having the source grounded is connected, When operating with normal sense amplifier (SA), it operates with SP1b and SN signals, and when operating with idle sense amplifier (ISA), it operates with SP2b and SN signals and operates idle sense amplifier (ISA) with VDD-VTN to VDD. Data can be easily written from a functioning sense amplifier (SA).

As described in detail above, the present invention designates an idle sense amplifier and a busy sense amplifier in a mode register, and uses the idle sense amplifier as a static RAM cache to implement a hidden precharge function without increasing the area, thereby performing a low operation cycle of a memory. There is an effect to reduce.

Claims (2)

A memory cell array unit in which data is read or written; A plurality of sense amplifier array units enabled by a first sense amplifier enable signal and configured to sense data of the memory cell array unit; A static RAM cache unit configured to enable an idle sense amplifier array unit designated by a mode register among the plurality of sense amplifier array units according to a second sense amplifier enable signal to temporarily store accessed data of the memory cell array unit; And a sense amplifier driver for outputting first and second sense amplifier enable signals for enabling the sense amplifier array unit and the static ram cache unit. The method of claim 1, wherein the sense amplifier driver is connected to a common connection point of the drain and the gate of the first NMOS transistor to the drain of the first PMOS transistor, the power supply voltage is applied to the source and the SP2b signal is applied to the gate, A drain of the first PMOS transistor to which the power voltage is applied to the source of the first NMOS transistor and the SP1b signal is applied to the gate, and a VBLP signal is applied to the gate of the drain of the first PMOS transistor; A fourth NMOS transistor is connected to the drain of the fourth NMOS transistor, a source of the third NMOS transistor to which the VBLP signal is applied to the gate is connected, and a VBLP signal is gated to the drain of the third NMOS transistor. Is connected to the drain of the second NMOS transistor, the drain of which is connected to the first PMOS transistor, and the small portion of the third NMOS transistor. The semiconductor memory device, characterized in that the signal SN is applied to the gate is configured with a source connected to the drain of the fifth NMOS transistor to ground.