KR20030002153A - Circuit for cutting fuse - Google Patents

Abstract

PURPOSE: A fuse cutting circuit is provided to prevent an increase of standby current by using a precharge transistor, a latch transistor, and an MRSB signal to remove a current path after a fuse cutting process. CONSTITUTION: A precharge transistor(PM31) receives a signal(MRSB) and transfers a voltage of Vperi to a node of A. The first switching transistor(NM31) is formed between the node of A and a ground voltage terminal in order to receive a signal(FSS) and determine electric potential of the node of A("A") according to a cutting state of a fuse. The fuse is used for controlling an operation to transfer a signal to the node of A("A") through the first switching transistor(NM31). The first and the second inverters(IN31,IN32) delay the signal of the node of A and output the delayed signal to a final output terminal(FEB). A latch transistor(PM32) is used for receiving an output signal of the first inverter(IN31) and latching a precharge level. The second switching transistor(NM32) is used for receiving an output signal of the first inverter(IN31) and maintaining the electric potential transferred to the node of A.

Description

Fuse cutting circuit {CIRCUIT FOR CUTTING FUSE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor fuse cutting circuit, and more particularly, to a fuse cutting circuit which can be applied to a low power product by preventing an increase in standby current after repair.

Referring to the accompanying drawings, a conventional fuse cutting circuit will be described.

1 is a block diagram of a fuse cutting circuit according to a first method, and FIG. 2 is a block diagram of a fuse cutting circuit according to a second method.

As shown in FIG. 1, the unit fuse cutting circuit according to the first method includes a fuse controlling the transfer of the Vperi signal to the 'B' node, and a 'B' node and a ground voltage (Vss) terminal in turn. First and second transistors NM1 and FS (Fuse Set Signal) signals operated to receive a supply voltage, and third and fourth NMOS transistors NM2 and NM3 operated to receive a voltage and a potential of the 'B' node. First and second inverters IN1 and IN2 connected in series to delay output to a fuse enable bar (FEB) and output signals of the first inverter and the second and second to maintain the potential of the 'B' node. It consisted of MOS transistor NM2.

The conventional unit fuse cutting circuit according to the second method includes a third inverter IN3 and first and second transfer gates in addition to the conventional fuse cutting circuit according to the first method.

At this time, the third inverter IN3 receives the address signal, and the first transfer gate receives the signal of the second inverter IN2 into the PMOS and the signal of the first inverter IN1 into the NMOS to receive the address signal. Output to the final output stage.

The second transfer gate receives the signal of the first inverter IN1 to the PMOS and the signal of the second inverter IN2 to the NMOS to output the signal output through the third inverter IN3 to the final output terminal. do.

In the conventional fuse cutting circuit as described above, since the FSS signal is "low" level in the initial state and the "B" node is precharged to the "high" level, the "high" signal is output to the final output terminal.

Thereafter, after the MRS (Mode Register Set), the FSS signal is input in the form of a "high" pulse. At this time, the 'B' node has a collision between the Vperi voltage and the ground voltage through the fuse.

At this time, a through current occurs and the potential of the 'B' node is changed according to the cutting state of the fuse.

First, when the fuse is cut, the 'B' node is latched by the second N-MOS transistor NM2 to indicate a "low" level, and a "low" level signal is output to the final output terminal FEB.

Next, when the fuse is not cut and the FSS signal is at the "low" level, the 'B' node maintains the Vperi voltage level through the fuse, so the final output stage (FEB) maintains the "high" level signal.

In the conventional fuse cutting circuit, a current path may be formed when the resistance component is maintained by the residue of the fuse even after the fuse is cut, which may affect the standby current.

For example, assuming that the current after repair increases about 10 mA per unit fuse-cutting circuit, the standby current increases up to 1.2 mA with 128 unit fuse-cutting circuits for 128M SDRAM (Synchronous DRAM). .

This accounts for a large proportion of the standby current spec (2mA), which is fatal for products requiring low power.

Next, the fuse cutting circuit according to the second method is similar to the operation of the first method, but determines whether an address transmitted when cutting the fuse is inverted. The circuit receives a single address and cuts it if the address is "low" and leaves it uncut if it is "high" so that the signal at the final output (HIT) is always "high" at repair.

The conventional fuse cutting circuit as described above has the following problems.

Even after cutting the fuse, if a resistance component is maintained due to the residue of the fuse, a current path may be formed, which may affect the standby current, which is a fatal disadvantage in products requiring low power.

The present invention has been made to solve the above problems, and in particular, it is an object of the present invention to provide a fuse cutting circuit that can be applied to low-power products to solve the problem of increasing the standby current after repair.

1 is a block diagram of a unit fuse cutting circuit according to a first method

2 is a configuration diagram of a unit fuse cutting circuit according to a second method.

3 is a configuration diagram of a unit fuse cutting circuit according to a first embodiment of the present invention.

4 is a configuration diagram of a unit fuse cutting circuit according to a second exemplary embodiment of the present invention.

5 is an operation timing diagram of FIG. 3.

In order to achieve the above object, the fuse cutting circuit of the present invention includes a precharge transistor configured to receive an inverted signal of a mode register set (MRS) and precharge one node, and between the one node and the ground voltage terminal. A first switching transistor, a fuse configured between the one node and the first switching transistor to determine the potential of the one node according to whether to cut the first switching transistor, and a first and a first series configured to delay the potential of the one node; A two-inverter, a latch transistor that receives a signal from the first inverter and performs a precharge level latch operation on the one node, and receives a signal of the first inverter to maintain the potential of the one node when the fuse is cut. The second switching transistor is operated, and the address and the unit fuse are 1: 1.

Hereinafter, the fuse cutting circuit of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram of a unit fuse cutting circuit according to a first embodiment of the present invention, FIG. 4 is a configuration diagram of a unit fuse cutting circuit according to a second embodiment of the present invention, and FIG. 5 is an operation timing diagram of FIG. .

According to the present invention, the fuse is not completely cut by the fuse residue after the repair (ie, after the fuse cutting) in a fuse repair scheme in which the address and the unit fuse cutting circuits have a 1: 1 matching. The present invention relates to a configuration of a unit fuse cutting circuit which prevents malfunction when a bridge component of a sub-micron unit exists and performs stable operation without increasing a standby current.

First, the unit fuse cutting circuit according to the first exemplary embodiment of the present invention further includes a precharge transistor PM31, a latch transistor PM32 for the precharge level latch, and an MRSB signal as shown in FIG. The current path is eliminated after the fuse is cut to prevent an increase in the standby current. The configuration is as follows.

As shown in FIG. 3, there is a precharge transistor PM31 for receiving the MRSB signal and transferring the Vperi voltage to the 'A' node, and receiving the FSS signal and determining the potential of the 'A' node according to whether the fuse is cut. There is a first switching transistor NM31 configured between the node and the ground voltage VSS terminal, and a fuse for controlling signal transmission to the node A through the first switching transistor NM31. 'There are first and second inverters IN31 and IN32 configured in series to delay the signal of the node to the final output terminal FEB, and the precharge level latch receives the output signal of the first inverter IN31. There is a latch transistor (PM32) for the first, and is configured between the 'A' node and the ground voltage (VSS) terminal to receive the output signal of the first inverter (IN31) and to maintain the potential delivered to the 'A' node There is a two switching transistor NM32.

The precharge transistor PM31 and the latch transistor PM32 are configured as PMOS transistors, and the first and second switching transistors NM31 and NM32 are configured as NMOS transistors, respectively.

The MRSB is an inverting signal of a mode register set, and the fuse set signal (FSS) is a reset signal at power-up and MRS (mode register set), and the fuse enable function is performed. Bar) signal indicates whether the fuse is cut.

Next, the unit fuse cutting circuit according to the second embodiment of the present invention further includes a third inverter IN33 and first and second transfer gates in the configuration of the first embodiment of the present invention, as shown in FIG. It outputs 'HIT' signal.

At this time, the third inverter IN33 receives the address signal, the first transfer gate receives the signal of the second inverter IN32 into the PMOS, the signal of the first inverter IN31 into the NMOS, and the third inverter. The signal output through IN33 is output to the final output terminal.

The second transfer gate receives the signal of the first inverter IN31 into the PMOS, receives the signal of the second inverter IN32 into the NMOS, and outputs an address signal to the final output terminal HITM.

Next, the operation of the fuse cutting circuit according to the first embodiment of the present invention having the above configuration will be described.

In the initial state as shown in Figs. 3 and 5, the 'A' node is precharged to the "high" level by the "low" pulse signal of the MRSB.

At this time, the MRSB is a simple inverter output of an internal signal indicating a mode register set.

Thereafter, after delaying for a predetermined time, the FSS signal is inputted as a "high" pulse. At this time, current fighting occurs in the 'A' node.

At this time, the FSS is a reset signal during power-up and MRS (Mode Register Set).

Next, the output signal of the final output stage before and after the fuse is cut will be described.

First, before the fuse is cut, the potential of the 'A' node is brought to the "low" level and latched by the second switching transistor NM32.

In this case, the "low" level is output to the final output terminal FEB of the fuse cutting circuit, indicating that the fuse is not cut.

Next, when the fuse is cut, even when the FSS is enabled with the "high" pulse as shown in FIG. 5, the 'A' node maintains the "high" level without a current collision, and the "high" as the final output terminal (FEB). A level signal is output to indicate that the fuse has been cut.

Such a circuit accepts one address to be 1: 1 matched with the address and cuts when the address is "Low", and maintains the uncut state when the address is "high".

As described above, the unit fuse cutting method is improved to reduce the current penetrating when current collision occurs in the 'A' node, and to prevent the standby current from increasing by eliminating the current path even after the fuse cutting.

The unit fuse cutting circuits as described above are gathered by the number of addresses to form a fuse set, and the fuse set is used for a repair circuit. It is equal to or smaller than the Fuse layout pitch.

In the above, when the address and the unit fuse cutting circuit match 1: 1, a delay time of less than one clock is provided between the MRSB and the FSS to reduce the direct current.

The fuse cutting circuit according to the present invention as described above has the following effects.

The standby current is prevented from increasing after the fuse is cut, which is useful for low power memory devices.

Claims (4)

A precharge transistor configured to receive an inverted signal of a mode register set (MRS) and to precharge one node; A first switching transistor configured between the one node and a ground voltage terminal; A fuse configured between the one node and the first switching transistor to determine the potential of the one node according to whether to cut or not; First and second inverters configured in series to delay output the potential of the one node; A latch transistor configured to receive a signal from the first inverter and perform a precharge level latch operation on the one node; And a second switching transistor operated by receiving a signal from the first inverter to maintain the potential of the one node when the fuse is cut, wherein an address and a unit fuse are matched 1: 1. The method of claim 1, The fuse cutting circuit may include a first transfer gate configured to input the first inverter signal to NMOS and to input the second inverter signal to PMOS to determine whether to transfer an inverted signal; And a second transfer gate configured to input the first inverter signal to the PMOS and the second inverter signal to the NMOS to determine whether to transfer the address signal. The method of claim 1, And the precharge transistor and the latch transistor comprise a PMOS transistor. The method of claim 1, And the first and second switching transistors are configured as NMOS transistors.