KR20030001915A - Field transistor for protecting electrostatics - Google Patents
Field transistor for protecting electrostatics Download PDFInfo
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- KR20030001915A KR20030001915A KR1020010037784A KR20010037784A KR20030001915A KR 20030001915 A KR20030001915 A KR 20030001915A KR 1020010037784 A KR1020010037784 A KR 1020010037784A KR 20010037784 A KR20010037784 A KR 20010037784A KR 20030001915 A KR20030001915 A KR 20030001915A
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- 238000002955 isolation Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
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- 239000012535 impurity Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 4
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000005611 electricity Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Non-Volatile Memory (AREA)
Abstract
Description
본 발명은 정전기 보호용 필드 트랜지스터에 관한 것으로, 특히, 적층 구조의 게이트 전극을 갖는 플래쉬 메모리 소자에 구비되는 정전기 보호용 필드 트랜지스터에 관한 것이다.The present invention relates to a field transistor for electrostatic protection, and more particularly, to a field transistor for electrostatic protection provided in a flash memory device having a gate electrode of a laminated structure.
일반적으로 디램(DRAM) 또는 에스램(SRAM)과 같은 메모리 소자는 프로그램 및 소거 동작시 전원전압을 사용하는 반면, 플래쉬 메모리 소자는 포지티브(Positive) 고전압 또는 네가티브(Negative) 고전압을 사용한다.In general, memory devices such as DRAM or SRAM use a power supply voltage during program and erase operations, whereas flash memory devices use a positive high voltage or a negative high voltage.
그러므로 플래쉬 메모리 소자에는 고전압을 공급하기 위한 고전압 발생 회로 및 고전압을 전달할 수 있도록 높은 항복전압을 갖는 트랜지스터가 구비된다.Therefore, the flash memory device is provided with a high voltage generating circuit for supplying a high voltage and a transistor having a high breakdown voltage for delivering a high voltage.
그러나 정전기 방전 회로(Electrostatic discharge circuit)는 전하(Charge)의 방전이 용이하도록 하기 위해 낮은 항복전압을 갖는 트랜지스터를 필요로 하기 때문에 플래쉬 메모리 소자의 정전기 보호 회로는 디램이나 에스램의 정전기 방전 회로보다 취약한 특성을 갖게 된다.However, since the electrostatic discharge circuit requires a transistor having a low breakdown voltage to facilitate the discharge of the charge, the electrostatic protection circuit of the flash memory device is more vulnerable than the electrostatic discharge circuit of the DRAM or SRAM. Will have characteristics.
그러면 종래의 정전기 방전 회로에 사용되는 정전기 보호용 필드 트랜지스터의 구조를 도 1을 통해 살펴보기로 한다.Then, the structure of the electrostatic protection field transistor used in the conventional electrostatic discharge circuit will be described with reference to FIG.
종래의 정전기 보호용 트랜지스터는 반도체 기판(1)의 P웰(2)에 형성되며, P웰(2)의 반도체 기판(1)에 형성된 트렌치 구조의 소자분리막(3)과, 상기 소자분리막(3) 양측부의 반도체 기판(1)에 N+형의 불순물 이온이 주입된 소오스 및 드레인(4 및 5)으로 이루어진다.The conventional static electricity protection transistor is formed in the P well 2 of the semiconductor substrate 1, the device isolation film 3 of the trench structure formed in the semiconductor substrate 1 of the P well 2, and the device isolation film 3 It consists of the source and drain 4 and 5 in which the N + type impurity ion was inject | poured into the semiconductor substrate 1 of both sides.
상기 필드 트랜지스터는 정상 동작시 접합 항복이 방지되도록 소오스 및 드레인(4 및 5)이 DDD(Double Doped Drain) 구조로 형성되며, 상기 소오스(4)는 전원전압(Vcc) 또는 접지전압(Vss)에 연결되고, 상기 드레인(5)은 입출력 패드에 연결된다.In the field transistor, a source and a drain 4 and 5 are formed in a double doped drain (DDD) structure to prevent junction breakdown during normal operation, and the source 4 is connected to a power supply voltage Vcc or a ground voltage Vss. The drain 5 is connected to an input / output pad.
그런데 플래쉬 메모리 소자의 입출력 패드(Input/Output pad)에 발생되는 정전기를 방전시키기 위한 상기 정전기 보호용 필드 트랜지스터는 접합영역을 통해 많은 양의 전하가 방전될 경우 특정 부위에 전하가 몰려 콘택홀에 형성된 플러그가 용해되는 등 소자의 신뢰성에 영향을 미치는 문제점이 발생된다.However, the electrostatic protection field transistor for discharging static electricity generated in an input / output pad of a flash memory device has a plug formed in a contact hole when a large amount of electric charge is discharged through a junction region, due to the charge being collected at a specific site. Problems affecting the reliability of the device such as dissolution occur.
따라서 본 발명은 소자의 동작시 고전압이 인가되는 드레인은 높은 항복전압을 갖는 DDD 구조로 형성하고, 소오스는 전하의 방전이 용이하도록 일반적인 구조로 형성하므로써 상기한 단점을 해소할 수 있는 정전기 방지용 필드 트랜지스터를 제공하는 데 그 목적이 있다.Therefore, in the present invention, the drain to which the high voltage is applied during operation of the device is formed in a DDD structure having a high breakdown voltage, and the source is formed in a general structure to facilitate discharge of charge. The purpose is to provide.
상기한 목적을 달성하기 위한 본 발명은 N웰 및 P웰이 형성된 반도체 기판과, N웰 및 P웰 계면의 반도체 기판에 형성된 소자분리막과, 소자분리막 일측부의 N웰에 형성된 소오스와, 소자분리막으로부터 소정 거리 이격된 P웰에 형성된 드레인으로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a semiconductor substrate formed with N well and P well, a device isolation film formed on the semiconductor substrate of the N well and P well interface, a source formed in the N well of one side of the device isolation film, the device isolation film Characterized in that the drain formed in the P well spaced from a predetermined distance from.
또한, 상기 소자분리막 및 드레인 간의 반도체 기판 상에 형성된 게이트 전극과, 상기 게이트 전극 및 입출력 패드 간에 접속된 저항을 더 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device may further include a gate electrode formed on the semiconductor substrate between the device isolation layer and the drain, and a resistor connected between the gate electrode and the input / output pad.
상기 드레인은 DDD 구조로 형성되며, 상기 게이트 전극은 금속으로 이루어진 것을 특징으로 한다.The drain has a DDD structure, and the gate electrode is made of metal.
도 1은 종래의 정전기 보호용 트랜지스터를 설명하기 위한 소자의 단면도.1 is a cross-sectional view of an element for explaining a conventional electrostatic protection transistor.
도 2는 본 발명의 제 1 실시예를 설명하기 위한 소자의 단면도.Fig. 2 is a sectional view of a device for explaining the first embodiment of the present invention.
도 3은 본 발명의 제 2 실시예를 설명하기 위한 소자의 단면도.3 is a cross-sectional view of an element for explaining a second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 및 11: 반도체 기판2 및 12a: P웰1 and 11: semiconductor substrates 2 and 12a: P well
3 및 13: 소자분리막4 및 14: 소오스3 and 13: device isolation layers 4 and 14: source
5 및 15: 드레인12b: N웰5 and 15: drain 12b: N well
16: 절연막17: 게이트 전극16: insulating film 17: gate electrode
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2는 본 발명에 따른 정전기 방지용 필드 트랜지스터를 설명하기 위한 소자의 단면도이다.2 is a cross-sectional view of a device for explaining an antistatic field transistor according to the present invention.
본 발명에 따른 정전기 방지용 필드 트랜지스터는 P웰(12a) 및 N웰(12b)이 형성된 반도체 기판(11)에 형성된다.The antistatic field transistor according to the present invention is formed in the semiconductor substrate 11 on which the P well 12a and the N well 12b are formed.
P웰(12a) 및 N웰(12b) 계면의 상기 반도체 기판(11)에 트렌치 구조의 소자분리막(13)이 형성되고, 상기 소자분리막(13) 일측부의 상기 N웰(12b)에는 N+형의 불순물 이온이 주입된 소오스(14)가 형성되며, 상기 소자분리막(13)으로부터 소정 거리 이격된 상기 P웰(12a)에는 N+형의 불순물 이온이 주입된 드레인(15)이 형성된다.A trench isolation device 13 is formed in the semiconductor substrate 11 at the interface between the P well 12a and the N well 12b, and an N + type is formed in the N well 12b at one side of the device isolation film 13. A source 14 into which impurity ions are implanted is formed, and a drain 15 into which N + type impurity ions are implanted is formed in the P well 12a spaced apart from the device isolation layer 13 by a predetermined distance.
상기 소오스(14)는 전원전압(Vcc) 또는 접지전압(Vss)에 연결되고, 상기 드레인(15)은 입출력 패드에 연결된다.The source 14 is connected to a power supply voltage Vcc or a ground voltage Vss, and the drain 15 is connected to an input / output pad.
플래쉬 메모리 소자의 동작시 상기 필드 트랜지스터의 드레인(15)에는 고전압이 인가된다. 그러므로 본 발명은 드레인(15)은 DDD 구조로 형성하여 정상 동작시 접합 항복이 방지되도록 하는 반면, 소오스(14)는 일반적인 형태로 만들어 접합 항복에 유리하도록 하였다.In operation of a flash memory device, a high voltage is applied to the drain 15 of the field transistor. Therefore, in the present invention, the drain 15 is formed in a DDD structure to prevent junction breakdown during normal operation, while the source 14 is made in a general shape to be advantageous in junction breakdown.
상기 필드 트랜지스터는 입출력 패드에 정전기 등으로 인해 고전압이 인가되는 경우 상기 P웰(12a)에 역 바이어스 전압이 인가되어 P웰(12a) 및 N웰(12b)의 계면 부근까지 드레인(15) 공핍영역이 확장된다. 따라서 입출력 패드와 전원전압(Vcc) 사이에 낮은 임피던스를 갖는 경로가 형성되고, 이 경로를 통한 전류의 흐름이 발생되어 정전기로부터 보호된다.In the field transistor, when a high voltage is applied to an input / output pad due to static electricity or the like, a reverse bias voltage is applied to the P well 12a to drain the drain 15 to the vicinity of an interface between the P well 12a and the N well 12b. This is expanded. Therefore, a path having a low impedance is formed between the input / output pad and the power supply voltage Vcc, and a current flows through the path to protect it from static electricity.
또한, 본 발명은 정전기 방전 효과를 향상시키기 위하여 상기 소자분리막(13) 및 드레인(15) 사이의 반도체 기판(11) 상에 도 3과 같이 금속으로 게이트 전극(17)을 형성하고, 입출력 패드와 상기 전극(17)간에 큰 값을 갖는 저항(R)을 연결시킨다. 도면에서 부호 16은 절연막을 지시한다.In addition, in order to improve the electrostatic discharge effect, the present invention forms the gate electrode 17 on the semiconductor substrate 11 between the device isolation layer 13 and the drain 15 as shown in FIG. A resistor R having a large value is connected between the electrodes 17. In the drawing, reference numeral 16 designates an insulating film.
따라서 정상 적인 동작시에는 상기 저항(R)에 의해 상기 게이트 전극(17)에 거의 바이어스 전압이 인가되지 않지만, 상기 입출력 패드에 고전압이 인가되는 경우 상기 게이트 전극(17)에 소정의 전압이 인가되어 상기 소자분리막(13)과 드레인(15) 사이의 반도체 기판(11)에 채널이 형성되기 때문에 드레인(15)이 소오스(14) 쪽의 N웰(12b)과 가까와지고, 이에 따라 펀치쓰루우(Punch through)가 발생되어 소오스(14)를 통한 전류의 흐름이 발생된다.Therefore, in the normal operation, a bias voltage is hardly applied to the gate electrode 17 by the resistor R, but when a high voltage is applied to the input / output pad, a predetermined voltage is applied to the gate electrode 17. Since a channel is formed in the semiconductor substrate 11 between the device isolation film 13 and the drain 15, the drain 15 is brought closer to the N well 12b on the source 14 side. Punch through occurs to generate a current flow through the source 14.
상술한 바와 같이 본 발명은 소자의 동작시 고전압이 인가되는 드레인은 높은 항복전압을 갖도록 DDD 구조로 형성하고, 소오스는 전하의 방전이 용이하도록 일반적인 구조로 형성한다.As described above, in the present invention, a drain to which a high voltage is applied during operation of the device is formed in a DDD structure so as to have a high breakdown voltage, and a source is formed in a general structure to facilitate discharge of charge.
또한, 소자분리막과 드레인 간의 반도체 기판상에 게이트를 형성하고 입출력 패드와 게이트 간에 저항을 연결하므로써 입출력 패드에 고전압이 인가되는 경우채널의 형성에 따른 펀치쓰루우에 의해 전하의 방전이 용이하도록 한다.In addition, since a gate is formed on the semiconductor substrate between the device isolation layer and the drain, and a resistance is connected between the input / output pad and the gate, the discharge of electric charges is facilitated by the punch-through according to the formation of the channel when a high voltage is applied to the input / output pad.
따라서 본 발명을 이용하면 플래쉬 메모리 소자의 정전기 방전 특성을 향상시킬 수 있으며, 이에 따라 소자의 신뢰성이 향상된다.Therefore, using the present invention can improve the electrostatic discharge characteristics of the flash memory device, thereby improving the reliability of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010037784A KR20030001915A (en) | 2001-06-28 | 2001-06-28 | Field transistor for protecting electrostatics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010037784A KR20030001915A (en) | 2001-06-28 | 2001-06-28 | Field transistor for protecting electrostatics |
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| Publication Number | Publication Date |
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| KR20030001915A true KR20030001915A (en) | 2003-01-08 |
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| KR1020010037784A KR20030001915A (en) | 2001-06-28 | 2001-06-28 | Field transistor for protecting electrostatics |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8242565B2 (en) | 2009-04-30 | 2012-08-14 | Hynix Semiconductor Inc. | Electrostatic discharge protection device |
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- 2001-06-28 KR KR1020010037784A patent/KR20030001915A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8242565B2 (en) | 2009-04-30 | 2012-08-14 | Hynix Semiconductor Inc. | Electrostatic discharge protection device |
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