KR20030001217A - Ferroelectric memory device having expanded plate lines and method of fabricating the same - Google Patents

Abstract

PURPOSE: A ferroelectric memory device having an extended plate line and a method for fabricating the same are provided to maximize a contact area between a plate line and an upper electrode and improve an insulating characteristic between the plate line and a main word line. CONSTITUTION: An isolation layer(53) is formed on a semiconductor substrate(51). A plurality of insulated gate electrodes(57) are formed across the isolation layer(53). An active region is divided into one common drain region(61d) and two source regions(61s). A lower interlayer dielectric(74) is deposited on a whole surface of the above structure. A plurality of contact plugs(75) are connected with the source regions(61s). A ferroelectric capacitor(82) is arranged on the whole surface of the above structure. The ferroelectric capacitor(82) includes a lower electrode(77), a ferroelectric layer pattern(79), and an upper electrode(81). An insulating layer pattern(85a) are formed on a gap region between the ferroelectric capacitors(82). A local plate line(87) is formed on the ferroelectric capacitor(82) and the insulating layer pattern(85a). The first and the second upper interlayer dielectric(89,93) are deposited thereon. A main word line(91) is inserted between the first and the second upper interlayer dielectric(89,93). A main plate line(97) is connected with the local plate line(87) through a slit type via hole(95).

Description

Ferroelectric memory device having expanded plate lines and method of fabricating the same

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a ferroelectric memory device having an extended plate line and a method for manufacturing the same.

Among the semiconductor devices, ferroelectric memory devices have a non-volatile characteristic that retains data of the previous state even if power is not supplied. In addition, ferroelectric memory devices have characteristics such as operating at low power supply voltages such as DRAM and SRAM. Therefore, ferroelectric memory devices are in the spotlight as potential candidates that can be widely used in smart cards and the like.

1 to 3 are cross-sectional views illustrating a method of manufacturing a conventional ferroelectric memory device.

Referring to FIG. 1, an isolation region 13 is formed in a predetermined region of a semiconductor substrate 11 to define an active region. A plurality of insulated gate electrodes 15, that is, word lines, are formed across the active region and the device isolation layer 13. Subsequently, impurity ions are implanted into the active region between the gate electrodes 15 to form source / drain regions 17s and 17d. A first lower interlayer insulating film 19 is formed on the entire surface of the resultant source / drain regions 17s and 17d formed thereon. The first lower interlayer insulating layer 19 is patterned to form storage node contact holes exposing the source regions 17s. Next, contact plugs 21 are formed in the storage node contact holes.

Referring to FIG. 2, ferroelectric capacitors 32 two-dimensionally arranged on the front surface of the semiconductor substrate having the contact plugs 21 are formed. Each of the ferroelectric capacitors 32 includes a lower electrode 27, a ferroelectric layer pattern 29, and an upper electrode 31 that are sequentially stacked. Each of the lower electrodes 27 covers the contact plug 21. A first upper interlayer insulating film 33 is formed on the entire surface of the semiconductor substrate having the ferroelectric capacitors 32. Subsequently, a plurality of main word lines 35 are formed on the first upper interlayer insulating layer 33 in parallel with the gate electrodes 15. Each main word line 35 typically controls four word lines 15.

Referring to FIG. 3, a second upper interlayer insulating layer 37 is formed on an entire surface of the semiconductor substrate having the main word lines 35. The second upper interlayer insulating layer 37 and the first upper interlayer insulating layer 33 are patterned to form via holes 39 exposing the upper electrodes 31. In this case, a wet etching process and a dry etching process may be used to reduce the aspect ratio of each via hole 39. In this case, as shown in Fig. 3, the via hole 39 has an inclined upper side wall 39a. However, if the wet etching process is excessively performed, the main word line 35 may be exposed.

Meanwhile, the diameter of the via hole 39 may be increased by another method for reducing the aspect ratio of the via hole 39. However, the spacing s between the via hole 39 and the main word line 35 adjacent thereto gradually decreases as the integration degree of the ferroelectric memory device increases. Therefore, when increasing the diameter of the via hole 39, a precise alignment is required during the photolithography process for forming the via hole 39.

Subsequently, a plurality of plate lines 41 covering the via holes 39 are formed. The plate lines 41 are disposed parallel to the main word lines 35.

As described above, according to the related art, reducing the aspect ratio of the via holes increases the probability that the main word lines are exposed. Accordingly, it is difficult to solve both the contact failure between the upper electrode and the plate line and the electrical short between the plate line and the main word line.

Accordingly, an object of the present invention is to provide a ferroelectric memory device capable of maximizing a contact area between a plate line and an upper electrode, as well as securing insulation characteristics between the plate line and the main word line.

Another object of the present invention is to provide a method of manufacturing a ferroelectric memory device capable of maximizing the contact area between a plate line and an upper electrode, as well as securing insulating properties between the plate line and the main word line. have.

1 to 3 are cross-sectional views illustrating a method of manufacturing a conventional ferroelectric memory device.

4 is a plan view illustrating a cell array region of a ferroelectric memory device according to the present invention.

5 is a perspective view illustrating a ferroelectric memory device according to an embodiment of the present invention.

6 is a perspective view illustrating a ferroelectric memory device according to another embodiment of the present invention.

7 is a perspective view illustrating a ferroelectric memory device according to still another embodiment of the present invention.

8 to 14 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to an embodiment of the present invention, according to II ′ of FIG. 4.

15 to 19 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to another embodiment of the present invention according to II ′ of FIG. 4.

20 to 24 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to still another embodiment of the present invention according to II ′ of FIG. 4.

25 is a plan view illustrating a cell array region of a ferroelectric memory device according to a modification of the present invention.

FIG. 26 is a cross-sectional view illustrating a ferroelectric memory device and a method of manufacturing the same according to a modified example of the present invention according to II-II ′ of FIG. 25.

To achieve the above technical problem, the present invention provides a ferroelectric memory device having an expanded plate line in direct contact with upper electrodes arranged on at least two rows adjacent to each other. This ferroelectric memory device has a lower interlayer insulating film formed on a semiconductor substrate. A plurality of ferroelectric capacitors are two-dimensionally arranged along the row direction and the column direction on the lower interlayer insulating film. The front surface of the semiconductor substrate having the plurality of ferroelectric capacitors is covered by an upper interlayer insulating film. The upper interlayer insulating film includes first and second upper interlayer insulating films that are sequentially stacked. A plurality of plate lines parallel to the column direction are disposed in the upper interlayer insulating film. Each of the plate lines is in direct contact with top surfaces of the ferroelectric capacitors arranged in at least two rows adjacent to each other. As a result, the ferroelectric capacitors arranged on at least two rows adjacent to each other share one plate line. In addition, a plurality of main word lines may be disposed between the first and second upper interlayer insulating layers. The main word lines are parallel to the column direction.

Meanwhile, the plate line may contact the ferroelectric capacitors arranged in at least two adjacent rows and at least one column.

The plate line may be a local plate line covered by the upper interlayer insulating film or a main plate line covering a slit-type via hole penetrating the upper interlayer insulating film. It may be. Alternatively, the plate line may include the local plate line and the main plate line. Each of the slit-shaped via holes is located between the main word lines.

Meanwhile, each of the ferroelectric capacitors includes a bottom electrode, a ferroelectric layer pattern, and a top electrode stacked in sequence. In this case, each of the plate lines is in direct contact with the upper electrodes arranged on at least two rows adjacent to each other. Alternatively, the upper electrodes of the ferroelectric capacitors arranged in at least two adjacent rows may contact a plurality of local plate patterns instead of one local plate line. Thus, each of the plurality of local plate patterns may contact upper electrodes of ferroelectric capacitors disposed in at least two adjacent rows and at least one column. Advantageously, each of said plurality of local plate patterns contacts upper electrodes of ferroelectric capacitors disposed in at least two adjacent rows and at least two columns. In this case, each of the main plate lines is electrically connected to the plurality of local plate patterns through a plurality of via holes. Alternatively, each of the main plate lines may be electrically connected to the plurality of local plate patterns through the slit-shaped via hole. Here, the gap region between the ferroelectric capacitors is preferably filled with a material film having an etch selectivity with respect to the upper interlayer insulating film.

In addition, each of the ferroelectric capacitors may include a lower electrode, a ferroelectric layer pattern, and a common top electrode, which are sequentially stacked. Here, the common upper electrode covers the ferroelectric film patterns arranged on at least two rows adjacent to each other. The gap region between the lower electrodes and the gap region between the ferroelectric layer patterns may be filled with an insulating layer pattern. As a result, the ferroelectric capacitors arranged on at least two rows adjacent to each other share one common upper electrode. The common upper electrode is in direct contact with the plate line.

In addition, each of the ferroelectric capacitors may include a lower electrode, a common ferroelectric layer pattern, and a common upper electrode which are sequentially stacked. Here, the common ferroelectric film pattern covers the lower electrodes arranged on at least two rows adjacent to each other. The common ferroelectric film pattern overlaps the common upper electrode. Accordingly, the common upper electrode is in direct contact with the plate line.

The present invention provides a method of manufacturing a ferroelectric memory device having an expanded plate line in direct contact with the upper electrodes arranged on at least two rows adjacent to each other to achieve the above technical problem. . The method includes forming a lower interlayer insulating film on the semiconductor substrate. A plurality of ferroelectric capacitors are formed two-dimensionally on the lower interlayer insulating film in a row direction and a column direction. An upper interlayer insulating film and a plurality of plate lines disposed in the upper interlayer insulating film are formed on an entire surface of the semiconductor substrate having the ferroelectric capacitors. The plate lines are formed parallel to the column direction. Each of the plate lines is in direct contact with top surfaces of the ferroelectric capacitors arranged on at least two rows adjacent to each other. In addition, the upper interlayer insulating layer may be formed by sequentially stacking first and second upper interlayer insulating layers.

The method of forming the plurality of ferroelectric capacitors includes sequentially forming a lower electrode film, a ferroelectric film, and an upper electrode film on the lower interlayer insulating film, and successively patterning the upper electrode film, the ferroelectric film, and the lower electrode film. Accordingly, each of the ferroelectric capacitors includes a lower electrode, a ferroelectric film pattern, and an upper electrode stacked in sequence. In this case, each of the plate lines is in contact with the upper electrodes arranged on at least two rows adjacent to each other. It is preferable to form an insulating film pattern filling the gap region between the ferroelectric capacitors.

Alternatively, the method of forming the plurality of ferroelectric capacitors includes sequentially forming a lower electrode film and a ferroelectric film on the lower interlayer insulating film. Subsequently, the ferroelectric film and the lower electrode film are successively patterned to form a plurality of lower electrodes arranged in two dimensions along the row direction and the column direction, and a plurality of ferroelectric film patterns stacked on the lower electrodes. An insulating layer pattern is formed to fill the gap region between the ferroelectric layer patterns and the gap region between the lower electrodes. An upper electrode layer is formed on the insulating layer pattern and the ferroelectric layer patterns. The upper electrode layer is patterned to form a common upper electrode covering the ferroelectric layer patterns arranged on at least two adjacent rows. The common upper electrode is in contact with the plate line.

Another method of forming the plurality of ferroelectric capacitors includes forming a plurality of lower electrodes arranged two-dimensionally along the row direction and the column direction on the lower interlayer insulating film. A ferroelectric film and an upper electrode film are sequentially formed on the entire surface of the semiconductor substrate having the lower electrodes. The upper electrode layer and the ferroelectric layer are patterned to form a common ferroelectric layer pattern and a common upper electrode which are sequentially stacked. Here, the common ferroelectric film pattern covers the lower electrodes arranged on at least two rows adjacent to each other. Thus, the common upper electrode is interposed between the plate line and the ferroelectric film pattern. Before forming the ferroelectric film, it is preferable to form a lower insulating film pattern filling the gap region between the lower electrodes.

Meanwhile, the method of forming the upper interlayer insulating film and the plurality of plate lines includes forming a lower plate film on an entire surface of the semiconductor substrate having the plurality of ferroelectric capacitors. The lower plate film is patterned to form local plate lines covering the ferroelectric capacitors arranged on at least two adjacent rows. Alternatively, the lower plate layer may be patterned to form a plurality of local plate patterns covering the ferroelectric capacitors arranged in at least two rows adjacent to each other and two columns adjacent to each other. As a result, the plurality of local plate patterns are formed instead of the local plate line. In this case, the physical stress due to the plurality of local plate patterns is small compared to the physical stress due to the plurality of local plate lines. In particular, in the case where the lower plate film is formed of at least one of an iridium film and an iridium oxide film, physical stresses caused by the plurality of local plate patterns may be affected by physical stresses caused by the plurality of local plate lines. It is significantly reduced in comparison with that. Accordingly, when the local plate patterns are formed instead of the local plate line, the degradation of the ferroelectric properties of the ferroelectric film patterns can be significantly suppressed.

Subsequently, an upper interlayer insulating film is formed on the entire surface of the semiconductor substrate having the local plate line. The upper interlayer insulating layer may be formed by sequentially stacking first and second upper interlayer insulating layers. In addition, before forming the second upper interlayer insulating layer, a plurality of main word lines parallel to the column direction may be formed on the first upper interlayer insulating layer. The second upper interlayer insulating layer and the first upper interlayer insulating layer may be successively patterned to further form slit type via holes parallel to the main word lines. The slit-type via hole penetrates the upper interlayer insulating film between the main word lines to expose the local plate line. A main plate line is formed to cover the slit via hole.

Meanwhile, in the case of forming the plurality of local plate patterns instead of the local plate line, the slit type via hole exposes the plurality of local plate patterns and the lower insulating layer patterns therebetween. Alternatively, instead of the slit type via hole, a plurality of via holes exposing the plurality of local plate patterns may be formed.

Alternatively, the method of forming the upper interlayer insulating film and the plurality of plate lines includes forming an upper interlayer insulating film on an entire surface of the semiconductor substrate having the plurality of ferroelectric capacitors. The upper interlayer insulating layer may be formed by sequentially stacking first and second upper interlayer insulating layers. In this case, main word lines parallel to the column direction may be formed between the first and second upper interlayer insulating layers. The upper interlayer insulating layer is patterned to form slit via holes parallel to the column direction between the main word lines. The slit type via hole exposes top surfaces of the ferroelectric capacitors arranged on at least two rows adjacent to each other. A main plate line is formed to cover the slit via hole.

When each of the ferroelectric capacitors is composed of the lower electrode, the ferroelectric film pattern, and the upper electrode, which are sequentially stacked, the slit type via hole exposes the upper electrodes arranged on at least two adjacent rows. In this case, the insulating film pattern filling the gap region between the ferroelectric capacitors is preferably formed of a material film having an etch selectivity with respect to the upper interlayer insulating film.

In addition, when each of the ferroelectric capacitors includes the common upper electrode, the slit type via hole exposes the common upper electrode.

Furthermore, each of the lower electrodes is electrically connected to a predetermined region of the semiconductor substrate through a storage node contact hole penetrating the lower interlayer insulating layer. Preferably, the upper diameter of the storage node contact hole is larger than the lower diameter thereof. In addition, it is preferable to form a hydrogen barrier film pattern on at least the sidewall of the ferroelectric film pattern or the sidewall of the common ferroelectric film pattern.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

4 is a plan view illustrating a portion of a cell array region of a ferroelectric memory device according to the present invention, and FIGS. 5 to 7 are perspective views illustrating ferroelectric memory devices according to the first to third embodiments of the present invention, respectively. admit.

4 and 5, the device isolation layer 53 is disposed in a predetermined region of the semiconductor substrate 51. The device isolation layer 53 defines a plurality of active regions 53a arranged two-dimensionally. A plurality of insulated gate electrodes 57, that is, a plurality of word lines, are disposed across the active regions 53a and the device isolation layer 53. The gate electrodes 57 are parallel to the row direction (y-axis). Each of the active regions 53a intersects the pair of gate electrodes 57. Accordingly, each active region 53a is divided into three parts. The common drain region 61d is formed in the active region 53a between the pair of gate electrodes 57, and the source regions are formed in the active regions 53a on both sides of the common drain region 61d. 61s) is formed. Thus, cell transistors are formed at points where the gate electrodes 57 and the active regions 53a intersect. As a result, the cell transistors are arranged two-dimensionally along the column direction (x axis) and the row direction (y axis).

The front surface of the semiconductor substrate having the cell transistors is covered by the lower interlayer insulating film 74. A plurality of bit lines 71 crossing the upper portions of the word lines 57 are disposed in the lower interlayer insulating layer 74. Each of the bit lines 71 is electrically connected to the common drain region 61d through a bit line contact hole 71a. The source regions 61s are exposed by the storage node contact holes 75a penetrating the lower interlayer insulating layer 74. The upper sidewall of the storage node contact hole 75a preferably has a sloped profile. The storage node contact holes 75a are respectively filled by the contact plugs 75. As a result, the upper diameter of the contact plug 75 is larger than its lower diameter as shown in FIG.

A plurality of ferroelectric capacitors 82 (CP of FIG. 4) arranged two-dimensionally along the column direction (x axis) and the row direction (y axis) on a front surface of the semiconductor substrate having the contact plugs 75. Is placed. Each of the ferroelectric capacitors 82 includes a lower electrode 77, a ferroelectric film pattern 79, and an upper electrode 81 that are sequentially stacked. The lower electrodes 77 are positioned on the contact plugs 75, respectively. As a result, the lower electrode 77 is electrically connected to the source region 61s through the contact plug 75. The gap region between the ferroelectric capacitors 82 may be filled with the insulating film pattern 85a.

In addition, a hydrogen barrier layer pattern 83a may be interposed between the insulating layer pattern 85a and at least the ferroelectric layer patterns 79. The hydrogen barrier layer pattern 83a may be a titanium oxide layer (TiO ₂ ), an aluminum oxide layer (Al ₂ O ₃ ), a silicon nitride layer (Si ₃ N ₄ ), or a combination thereof. Therefore, hydrogen atoms can be prevented from penetrating into the ferroelectric film pattern 79. When hydrogen atoms are injected into the ferroelectric film pattern 79, the reliability of the ferroelectric film pattern 79 is lowered. For example, when hydrogen atoms are injected into a ferroelectric film such as a PZT (Pb, Zr, TiO ₃ ) film, oxygen atoms in the PZT film and the hydrogen atoms react to generate oxygen vacancy in the PZT film. do. Such oxygen vacancies lower the polarization characteristic of the ferroelectric. As a result, a malfunction of the ferroelectric memory element is caused.

In addition, when the hydrogen atoms are trapped at the interface between the ferroelectric film pattern and the top / bottom electrodes, the energy barrier between them is lowered. Therefore, the leakage current characteristic of the ferroelectric capacitor is reduced. In conclusion, the hydrogen barrier layer pattern 83a improves the characteristics and reliability of the ferroelectric capacitor 82.

A plurality of local plate lines 87 (PL of FIG. 4) are disposed on the ferroelectric capacitors 82 and the insulating layer pattern 85a. The local plate lines 87 correspond to a metal film, a conductive metal oxide layer, a conductive metal nitride layer, or a composite film thereof. For example, the local plate lines 87 may include titanium aluminum nitride (TiAlN), titanium (Ti), titanium nitride (TiN), iridium (Ir), iridium oxide (IrO2), and platinum (Pt). ), A ruthenium film Ru, a ruthenium oxide film RuO2, an aluminum film Al, or a composite film thereof. The local plate lines 87 are arranged parallel to the row direction (y axis). Further, each of the local plate lines 87 covers the ferroelectric capacitors 82 arranged on at least two rows adjacent to each other. As a result, the local plate line 87 is in direct contact with the upper electrodes 81 arranged on at least two rows adjacent to each other. The front surface of the semiconductor substrate having the local plate lines 87 is covered by an upper interlayer insulating film. Here, the upper interlayer insulating layers may include first and second upper interlayer insulating layers 89 and 93 sequentially stacked.

In addition, a plurality of main word lines 91 may be interposed between the first and second upper interlayer insulating layers 89 and 93. The main word lines 91 extend along the row direction (y-axis) and are parallel to the local plate lines 87. Each of the main word lines 91 generally controls four word lines 57 through a decoder. In addition, a main plate line 97 may be disposed in the upper interlayer insulating layer between the main word lines 91. The main plate line 97 is electrically connected to the local plate line 87 through a slit-type via hole 95 passing through the upper interlayer insulating film. The slit-shaped via hole 95 is parallel to the row direction (y-axis) and exposes the local plate line 87. As shown in FIG. 5, the width of the slit-shaped via hole 95 is larger than the diameter of the via hole (39 in FIG. 3) in the prior art. In addition, the local plate line 87 is in direct contact with the upper surfaces of the upper electrodes 81.

The local plate line 87 and the main plate line 97 constitute a plate line. The plate line may consist of only the local plate line 87 or the main plate line 97. When the plate line is composed of only the main plate line 97, the main plate line 97 is connected to the upper electrodes of the ferroelectric capacitors disposed in at least two adjacent rows through the slit-type via hole 95. 81) direct contact. In addition, when the plate line is composed of only the main plate line 97, the insulating film pattern 85a is preferably a material film having an etching selectivity with respect to the upper interlayer insulating film. For example, when the upper interlayer insulating film is a silicon oxide film, the insulating film pattern 85a is preferably a silicon nitride film.

6 is a perspective view illustrating a ferroelectric memory device according to a second embodiment of the present invention. In the second embodiment of the present invention, the cell transistors, the lower interlayer insulating film and the contact plugs have the same structure as those of the first embodiment of the present invention described in FIG. Therefore, description thereof will be omitted.

4 and 6, a plurality of ferroelectric capacitors covering the contact plugs 75 are disposed on the lower interlayer insulating layer 74. Thus, the ferroelectric capacitors are two-dimensionally arranged along the row direction and the column direction. Each of the ferroelectric capacitors includes a lower electrode 101, a ferroelectric film pattern 103, and a common upper electrode 109 that are sequentially stacked. The common upper electrode 109 contacts the ferroelectric film patterns 103 of the ferroelectric capacitors arranged in at least two adjacent rows and at least one column. In detail, the common upper electrode 109 extends to cover the ferroelectric film patterns 103 arranged on at least two rows adjacent to each other. Accordingly, the common upper electrode 109 is disposed in parallel with the row direction as in the local plate line PL of FIG. 4. The gap region between the ferroelectric layer patterns 103 and the gap region between the lower electrodes 101 may be filled with a lower insulating layer pattern 107a. In addition, as in the first embodiment, it is preferable that a hydrogen blocking film pattern 105a is interposed between the lower insulating film pattern 107a and at least the ferroelectric film pattern 103.

The entire surface of the semiconductor substrate having the common upper electrode 109 is covered by the upper insulating layer 111. The upper insulating layer 111 has a slit type contact hole exposing the common upper electrode 109. The slit-like contact hole is parallel to the row direction (y axis) and covered by a local plate line 113 (PL in FIG. 4). As a result, the local plate line 113 is electrically connected to the common upper electrode 109 through the slit type contact hole. Although not shown, a plurality of local plate patterns may be disposed instead of the local plate line 113. In this case, each of the local plate patterns is in contact with a common top electrode 109 of ferroelectric capacitors arranged in at least two adjacent rows and at least one column. The local plate line 113 is the same material film as the local plate line 87 described in the first embodiment of the present invention. The front surface of the semiconductor substrate having the local plate line 113 is covered by an upper interlayer insulating film. The upper interlayer insulating layer may include first and second upper interlayer insulating layers 115 and 119 which are sequentially stacked.

In addition, a plurality of main word lines 117 may be interposed between the first and second upper interlayer insulating layers 115 and 119. The main word lines 117 are parallel to the row direction. In addition, a main plate line 123 may be disposed in the upper interlayer insulating layer between the main word lines 117. The main plate line 123 is electrically connected to the local plate line 113 through a slit-type via hole 121 passing through the upper interlayer insulating layer. The slit-shaped via hole 121 is parallel to the row direction (y axis). Alternatively, although not shown, the local plate line 113 may be exposed by a plurality of via holes instead of the slit-type via holes 121.

The local plate line 113 and the main plate line 123 constitute a plate line. The plate line may consist of only the local plate line 113 or the main plate line 123. When the plate line includes only the main plate line 123, the main plate line 123 is a common upper electrode of the ferroelectric capacitors disposed in at least two adjacent rows through the slit-type via hole 121. 109) directly.

7 is a perspective view illustrating a ferroelectric memory device according to a third embodiment of the present invention. In the third embodiment of the present invention, the cell transistors, the lower interlayer insulating film and the contact plugs have the same structure as those of the first embodiment of the present invention described in FIG. Therefore, description thereof will be omitted.

4 and 7, a plurality of ferroelectric capacitors covering the contact plugs 75 are disposed on the lower interlayer insulating layer 74. Thus, the ferroelectric capacitors are two-dimensionally arranged along the row direction and the column direction. Each of the ferroelectric capacitors includes a lower electrode 151, a common ferroelectric layer pattern 155, and a common upper electrode 157 that are sequentially stacked. The common ferroelectric film pattern 155 directly contacts the lower electrodes 151 disposed in at least two adjacent rows and at least one column. Specifically, the common ferroelectric film pattern 155 extends to cover the lower electrodes 151 arranged on at least two adjacent rows. In addition, the common upper electrode 157 is stacked on the common ferroelectric layer pattern 155. Accordingly, the common ferroelectric film pattern 155 and the common upper electrode 157 are disposed in parallel with the row direction as in the local plate line PL of FIG. 4.

The gap region between the lower electrodes 151 may be filled with the lower insulating layer pattern 153a. In addition, the gap region between the common ferroelectric layer patterns 155 and the gap region between the common upper electrodes 157 may be filled with the upper insulating layer pattern 161. In addition, the hydrogen blocking layer pattern 159 may be interposed between the upper insulating layer pattern 161 and at least the common ferroelectric layer pattern 155.

A local plate line 163 (PL of FIG. 4) is disposed on the common upper electrode 157. The local plate line 163 is in contact with the common upper electrode 157 of ferroelectric capacitors disposed in at least two rows and at least one column. In addition, the local plate line 163 may extend parallel to the row direction (y-axis). The local plate line 163 is the same material film as the local plate line 87 described in the first embodiment of the present invention. The front surface of the semiconductor substrate having the local plate lines 163 is covered by an upper interlayer insulating film. The upper interlayer insulating layer may include first and second upper interlayer insulating layers 165 and 169 that are sequentially stacked.

In addition, a plurality of main word lines 167 may be interposed between the first and second upper interlayer insulating layers 165 and 169. The main word lines 167 are parallel to the row direction. In addition, a main plate line 173 may be disposed in the upper interlayer insulating layer between the main word lines 167. The main plate line 173 is electrically connected to the local plate line 163 through a slit via hole 171 passing through the upper interlayer insulating layer. The slit-shaped via hole 171 is parallel to the row direction (y axis). The local plate line 163 may be exposed by a plurality of via holes instead of the slit-type via hole 171. In this case, each of the via holes exposes a common top electrode of ferroelectric capacitors disposed in at least two rows and at least one column.

The local plate line 163 and the main plate line 173 constitute a plate line. The plate line may consist of only the local plate line 163 or the main plate line 173. When the plate line includes only the main plate line 173, the main plate line 173 is a common upper electrode of the ferroelectric capacitors disposed in at least two adjacent rows through the slit-type via hole 171. 157) directly.

Next, a method of manufacturing the ferroelectric memory device according to the present invention will be described.

8 through 14 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to a first embodiment of the present invention, according to II ′ of FIG. 4.

Referring to FIG. 8, a device isolation layer 53 is formed in a predetermined region of the semiconductor substrate 51 to define a plurality of active regions 53a. A gate insulating film, a gate conductive film, and a capping insulating film are sequentially formed on the front surface of the semiconductor substrate having the active regions. The capping insulating layer, the gate conductive layer, and the gate insulating layer are successively patterned to form a plurality of parallel gate patterns 60 crossing the upper portions of the active regions 53a and the device isolation layer 53. Each of the gate patterns 60 includes a gate insulating layer pattern 55, a gate electrode 57, and a capping insulating layer pattern 59 that are sequentially stacked. Here, each of the active regions intersects the pair of gate electrodes 57. The gate electrode 57 corresponds to a word line. Preferably, the gate patterns 60 are formed to be parallel to the row direction (y-axis of FIG. 4).

Impurity ions are implanted into the active regions using the gate patterns 60 and the device isolation layer 53 as ion implantation masks. As a result, three impurity regions are formed in each of the active regions. The impurity region in the middle of these three impurity regions corresponds to the common drain region 61d, and the remaining impurity regions correspond to the source regions 61s. Accordingly, a pair of cell transistors are formed in each of the active regions. As a result, the cell transistors are arranged two-dimensionally on the semiconductor substrate 51 along the row direction and the column direction. Subsequently, spacers 63 are formed on the sidewalls of the gate pattern 60 using conventional methods.

Referring to FIG. 9, a first lower interlayer insulating film 65 is formed on the entire surface of the semiconductor substrate having the spacers 63. The first lower interlayer insulating layer 65 is patterned to form pad contact holes exposing the source / drain regions 61s and 61d. Storage node pads 67s and bitline pads 67d are formed in the pad contact hole using conventional methods. The storage node pads 67s are connected to the source regions 61s, and the bit line pads 67d are connected to the common drain region 61d. A second lower interlayer insulating film 69 is formed on the entire surface of the semiconductor substrate having the pads 67s and 67d. The second lower interlayer insulating layer 69 is patterned to form bit line contact holes 71a of FIG. 4 that expose the bit line pads 67d. A plurality of parallel bit lines 71 covering the bit line contact holes are formed. The bit lines 71 cross the upper portions of the word lines 57.

Referring to FIG. 10, a third lower interlayer insulating film 73 is formed on an entire surface of the semiconductor substrate having the bit lines 71. The first to third lower interlayer insulating layers 65, 69, and 73 constitute a lower interlayer insulating layer 74. Subsequently, the second and third lower interlayer insulating layers 69 and 73 are patterned to form storage node contact holes 75a of FIG. 4 that expose the storage node pads 67s. The storage node contact hole may be formed using a wet etching process and a dry etching process to increase an upper diameter thereof. Accordingly, the upper sidewall of the storage node contact hole may have an inclined profile as shown. This is to reduce the electrical resistance between the lower electrode formed in a subsequent process and the source region 61s. Contact plugs 75 are formed in the storage node contact holes.

Referring to FIG. 11, a lower electrode film, a ferroelectric film, and an upper electrode film are sequentially formed on the contact plugs 75 and the lower interlayer insulating film 74. The upper electrode film, the ferroelectric film, and the lower electrode film are successively patterned to form a plurality of ferroelectric capacitors 82 (CP of FIG. 4) arranged two-dimensionally along the row direction and the column direction. Each of the ferroelectric capacitors 82 includes a lower electrode 77, a ferroelectric film pattern 79, and an upper electrode 81 that are sequentially stacked. The lower electrodes 77 contact the contact plugs 75, respectively. As a result, the ferroelectric capacitors 82 are electrically connected to the source regions 61s, respectively. Subsequently, an insulating film 85 is sequentially formed on the entire surface of the resultant product in which the ferroelectric capacitors 82 are formed. Before forming the insulating layer 85, a hydrogen barrier layer 83 may be conformally formed. The hydrogen barrier layer 83 is preferably formed of a titanium oxide layer (TiO ₂ ), an aluminum oxide layer (Al ₂ O ₃ ), a silicon nitride layer (Si ₃ N ₄ ), or a combination thereof.

Referring to FIG. 12, the insulating layer 85 and the hydrogen blocking layer 83 are planarized to expose the upper electrodes 81. The planarization process may be carried out using a chemical mechanical polishing technique or an etch back technique. Accordingly, a hydrogen blocking film pattern 83a and an insulating film pattern 85a are formed between the ferroelectric capacitors 82. The hydrogen blocking film pattern 83a covers sidewalls of the ferroelectric capacitors 82, that is, sidewalls of the ferroelectric film patterns 79. Therefore, hydrogen atoms may be prevented from being injected into the ferroelectric film patterns 79. When hydrogen atoms are injected into the ferroelectric film patterns 79, characteristics of the ferroelectric capacitors 82, such as polarization characteristics and leakage current characteristics, are degraded. As a result, the hydrogen barrier layer pattern 83a improves the characteristics of the ferroelectric capacitor 82.

A lower plate layer is formed on the entire surface of the semiconductor substrate including the insulating layer pattern 85a. The lower plate film may be formed of a metal film, a conductive metal oxide film, a conductive metal nitride film, or a composite film thereof. For example, the lower plate film may include a titanium aluminum nitride film (TiAlN), a titanium film (Ti), a titanium nitride film (TiN), an iridium film (Ir), an iridium oxide film (IrO 2), a platinum film (Pt), and a ruthenium film. (Ru), ruthenium oxide film (RuO2), aluminum film (Al), or a composite film thereof. The lower plate layer is patterned to form a plurality of local plate lines 87 (PL of FIG. 4) parallel to the word lines 57. In other words, the plurality of local plate lines 87 are parallel to the row direction (y-axis in FIG. 4). Each of the local plate lines 87 is in direct contact with a plurality of upper electrodes 81 arranged along two adjacent rows of each other. An upper interlayer insulating film is formed on the entire surface of the semiconductor substrate having the local plate lines 87. The upper interlayer insulating layer is formed by sequentially stacking first and second upper interlayer insulating layers 89 and 93. Before forming the second upper interlayer insulating layer 93, a plurality of parallel main word lines 91 may be formed on the first upper interlayer insulating layer 89. The main word lines 91 are parallel to the row direction (y-axis of FIG. 4). Typically, one main word line 91 controls four word lines 57 through a decoder.

Referring to FIG. 13, the upper interlayer insulating layer is patterned to form a slit type via hole 95 exposing the local plate line 87. The slit-shaped via hole 95 is formed between the main word lines 91 and is parallel to the main word lines 91. Instead of the slit type via hole 95, a plurality of via holes may be formed. In this case, each of the via holes exposes a local plate line 87 located on ferroelectric capacitors disposed in at least two adjacent rows and at least one column. The slit-shaped via hole 95 has a wider width than the prior art as shown. Nevertheless, the spacing A between the slit via hole 95 and the main word lines 91 adjacent thereto may be kept larger than in the related art. Thus, even if the slit via hole 95 is formed using a wet etching process and a dry etching process to further reduce the aspect ratio of the slit via hole 95, the probability of the main word lines 91 is exposed. Is significantly reduced compared to the prior art. As a result, without exposing the main word lines 91, the aspect ratio of the slit via hole 95 can be significantly reduced as compared to the prior art, and the exposed area of the local plate line 87 can be maximized. have.

Subsequently, an upper plate film such as a metal film is formed on the entire surface of the resultant in which the slit-shaped via holes 95 are formed. For example, the upper plate film may be formed of an aluminum film. In this case, since the aspect ratio of the slit-type via hole 95 is significantly low, the upper plate film exhibits excellent step coverage. The upper plate layer is patterned to form a main plate line 97 covering the slit via hole 95. The main plate line 97 is formed to be parallel to the row direction (y-axis). As a result, the main plate line 97 is electrically connected to the ferroelectric capacitors disposed in at least two adjacent rows via the local plate line 87.

FIG. 14 is a cross-sectional view for describing a modified embodiment of the first embodiment described with reference to FIGS. 8 to 13. The modification corresponds to the case where the step of forming the local plate line 87 is omitted in the first embodiment of the present invention. In this case, not only the upper electrodes 81 but also the insulating layer pattern 85a therebetween are exposed while the slit-type via hole 95 is formed. Accordingly, the insulating layer pattern 85a may be formed of a material layer having an etching selectivity with respect to the upper interlayer insulating layer, for example, a silicon nitride layer. As a result, the main plate line 97 is in direct contact with the upper electrodes 81 of the ferroelectric capacitors arranged in at least two adjacent rows.

15 to 19 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to a second embodiment of the present invention according to II ′ of FIG. 4. In the second embodiment of the present invention, the cell transistors, the lower interlayer insulating film, and the contact plugs are formed using the same method as the first embodiment of the present invention described with reference to Figs. Therefore, description thereof will be omitted.

Referring to FIG. 15, a lower electrode layer and a ferroelectric layer are sequentially formed on the lower interlayer insulating layer 74 and the contact plugs 75. The ferroelectric film and the lower electrode film are successively patterned to form a plurality of lower electrodes 101 covering the contact plugs 75 and a plurality of ferroelectric film patterns 103 stacked on the lower electrodes 101. Form. The hydrogen blocking film 105 and the lower insulating film 107 are sequentially formed on the entire surface of the semiconductor substrate having the ferroelectric film patterns 103 using the same method as the first embodiment of the present invention described with reference to FIG.

Referring to FIG. 16, the lower insulating film 107 and the hydrogen blocking film 105 are planarized to expose the ferroelectric film patterns 103. Accordingly, the lower insulating layer pattern 107a and the hydrogen blocking layer pattern 105a are formed in the gap region between the ferroelectric layer patterns 103 and the gap region between the lower electrodes 101. An upper electrode layer is formed on the entire surface of the resultant product in which the lower insulating layer pattern 107a and the hydrogen blocking layer pattern 105a are formed. The upper electrode layer is patterned to form a plurality of common upper electrodes 109 parallel to the word lines 57. Each of the common upper electrodes 109 covers the ferroelectric film patterns 103 arranged on at least two rows adjacent to each other. In other words, the common upper electrode 109 is in contact with ferroelectric film patterns 103 of ferroelectric capacitors arranged in at least two rows and at least one column.

Referring to FIG. 17, an upper insulating layer 111 is formed on an entire surface of a semiconductor substrate including the common upper electrodes 109. The upper insulating layer 111 is patterned to form a slit type contact hole exposing the common upper electrode 109. The process of forming the upper insulating layer 111 and the slit type contact hole may be omitted. A lower plate film is formed on the entire surface of the semiconductor substrate having the slit type contact hole. The lower plate film is formed of the same material film as the lower plate film described in the first embodiment of the present invention. The lower plate layer is patterned to form local plate lines 113 (PL of FIG. 4) covering the slit-type contact holes. First and second upper interlayer insulating layers 115 and 119 are sequentially formed on the entire surface of the semiconductor substrate including the local plate line 113. The first and second upper interlayer insulating layers 115 and 119 form an upper interlayer insulating layer.

In addition, a plurality of parallel main word lines 117 may be formed between the first and second upper interlayer insulating layers 115 and 119. The main word lines 117 are formed using the same method as the first embodiment of the present invention described in FIG.

Referring to FIG. 18, a slit type via hole 121 penetrating the upper interlayer insulating layer is formed, and a main plate line 123 is formed to cover the slit type via hole 121. The slit-shaped via hole 121 and the main plate line 123 are formed using the same method as in the first embodiment of the present invention.

19 is a cross-sectional view for describing a modified embodiment of the second embodiment described with reference to FIGS. 15 to 18. The modification corresponds to a case where the process of forming the local plate line 113 is omitted in the second embodiment of the present invention. In this case, the slit type via hole 121 exposes the common upper electrode 109.

20 to 24 are cross-sectional views illustrating a method of manufacturing a ferroelectric memory device according to a third embodiment of the present invention, according to II ′ of FIG. 4. In the third embodiment of the present invention, the cell transistors, the lower interlayer insulating film, and the contact plugs are formed using the same method as the first embodiment of the present invention described with reference to FIGS. Therefore, description thereof will be omitted.

Referring to FIG. 20, a lower electrode layer is formed on the lower interlayer insulating layer 74 and the contact plugs 75. The lower electrode layer is patterned to form a plurality of lower electrodes 151 covering the contact plugs 75. The lower insulating layer 153 is formed on the entire surface of the semiconductor substrate including the lower electrodes 151.

Referring to FIG. 21, the lower insulating layer 153 is planarized to expose upper surfaces of the lower electrodes 151. Accordingly, the lower insulating layer pattern 153a is formed in the gap region between the lower electrodes 151. A ferroelectric film and an upper electrode film are sequentially formed on the entire surface of the resultant product on which the lower insulating film pattern 153a is formed. The upper electrode layer and the ferroelectric layer are successively patterned to be stacked on a plurality of common ferroelectric layer patterns 155 parallel to the word lines 57 and the common ferroelectric layer patterns 155. A plurality of common upper electrodes 157 are formed. Each of the common ferroelectric film patterns 155 covers the lower electrodes 151 arranged in at least two rows and at least one column adjacent to each other. In addition, each of the common ferroelectric film patterns 155 may extend to be parallel to the row direction (y-axis). The hydrogen barrier layer pattern 159 and the upper insulation layer pattern are formed in the gap region between the common ferroelectric layer patterns 155 and the gap region between the common upper electrodes 157 using the same method as in the first embodiment of the present invention. 161 is formed.

Referring to FIG. 22, a lower plate layer is formed on an entire surface of the semiconductor substrate having the upper insulating layer pattern 161. The lower plate film is formed of the same material film as the lower plate film described in the first embodiment of the present invention. The lower plate layer is patterned to form a local plate line 163 (PL of FIG. 4) covering the common upper electrode 157. As a result, the local plate line 163 is in contact with the common upper electrode 157 of the ferroelectric capacitors arranged in at least two adjacent rows. Preferably, the local plate line 163 is in contact with the common upper electrode 157 of the ferroelectric capacitors arranged in at least two adjacent rows and at least one column.

An upper interlayer insulating film is formed on the entire surface of the resultant product in which the local plate lines 163 are formed. The upper interlayer insulating layer is formed by sequentially stacking first and second upper interlayer insulating layers 165 and 169. In addition, a plurality of parallel main word lines 167 may be formed between the first and second upper interlayer insulating layers 165 and 169. The main word lines 167 are formed using the same method as the first embodiment of the present invention described in FIG.

Referring to FIG. 23, a slit type via hole 171 penetrating the upper interlayer insulating layer is formed, and a main plate line 173 is formed to cover the slit type via hole 171. The slit-shaped via hole 171 and the main plate line 173 are formed using the same method as in the first embodiment of the present invention.

FIG. 24 is a cross-sectional view for illustrating a modified embodiment of the third embodiment illustrated in FIGS. 20 to 23. The modification corresponds to a case where the process of forming the local plate line 163 is omitted in the third embodiment of the present invention. In this case, the slit type via hole 171 exposes the common upper electrode 157.

FIG. 25 is a plan view illustrating a modified embodiment of the first embodiment of the present invention shown in FIG. 4, and FIG. 26 is a ferroelectric memory device according to a modified embodiment of the present invention according to II-II ′ of FIG. 25, and a fabrication thereof. Sections for explaining the method. In this modification, the cell transistors, lower interlayer insulating film, contact plugs, ferroelectric capacitors and insulating film patterns are formed using the same method as the first embodiment of the present invention described in Figs. Therefore, description thereof will be omitted.

First, a ferroelectric memory device according to a modification of the present invention will be described with reference to FIGS. 25 and 26.

25 and 26, a plurality of local plate patterns PP are disposed on the ferroelectric capacitors 82 and the insulating layer pattern 85a. The local plate patterns PP may be a metal film, a conductive metal oxide film, a conductive metal nitride film, or a composite film thereof. For example, the local plate patterns PP may include titanium aluminum nitride (TiAlN), titanium (Ti), titanium nitride (TiN), iridium (Ir), iridium oxide (IrO ₂ ), and platinum ( Pt), ruthenium film Ru, ruthenium oxide film RuO ₂ , aluminum film Al, or a composite film thereof. The local plate patterns PP are two-dimensionally disposed along the row direction (y axis) and the column direction (x axis). More specifically, each of the local plate patterns PP covers the ferroelectric capacitors 82 disposed in at least two adjacent rows and at least one column. For example, each of the local plate patterns PP covers four capacitors 82 disposed in two adjacent rows and two adjacent columns, as shown in FIG. 25. As a result, each of the local plate patterns PP is in direct contact with the upper electrodes 81 disposed in at least two adjacent rows and at least one column. The entire surface of the semiconductor substrate having the local plate patterns PP is covered by an upper interlayer insulating film. Here, the upper interlayer insulating layers may include first and second upper interlayer insulating layers 89 and 93 sequentially stacked.

In addition, as shown in the first embodiment of the present invention, a plurality of main word lines 91 may be interposed between the first and second upper interlayer insulating layers 89 and 93. . Each of the main word lines 91 generally controls four word lines 57 through a decoder. A main plate line 97 is disposed in the upper interlayer insulating layer between the main word lines 91. The main plate line 97 is electrically connected to the plurality of local plate patterns PP disposed in parallel with the y direction through a plurality of via holes 95c penetrating the upper interlayer insulating layer. In contrast, the main plate line 97 is electrically connected to the plurality of local plate patterns PP disposed to be parallel to the y direction through a slit-type via hole (95 in FIG. 4) passing through the upper interlayer insulating layer. May be connected.

Next, a method of manufacturing a ferroelectric memory device according to a modification of the present invention will be described.

Referring to FIGS. 25 and 26, a lower plate layer is formed on the entire surface of the semiconductor substrate on which the ferroelectric capacitors 82 and the insulating layer patterns 85a are formed. The lower plate film may be formed of a metal film, a conductive metal oxide film, a conductive metal nitride film, or a composite film thereof. Specifically, the lower plate film is a titanium aluminum nitride film (TiAlN), a titanium film (Ti), a titanium nitride film (TiN), an iridium film (Ir), an iridium oxide film (IrO ₂ ), a platinum film (Pt), a ruthenium film (Ru), a ruthenium oxide film (RuO ₂ ), an aluminum film (Al), or a composite film thereof. The lower plate layer is patterned to form a plurality of local plate patterns PP. Each of the local plate patterns PP covers ferroelectric capacitors 82 arranged in at least two adjacent rows and at least one column. For example, each of the local plate patterns PP is in direct contact with four upper electrodes 81 disposed in two adjacent rows and two adjacent columns. Accordingly, physical stress due to the local plate patterns PP can be significantly reduced compared to the first embodiment of the present invention employing the local plate line. In particular, when the lower plate film is formed of a material film having a high stress such as an iridium film and / or an iridium oxide film, the stress due to the local plate patterns PP may be reduced in the first embodiment of the present invention. It is significantly reduced compared to the stress due to the local plate lines 87. Therefore, when forming the local plate patterns PP instead of the local plate line 87 as in the present modification, the stress applied to the ferroelectric capacitors 82 can be reduced. As a result, the degradation of the ferroelectric characteristics of the ferroelectric capacitors 82 can be suppressed.

An upper interlayer insulating film is formed on the entire surface of the semiconductor substrate having the local plate patterns PP. The upper interlayer insulating layer is formed by sequentially stacking first and second upper interlayer insulating layers 89 and 93. Before forming the second upper interlayer insulating layer 93, a plurality of main word lines 91 parallel to the y direction may be formed on the first upper interlayer insulating layer 89. Here, each of the main word lines 91 generally controls four word lines 57 through a decoder.

Subsequently, the upper interlayer insulating layer is patterned to form a plurality of via holes 95c exposing the local plate patterns PP. Accordingly, the plurality of via holes 95c are two-dimensionally arranged along the x and y axes. Alternatively, instead of the via holes 95c, the slit type via hole (95 in FIGS. 5 and 13) described in the first embodiment of the present invention may be formed. An upper plate film such as a metal film is formed on the entire surface of the semiconductor substrate having the plurality of via holes 95c. The upper plate layer is patterned to form a main plate line 97 covering the plurality of via holes 95c. The main plate line 97 is formed to be parallel to the y axis.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art. For example, each of the plate lines may cover ferroelectric capacitors arranged on three or more rows adjacent to each other.

As described above, according to the present invention, one plate line is in direct contact with the upper electrodes of the ferroelectric capacitors arranged on at least two rows adjacent to each other in the cell array region. Alternatively, ferroelectric capacitors arranged on at least two adjacent rows may share one common top electrode. In this case, the common upper electrode is in direct contact with one plate line. Accordingly, a reliable contact structure can be implemented between the plate line and the upper electrode.

In addition, in the case where main word lines are disposed in the cell array region and slit via holes are formed between the main word lines, the distance between the slit via holes and the main word lines may be increased considerably. Can be.

Furthermore, in the case of forming a plurality of local plate patterns instead of the local plate line, the physical stress applied to the ferroelectric capacitors can be significantly reduced. Accordingly, it is possible to prevent the ferroelectric characteristics of the ferroelectric capacitors from deteriorating.

As a result, it is possible to increase the degree of integration of the ferroelectric memory element and to improve its reliability.

Claims (81)

A lower interlayer insulating film formed on the semiconductor substrate; A plurality of ferroelectric capacitors arranged two-dimensionally in a row direction and a column direction on the lower interlayer insulating film; An upper interlayer insulating film stacked on an entire surface of the semiconductor substrate having the plurality of ferroelectric capacitors; And A plurality of plate lines disposed in the upper interlayer insulating film in parallel with the row direction, each of the plate lines having upper surfaces of the ferroelectric capacitors arranged on at least two rows adjacent to each other; A ferroelectric memory device, characterized in that in direct contact. The method of claim 1, The plate line is a local plate line in direct contact with the top surfaces of the ferroelectric capacitors arranged on at least two adjacent rows, wherein the local plate line is covered by the upper interlayer insulating film. A ferroelectric memory device, characterized in that. The method of claim 2, The local plate line may be a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. . The method of claim 1, The plate line is in direct contact with the upper surfaces of the ferroelectric capacitors arranged on at least two rows adjacent to each other through a slit-type via hole penetrating the upper interlayer insulating film. ferroelectric memory device, characterized in that the main plate line). The method of claim 4, wherein And the upper interlayer insulating layer includes first and second upper interlayer insulating layers that are sequentially stacked. The method of claim 5, And ferroelectric memory elements disposed on both sides of the slit-type via hole in parallel with the row direction and interposed between the first and second upper interlayer insulating layers. . The method of claim 1, The plate line is A local plate line in direct contact with upper surfaces of the ferroelectric capacitors arranged on at least two adjacent rows, the local plate line covered by the upper interlayer insulating film; And And a main plate line directly contacting an upper surface of the local plate line through a slit-type via hole penetrating through the upper interlayer insulating layer. The method of claim 7, wherein The local plate line may be a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. . The method of claim 7, wherein And the upper interlayer insulating layer includes first and second upper interlayer insulating layers that are sequentially stacked. The method of claim 9, And ferroelectric memory elements disposed on both sides of the slit-type via hole in parallel with the row direction and interposed between the first and second upper interlayer insulating layers. . The method of claim 1, Each of the ferroelectric capacitors is electrically connected to a predetermined region of the semiconductor substrate through a storage node contact hole penetrating the lower interlayer insulating layer, wherein an upper diameter of the storage node contact hole is larger than a lower diameter of the ferroelectric capacitor. Memory elements. The method of claim 1, Each of the ferroelectric capacitors includes a lower electrode, a ferroelectric film pattern, and an upper electrode stacked in sequence, and the plate line is in direct contact with the upper electrodes arranged on at least two adjacent rows. Ferroelectric memory device. The method of claim 12, And an insulating film pattern filling a gap region between the ferroelectric capacitors, wherein the insulating film pattern is interposed between the upper interlayer insulating film and the lower interlayer insulating film. The method of claim 13, And the insulating layer pattern has an etch selectivity with respect to the upper interlayer insulating layer. The method of claim 13, And a hydrogen barrier layer pattern interposed between at least the ferroelectric film patterns and the insulating film pattern. The method of claim 1, The ferroelectric capacitor includes a lower electrode, a ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common upper electrode extends to cover the ferroelectric layer patterns positioned below the plate line, and the common top electrode. An upper surface of the upper electrode is in direct contact with the plate line. The method of claim 16, And an insulating layer pattern filling the gap region between the lower electrodes and the gap region between the ferroelectric layer patterns, wherein the insulating layer pattern is interposed between the upper interlayer insulating layer and the lower interlayer insulating layer. device. The method of claim 17, And a hydrogen barrier layer pattern interposed between at least sidewalls of the ferroelectric film patterns and the insulating film pattern. The method of claim 1, The ferroelectric capacitor includes a lower electrode, a common ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common ferroelectric layer pattern extends so that the lower electrode below the plate line. And a common upper electrode interposed between the common ferroelectric layer pattern and the plate line. The method of claim 19, And an insulating layer pattern filling the gap region between the common ferroelectric layer patterns and the gap region between the common upper electrodes, wherein the insulating layer pattern is interposed between the lower interlayer insulating layer and the upper interlayer insulating layer. Ferroelectric memory device. The method of claim 20, And a hydrogen barrier layer pattern interposed between at least sidewalls of the common ferroelectric film patterns and the insulating film pattern. A plurality of cell transistors two-dimensionally arranged in a row direction and a column direction on the semiconductor substrate; A lower interlayer insulating film covering the entire surface of the semiconductor substrate having the cell transistors; A ferroelectric capacitor disposed two-dimensionally on the lower interlayer insulating film in the row direction and the column direction, each of which is electrically connected to the respective cell transistors through a storage node contact hole passing through the lower interlayer insulating film; field; A plurality of ferroelectric capacitors arranged in parallel with the row direction on each of the semiconductor substrates having the ferroelectric capacitors, each of which is in direct contact with upper surfaces of the ferroelectric capacitors arranged on at least two adjacent rows; Local plate lines; And And ferroelectric memory devices including first and second upper interlayer insulating films sequentially stacked on a front surface of the semiconductor substrate having the plurality of local plate lines. The method of claim 22, The local plate lines may be a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. . The method of claim 22, A slit-type via hole penetrating the first and second upper interlayer insulating layers to expose the local plate line; And And a main plate line covering the slit-type via hole. The method of claim 24, And further comprising a plurality of main word lines interposed between the first and second upper interlayer insulating layers, wherein the main word lines are parallel to the row direction and disposed on both sides of the slit type via hole. Ferroelectric memory device, characterized in that. The method of claim 22, The ferroelectric capacitor includes a lower electrode, a ferroelectric layer pattern, and an upper electrode, which are sequentially stacked, and the local plate line is in direct contact with the upper electrodes arranged on at least two adjacent rows. Memory elements. The method of claim 22, The ferroelectric capacitor includes a lower electrode, a ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common upper electrode extends to cover the ferroelectric layer patterns positioned below the local plate line. The upper surface of the common upper electrode is in direct contact with the local plate line. The method of claim 22, The ferroelectric capacitor includes a lower electrode, a common ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common ferroelectric layer pattern extends to extend the lower portion of the lower portion of the local plate line. And covering the electrodes, wherein the common upper electrode is interposed between the common ferroelectric layer pattern and the local plate line. A plurality of cell transistors two-dimensionally arranged in a row direction and a column direction on the semiconductor substrate; A lower interlayer insulating film covering the entire surface of the semiconductor substrate having the cell transistors; A ferroelectric capacitor disposed two-dimensionally on the lower interlayer insulating film in the row direction and the column direction, each of which is electrically connected to the respective cell transistors through a storage node contact hole passing through the lower interlayer insulating film; field; First and second upper interlayer insulating layers sequentially stacked on a front surface of the semiconductor substrate having the ferroelectric capacitors; A slit via hole penetrating the first and second upper interlayer insulating films, exposing upper surfaces of the ferroelectric capacitors arranged on at least two adjacent rows, and being parallel to the row direction; And And a main plate line covering the slit-type via hole. The method of claim 29, And a plurality of main word lines disposed at both sides of the slit-type via hole in parallel with the row direction and interposed between the first and second upper interlayer insulating layers. Ferroelectric memory device. The method of claim 29, The ferroelectric capacitor includes a lower electrode, a ferroelectric layer pattern, and an upper electrode, which are sequentially stacked, and the main plate line directly contacts the upper electrodes arranged on at least two adjacent rows. Memory elements. The method of claim 29, The ferroelectric capacitor may include a lower electrode, a ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common upper electrode extends to cover the ferroelectric layer patterns positioned below the main plate line. And an upper surface of the common upper electrode is in direct contact with the main plate line. The method of claim 29, The ferroelectric capacitor includes a lower electrode, a common ferroelectric layer pattern, and a common top electrode, which are sequentially stacked, and the common ferroelectric layer pattern extends to extend the lower portion of the lower portion of the main plate line. And covering the electrodes, wherein the common upper electrode is interposed between the common ferroelectric layer pattern and the main plate line. Forming a lower interlayer insulating film on the semiconductor substrate; Forming a plurality of ferroelectric capacitors arranged two-dimensionally in a row direction and a column direction on the lower interlayer insulating film; And And forming a plurality of plate lines arranged parallel to the row direction in the upper interlayer insulating film and the upper interlayer insulating film stacked on the front surface of the semiconductor substrate having the ferroelectric capacitors, each of the plate lines being adjacent to each other. A method for manufacturing a ferroelectric memory device, characterized in that it is in direct contact with top surfaces of said ferroelectric capacitors arranged on at least two rows. The method of claim 34, wherein Forming the plurality of ferroelectric capacitors Sequentially forming a lower electrode film, a ferroelectric film, and an upper electrode film on the lower interlayer insulating film; And A plurality of lower electrodes arranged two-dimensionally along the row direction and the column direction by successively patterning the upper electrode film, the ferroelectric film and the lower electrode film, and a plurality of ferroelectric films stacked on the lower electrodes And forming a plurality of upper electrodes stacked on the patterns and on the ferroelectric layer patterns. 36. The method of claim 35 wherein Forming the upper interlayer insulating film and the plate lines Forming an insulating film on an entire surface of the semiconductor substrate on which the ferroelectric capacitors are formed; Planarizing the insulating film until the upper electrodes are exposed to form an insulating film pattern filling a gap region between the ferroelectric capacitors; Forming a lower plate film on an entire surface of the semiconductor substrate having the insulating film pattern; Patterning the lower plate film to form a plurality of local plate lines parallel to the row direction, wherein each local plate line is in direct contact with the upper electrodes arranged on at least two adjacent rows; And And sequentially forming a first upper interlayer insulating film and a second upper interlayer insulating film on a front surface of the semiconductor substrate having the local plate lines. The method of claim 36, The lower plate layer may be formed of a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. Method of manufacturing the device. The method of claim 36, Before the forming of the insulating film, And forming a hydrogen barrier film conformally on the entire surface of the semiconductor substrate having the ferroelectric capacitors, wherein the hydrogen barrier films on the upper electrodes are removed while the insulating film is planarized. . The method of claim 36, Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to expose the local plate line and form a slit via hole parallel to the row direction; And And forming a main plate line covering the slit-type via hole. The method of claim 39, Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. 36. The method of claim 35 wherein Forming the upper interlayer insulating film and the plate lines Forming an insulating film on an entire surface of the semiconductor substrate on which the ferroelectric capacitors are formed; Planarizing the insulating film until the upper electrodes are exposed to form an insulating film pattern filling a gap region between the ferroelectric capacitors; Sequentially forming first and second upper interlayer insulating films on the entire surface of the semiconductor substrate having the insulating film pattern; Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to expose the upper electrodes arranged on at least two adjacent rows and to form a slit type via hole parallel to the row direction; And And forming a main plate line covering the slit-type via hole. 42. The method of claim 41, wherein the insulating film is formed of a material film having an etch selectivity with respect to the first upper interlayer insulating film. 42. The method of claim 41 wherein Before the forming of the insulating film, And forming a hydrogen barrier film conformally on the entire surface of the semiconductor substrate having the ferroelectric capacitors, wherein the hydrogen barrier films on the upper electrodes are removed while the insulating film is planarized. . 42. The method of claim 41 wherein Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. The method of claim 34, wherein Forming the ferroelectric capacitors Sequentially forming a lower electrode film and a ferroelectric film on the lower interlayer insulating film; Successively patterning the ferroelectric film and the lower electrode film to form a plurality of lower electrodes arranged in two dimensions along the row direction and the column direction and a plurality of ferroelectric film patterns stacked on the lower electrodes ; Forming a lower insulating layer pattern filling a gap region between the lower electrodes and a gap region between the ferroelectric layer patterns; Forming an upper electrode film on an entire surface of the semiconductor substrate having the lower insulating film pattern; And Patterning the upper electrode film to form a plurality of common upper electrodes parallel to the row direction, wherein each common upper electrode is directly connected to the ferroelectric film patterns arranged on at least two adjacent rows; A method of manufacturing a ferroelectric memory device, characterized in that the contact. The method of claim 45, And forming a hydrogen blocking film pattern interposed between the sidewalls of the ferroelectric film pattern and the lower insulating film pattern. The method of claim 45, Forming the upper interlayer insulating film and the plate lines Forming an upper insulating film on an entire surface of the semiconductor substrate on which the ferroelectric capacitors are formed; Patterning the upper insulating film to expose the common upper electrode and form a slit type contact hole parallel to the row direction; Forming a local plate line covering the slit-like contact hole; And And sequentially forming first and second upper interlayer insulating films on the entire surface of the semiconductor substrate having the local plate lines. The method of claim 47, The local plate line may be formed of a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. Method of manufacturing a memory device. The method of claim 47, Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to expose the local plate line and form a slit via hole parallel to the row direction; And And forming a main plate line covering the slit-type via hole. The method of claim 49, Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. The method of claim 45, Forming the upper interlayer insulating film and the plate lines Sequentially forming first and second upper interlayer insulating films on the entire surface of the semiconductor substrate on which the ferroelectric capacitors are formed; Successively patterning the second upper interlayer insulating layer and the first upper interlayer insulating layer to form a slit type via hole parallel to the row direction while exposing the common upper electrode; And And forming a main plate line covering the slit-type via hole. The method of claim 51, wherein Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. The method of claim 34, wherein Forming the ferroelectric capacitors Forming a plurality of lower electrodes arranged two-dimensionally in the row direction and the column direction on the lower interlayer insulating film; Sequentially forming a ferroelectric film and an upper electrode film on the entire surface of the semiconductor substrate having the lower electrode; And The upper electrode layer and the ferroelectric layer are successively patterned to form a plurality of common ferroelectric layer patterns parallel to the row direction and a plurality of common upper electrodes stacked on the plurality of ferroelectric layer patterns, respectively. And a film pattern is in direct contact with upper surfaces of the lower electrodes arranged on at least two adjacent rows. The method of claim 53, wherein Forming the upper interlayer insulating film and the plate lines Forming an insulating film pattern filling a gap region between the ferroelectric capacitors; Forming a lower plate film on an entire surface of the semiconductor substrate having the insulating film pattern; Patterning the lower plate layer to form a plurality of local plate lines covering the common upper electrodes; And And sequentially forming a first upper interlayer insulating film and a second upper interlayer insulating film on a front surface of the semiconductor substrate having the local plate line. The method of claim 54, wherein The lower plate layer may be formed of a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. Method of manufacturing the device. The method of claim 54, wherein And forming a hydrogen blocking film pattern interposed between at least the common ferroelectric film pattern and the insulating film pattern. The method of claim 54, wherein Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to form a slit type via hole parallel to the row direction while exposing the local plate line; And And forming a main plate line covering the slit-type via hole. The method of claim 57, Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. The method of claim 53, wherein Forming the upper interlayer insulating film and the plate lines Sequentially forming first and second upper interlayer insulating films on the entire surface of the semiconductor substrate on which the ferroelectric capacitors are formed; Successively patterning the second upper interlayer insulating layer and the first upper interlayer insulating layer to form a slit type via hole parallel to the row direction while exposing the common upper electrode; And And forming a main plate line covering the slit-type via hole. The method of claim 59, Before forming the first upper interlayer insulating film And forming an insulating film pattern filling the gap regions between the ferroelectric capacitors. The method of claim 60, And forming a hydrogen blocking film pattern interposed between at least the common ferroelectric film pattern and the insulating film pattern. The method of claim 59, Before forming the second upper interlayer insulating film, And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. Forming a plurality of cell transistors two-dimensionally arranged in a row direction and a column direction on a semiconductor substrate; Forming a lower interlayer insulating film on an entire surface of the semiconductor substrate having the cell transistors; Forming a plurality of ferroelectric capacitors arranged two-dimensionally along the row direction and the column direction on the lower interlayer insulating film, wherein the ferroelectric capacitors are formed through the storage node contact holes penetrating the lower interlayer insulating film. Electrically connected with a transistor; Forming a plurality of local plate lines arranged parallel to the row direction on the semiconductor substrate having the plurality of ferroelectric capacitors, wherein each local plate line is on top of the ferroelectric capacitors arranged on at least two adjacent rows; In direct contact with the faces; And And sequentially forming first and second upper interlayer insulating films on a front surface of the semiconductor substrate having the plurality of local plate lines. The method of claim 63, wherein The local plate lines may be formed of a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. Method of manufacturing a memory device. The method of claim 63, wherein Forming the plurality of local plate lines Forming an insulating film pattern filling a gap region between the plurality of ferroelectric capacitors; Forming a lower plate film on an entire surface of the semiconductor substrate having the insulating film pattern; And Patterning the lower plate film to form a plurality of local plate lines parallel to the row direction, each local plate line having top surfaces of the ferroelectric capacitors arranged on at least two adjacent rows; A method of manufacturing a ferroelectric memory device, characterized in that in direct contact. The method of claim 63, wherein Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to form a slit type via hole parallel to the row direction while exposing the local plate line; And And forming a main plate line covering the slit-type via hole. The method of claim 66, wherein Before forming the second upper interlayer insulating film And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. Forming a plurality of cell transistors two-dimensionally arranged in a row direction and a column direction on a semiconductor substrate; Forming a lower interlayer insulating film on an entire surface of the semiconductor substrate having the cell transistors; Forming a plurality of ferroelectric capacitors arranged two-dimensionally along the row direction and the column direction on the lower interlayer insulating film, wherein the ferroelectric capacitors are formed through the storage node contact holes penetrating the lower interlayer insulating film. Electrically connected with a transistor; Sequentially forming first and second upper interlayer insulating films on a front surface of the semiconductor substrate having the plurality of ferroelectric capacitors; Successively patterning the second upper interlayer insulating film and the first upper interlayer insulating film to expose top surfaces of the ferroelectric capacitors arranged on at least two adjacent rows, and to form slit via holes parallel to the row direction. step; And Forming a main plate line covering the slit-type via hole. The method of claim 68, wherein Before forming the second upper interlayer insulating film And forming a plurality of main word lines parallel to the row direction on the first upper interlayer insulating layer, wherein the main word lines are disposed at both sides of the slit-type via hole. Manufacturing method. Semiconductor substrates; A plurality of ferroelectric capacitors arranged two-dimensionally in a row direction and a column direction on the semiconductor substrate; And A plurality of local plate patterns covering the plurality of ferroelectric capacitors and arranged two-dimensionally along the row direction and the column direction, each of the local plate patterns being within at least two adjacent rows and at least two adjacent columns. A ferroelectric memory device, characterized in that it is in direct contact with the top surfaces of arranged ferroelectric capacitors. The method of claim 70, The local plate patterns may be a titanium aluminum nitride film, a titanium film, a titanium nitride film, an iridium film, an iridium oxide film, a platinum film, a ruthenium film, a ruthenium oxide film, an aluminum film, or a combination thereof. . The method of claim 70, Each of the ferroelectric capacitors includes a lower electrode, a ferroelectric film pattern, and an upper electrode stacked in sequence, each of the local plate patterns having an upper surface of the upper electrodes arranged in the at least two adjacent rows and the at least two adjacent columns. Ferroelectric memory device, characterized in that in direct contact with the field. The method of claim 72, Wherein each of the local plate patterns is in direct contact with top surfaces of four upper electrodes arranged in two adjacent rows and two adjacent columns. The method of claim 70, And a plurality of main plate lines disposed parallel to the row direction on the semiconductor substrate having the local plate patterns, wherein each of the main plate lines includes the plurality of local plate patterns disposed along the row direction; A ferroelectric memory element, which is electrically connected. 77. The method of claim 74. And each of the main plate lines is electrically connected to the plurality of local plate patterns through a plurality of via holes or one slit via hole arranged in parallel with the row direction. 76. The method of claim 75 wherein And further comprising main word lines disposed parallel to the row direction on both sides of the slit-shaped via hole or the plurality of via holes, wherein the main word lines are higher than the local plate patterns and the main plate lines. A ferroelectric memory device, characterized in that disposed below the lines. The method of claim 1, And the plate line is in contact with the ferroelectric capacitors arranged in at least two adjacent rows and at least one column. The method of claim 4, wherein And the slit-type via hole exposes the ferroelectric capacitors arranged in at least two adjacent rows and at least one column. The method of claim 7, wherein And the slit-type via hole exposes the local plate line on the ferroelectric capacitors arranged in at least two adjacent rows and at least one column. The method of claim 34, wherein And the plate line is formed in contact with upper surfaces of the ferroelectric capacitors arranged in at least two rows and at least one column. The method of claim 39, And the slit-type via hole is formed to expose the local plate line on the ferroelectric capacitors arranged in at least two adjacent rows and at least one column.