KR20030000953A - Method for manufacturing transistor of semiconductor device - Google Patents
Method for manufacturing transistor of semiconductor device Download PDFInfo
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- KR20030000953A KR20030000953A KR1020010037229A KR20010037229A KR20030000953A KR 20030000953 A KR20030000953 A KR 20030000953A KR 1020010037229 A KR1020010037229 A KR 1020010037229A KR 20010037229 A KR20010037229 A KR 20010037229A KR 20030000953 A KR20030000953 A KR 20030000953A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체장치의 트랜지스터 제조방법에 관한 것으로서, 보다 상세하게는 반도체장치의 트랜지스터 제조시 결합누설 감소 및 콘택저항 감소를 위하여 소오스와 드레인의 콘택을 형성하기 위하여 랜딩플러그를 사용하는데 이때 랜딩플러그를 형성할 때 분자량이 무겁고 열확산이 적은 As를 사용할 뿐만 아니라 채널부를 정션부보다 깊게 형성하고 양끝단에 스페이서를 형성하여 랜딩플러그에서 확산되어 채널로 침투되는 현상을 막아 트랜지스터의 문턱전압, 오프시 흐르는 전류, GIDL열화의 마진을 확보할 수 있도록 한 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. More particularly, a landing plug is used to form a contact between a source and a drain to reduce coupling leakage and reduce contact resistance in manufacturing a transistor of a semiconductor device. When forming, not only uses As, which has a high molecular weight and low thermal diffusion, but also forms the channel portion deeper than the junction portion and forms a spacer at both ends to prevent the phenomenon of diffusion from the landing plug and penetration into the channel, thereby preventing the threshold voltage of the transistor and the current flowing in the off state. The present invention relates to a method for manufacturing a semiconductor device, which can secure a margin of deterioration of GIDL.
일반적으로, 반도체장치는 그 집적도가 증가하고 내부 회로가 복잡해지는 추세에 부응하여 다층의 배선 구조를 가지게 되며, 이러한 다층 배선간을 연결하기 위해 많은 방법이 제시되고 있다.In general, a semiconductor device has a multi-layered wiring structure in response to a trend of increasing integration and increasing complexity of internal circuits, and many methods for connecting such multi-layer wirings have been proposed.
도 1은 종래 방법에 의해 형성된 반도체장치의 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view showing a transistor of a semiconductor device formed by a conventional method.
여기에 도시된 바와 같이 반도체기판(10)에 소자간 분리를 위한 소자분리막(20)을 형성한 후 트랜지스터 채널부(30)을 형성한다. 그런다음 게이트(40)를 형성하고 소오스와 드레인을 형성하기 위해 이온주입하여 졍션부(50)를 형성한다.As shown here, after forming the device isolation layer 20 for isolation between devices on the semiconductor substrate 10, the transistor channel part 30 is formed. Thereafter, the gate 40 is formed, and ionization is performed to form the source portion and the drain to form the junction portion 50.
그런다음 트랜지스터가 형성된 전면에 층간절연막(60)을 증착한 후 감광막을 도포하고 마스크 공정을 수행하여 플러그콘택홀을 형성한 후 전면에 SiH4와 PH3의 가스를 동시에 투입하여 P31을 1E20 차수로 도핑시켜 플러그폴리막을 증착하여 플러그콘택홀을 매립하여 평탄화함으로써 랜딩플러그(70)를 형성한다.Then, after depositing the interlayer insulating layer 60 on the front surface where the transistor is formed, a photoresist film is applied, and a mask process is performed to form a plug contact hole, and then SiP4 and PH3 gas are simultaneously introduced into the front surface to dope P31 in the order of 1E20. The landing plug 70 is formed by depositing a plug poly film to fill and planarize the plug contact hole.
이와 같이 P31을 사용하는 이유는 금속보다 폴리가 실리콘기판에서 누설 측면에서 유리하고 랜딩플러그(70)와 기판의 졍션부(50)와의 콘택 저항을 줄이기 위하여 5가 계열인 P31을 도핑한다.The reason for using P31 is that poly is more advantageous than the metal in terms of leakage from the silicon substrate, and doped P31, which is a pentavalent series, in order to reduce contact resistance between the landing plug 70 and the cushion portion 50 of the substrate.
이렇게 형성된 랜딩플러그(70)에 이온주입을 수행하는데 이때 주입되는 P31의 농도는 기판의 정션부(50)에 도핑된 농도보다 높아 후속 열공정에 의해서 랜딩플러그(70)에서 기판(10)쪽으로 확산되어 트랜지스터의 채널부(30)로 침투하게 됨으로써 문턱전압을 떨어뜨리게 되거나, 오프시 흐르는 전류를 증가시키고, GIDL(Gate Induced Drain Leakage) 열화 등 트랜지스터에 악영향을 주는 문제점이 있다.The ion implantation is performed in the landing plug 70 formed as above, and the concentration of P31 implanted is higher than the concentration doped in the junction 50 of the substrate and diffused from the landing plug 70 to the substrate 10 by a subsequent thermal process. As a result, penetration into the channel portion 30 of the transistor causes a drop in the threshold voltage, an increase in the current flowing in the off state, and adversely affects the transistor such as GIDL (Gate Induced Drain Leakage) degradation.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 반도체장치의 트랜지스터 제조시 결합누설 감소 및 콘택저항 감소를 위하여 소오스와 드레인의 콘택을 형성하기 위하여 랜딩플러그를 사용하는데 이때 랜딩플러그를 형성할 때 분자량이 무겁고 열확산이 적은 As를 사용할 뿐만 아니라 채널부를 정션부보다 깊게 형성하고 양끝단에 스페이서를 형성하여 랜딩플러그에서 확산되어 채널로 침투되는 현상을 막아 트랜지스터의 문턱전압, 오프시 흐르는 전류, GIDL열화의 마진을 확보할 수 있도록 한 반도체장치의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use a landing plug to form a contact between a source and a drain for reducing coupling leakage and reducing contact resistance when manufacturing a transistor of a semiconductor device. When forming the landing plug, not only heavy As and low thermal diffusion As is used, but also the channel portion is formed deeper than the junction portion and spacers are formed at both ends to prevent the phenomenon of diffusion from the landing plug and penetration into the channel, thereby preventing the threshold voltage and the off of the transistor. The present invention provides a method for manufacturing a semiconductor device that can secure a current flowing in a circuit and a margin of GIDL deterioration.
도 1은 종래 방법에 의해 형성된 반도체장치의 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view showing a transistor of a semiconductor device formed by a conventional method.
도 2내지 도 7은 본 발명에 의한 반도체장치의 트랜지스터 제조방법을 설명하기 위해 순차적으로 도시한 단면도들이다.2 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 소자분리막10: substrate 20: device isolation film
30 : 채널부 32 : 채널장벽층30: channel portion 32: channel barrier layer
34 : 채널스페이서 40 : 게이트34: channel spacer 40: gate
50 : 졍션부 60 : 층간절연막50: section 60: interlayer insulating film
70 : 랜딩플러그 80 : 감광막70: landing plug 80: photosensitive film
상기와 같은 목적을 실현하기 위한 본 발명은 반도체기판에 소자분리막을 형성하는 단계와, 채널마스크를 통해 기판을 일정깊이 식각하여 채널부를 형성하는 단계와, 채널부를 형성한 후 채널부 내측벽에 채널스페이서를 형성하는 단계와, 채널스페이서를 형성한 후 채널이온주입을 수행한후 게이트를 형성하는 단계와, 게이트를 형성한 후 불순물 확산층을 형성하고 게이트스페이서를 형성하는 단계와, 게이트스페이서를 형성한 전면에 층간절연막을 증착한 후 플러그콘택홀을 형성하는 단계와, 플러그콘택홀을 형성한 후 전면에 As가 도핑된 플러그폴리막을 증착하고 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is the step of forming a device isolation film on the semiconductor substrate, the channel portion by forming a channel portion by etching a predetermined depth through the channel mask, and after forming the channel portion in the channel wall inner channel Forming a spacer; forming a gate after performing channel ion implantation after forming a channel spacer; forming an impurity diffusion layer and forming a gate spacer after forming the gate; and forming a gate spacer. And depositing a plug contact hole after depositing an interlayer insulating film on the entire surface, and depositing and planarizing a plug poly film doped with As on the front surface after forming the plug contact hole.
위에서 채널부는 300∼500Å의 깊이로 형성되는 것을 특징으로 한다.The channel portion from above is characterized in that it is formed to a depth of 300 ~ 500Å.
또한, 채널부를 형성할 때 채널마스크대신에 게이트마스크로 게인을 주어 게이트 CD보다 200∼400Å 크게 형성하는 것을 특징으로 한다.In addition, when the channel portion is formed, the gate mask is gained instead of the channel mask to form 200 to 400 kHz larger than the gate CD.
또한, 플러그폴리막은 SiH4와 AsH3 가스를 사용하여 도핑하는 것을 특징으로 한다.In addition, the plug poly film is characterized in that the doping using SiH4 and AsH3 gas.
위와 같이 이루어진 본 발명은 랜딩플러그를 형성할 때 분자량이 무겁고 열확산이 적은 As를 사용할 뿐만 아니라 채널부를 정션부보다 깊게 형성하고 양끝단에 채널스페이서를 형성하여 랜딩플러그에서 확산되어 채널로 침투되는 현상을 막아 트랜지스터의 문턱전압, 오프시 흐르는 전류, GIDL열화의 마진을 확보할 수 있게 된다.When the landing plug is formed, the present invention is formed of a channel spacer deeper than the junction portion and a channel spacer formed at both ends, as well as using As molecular weight and low thermal diffusion when forming the landing plug. As a result, the threshold voltage of the transistor, the current flowing in the OFF state, and the margin of GIDL degradation can be secured.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 2내지 도 7은 본 발명에 의한 반도체장치의 트랜지스터 제조방법을 설명하기 위해 순차적으로 도시한 단면도들이다.2 to 7 are cross-sectional views sequentially illustrating a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 2에 도시된 바와 같이 먼저 반도체 기판(10)에 패드산화막(12)과 패드질화막(14)을 증착한 후 STI 가 형성될 부위만 오픈하여 기판을 식각하여 트랜치를 형성하고, 트랜치에 절연막을 매립하여 소자분리막(20)을 형성하고, 평탄화 및 세정공정을 통해 토폴로지를 완화시킨다.As shown in FIG. 2, the pad oxide film 12 and the pad nitride film 14 are first deposited on the semiconductor substrate 10, and then only the portion where the STI is to be formed is etched to form a trench by etching the substrate, and an insulating film is formed in the trench. The buried device isolation layer 20 is formed, and the topology is relaxed through planarization and cleaning processes.
그런다음 도 3과 같이 평탄화된 결과물 전면에 감광막(80)을 도포한 후 채널마스크를 통해 패턴을 형성한 후 300∼500Å 깊이로 식각하여 채널부(30)를 형성한다.Then, after the photoresist film 80 is coated on the entire surface of the flattened product as shown in FIG. 3, a pattern is formed through a channel mask, and the channel portion 30 is formed by etching to a depth of 300 to 500 Å.
이때 채널마스크를 사용하지 않고 게이트마스크를 사용하여 게인을 게이트의 CD보다 200∼400Å 넓게 주어 형성할 수도 있다.In this case, the gate mask may be used to provide a gain 200 to 400 dB wider than the CD of the gate without using a channel mask.
그런다음 도 4와 같이 채널부(30)를 형성한 후 감광막(80)을 제거하고 전면에 채널장벽층(32)을 증착한다.Then, after forming the channel portion 30 as shown in FIG. 4, the photoresist film 80 is removed and the channel barrier layer 32 is deposited on the entire surface.
그런다음 도 5와 같이 채널장벽층(32)을 블랭킷 식각하여 채널부(30)의 내측벽에 채널스페이서(34)를 형성한다.Then, as shown in FIG. 5, the channel barrier layer 32 is blanket-etched to form a channel spacer 34 on the inner wall of the channel part 30.
이후 도 6과 같이 채널스페이서(34)를 형성한 후 채널부(30)에 이온주입을 진행하고 게이트 산화막(42)과, 게이트폴리(44)와 텅스텐실리사이드(46)와질화막(48)을 순차적으로 증착하고 게이트마스크를 통해 식각하여 게이트(40)를 형성한다.Thereafter, as shown in FIG. 6, after the channel spacer 34 is formed, ion implantation is performed in the channel part 30, and the gate oxide film 42, the gate poly 44, the tungsten silicide 46, and the nitride film 48 are sequentially formed. And the gate 40 is formed by etching through the gate mask.
그런다음 도 7과 같이 게이트를(40) 형성한 후 소오스/드레인의 불순물확산역의 졍션부(50)를 형성하고, 게이트스페이서(49)를 형성한다. 그리고 전면에 층간절연막(49)을 층착한 후 랜딩플러그(70)가 형성될 위치에 플러그콘택홀을 형성한다. 그런다음 전면에 플러그폴리막을 SiH4가스와 AsH3가스를 사용하여 증착하여 플러그콘택홀을 매립한 후 CMP 공정을 수행하여 평탄화하여 랜딩플러그(70)를 형성한다.Then, as shown in FIG. 7, the gate 40 is formed, and the section 50 of the source / drain diffusion region is formed, and the gate spacer 49 is formed. After the interlayer insulating layer 49 is deposited on the entire surface, a plug contact hole is formed at a position where the landing plug 70 is to be formed. Then, the plug poly film is deposited on the front surface using SiH 4 gas and AsH 3 gas to fill the plug contact hole, and then planarized by performing a CMP process to form a landing plug 70.
위와 같이 트랜지스터의 채널부(30)를 졍션부(50)보다 깊게 형성하고 채널부(30)의 내측벽에 채널스페이서(34)를 형성함으로써 정션부(50)에서 채널부(30)로 확산되는 도펀트들을 막아 채널길이가 줄어드는 효과가 개선되어 게이트와 졍션사이의 필드를 줄여 GIDL의 누설소스를 차단할 수 있게 된다.As described above, the channel portion 30 of the transistor is formed deeper than the junction portion 50 and the channel spacer 34 is formed on the inner wall of the channel portion 30 to diffuse from the junction portion 50 to the channel portion 30. The effect of reducing channel length by blocking dopants is improved, which reduces the field between the gate and the junction, thus blocking GIDL's leakage source.
또한, 채널부(30)를 정션부(50)보다 하단부에 위치하도록 함으로써 랜딩플러그(70)의 도펀트가 확산되어 채널부(30)까지 도달하는 거리를 멀게하여 문턱전압을 떨어뜨는 문제와, 오프시 흐르는 전류를 증가전류증가 및 GIDL열화 등을 일으키는 요소를 제거하여 트랜지스터 마진을 확보할 수 있게 된다.In addition, by placing the channel portion 30 at the lower portion than the junction portion 50, the dopant of the landing plug 70 is diffused to reach a distance to the channel portion 30 to reduce the threshold voltage, and off The transistor current can be secured by eliminating the factors that increase the current and increase the GIDL degradation.
한편, 랜딩플러그(70)를 형성할 때 P31 보다 분자량이 2배이상 무거운 As 이온을 도펀트로 사용함으로써 후속 열처리 공정시 열확산이 잘 이루어지지 않게 되어 트랜지스터 마진을 확보할 수 있게 된다.On the other hand, when forming the landing plug 70 by using As ions as a dopant having a molecular weight of 2 times or more than P31 as a dopant, it is difficult to thermally diffuse during the subsequent heat treatment process to secure the transistor margin.
상기한 바와 같이 본 발명은 반도체장치의 트랜지스터 제조시 결합누설 감소 및 콘택저항 감소를 위하여 소오스와 드레인의 콘택을 형성하기 위하여 랜딩플러그를 사용하는데 이때 랜딩플러그를 형성할 때 분자량이 무겁고 열확산이 적은 As를 사용할 뿐만 아니라 채널부를 정션부보다 깊게 형성하고 양끝단에 스페이서를 형성하여 랜딩플러그에서 확산되어 채널로 침투되는 현상을 막아 트랜지스터의 문턱전압, 오프 커런트, GIDL열화의 마진을 확보할 수 있는 이점이 있다.As described above, the present invention uses a landing plug to form a contact between a source and a drain in order to reduce coupling leakage and reduce contact resistance when manufacturing a transistor of a semiconductor device. In this case, when the landing plug is formed, As has a high molecular weight and low thermal diffusion. In addition, the channel portion is formed deeper than the junction portion, and spacers are formed at both ends to prevent the diffusion from the landing plug and penetrate into the channel, thereby securing the threshold voltage, off current, and GIDL degradation margin of the transistor. have.
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