KR20030000669A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to improve electrostatic discharge(ESD) by forming a floating junction region while sharing a source region of the first GMOS and a drain region of the second GMOS so that a current path is formed by a consecutive operation of a bipolar transistor. CONSTITUTION: A P-well is formed in the semiconductor substrate. An N-well guard ring(45) is formed outside the P-well. A P-well pickup(41) is formed inside the N-well guard ring. An isolation layer is formed inside the P-well pickup. The first and second GMOS transistors(600,700) share the floating junction region, composed of a drain region(35), the floating junction region(40) and a source region(39) which are formed between the isolation layers.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an antistatic circuit for enhancing electrostatic discharge (ESD) characteristics in a high speed semiconductor device.

Since a semiconductor device is exposed to a phenomenon such as static electricity, when such static electricity is generated and enters the chip, very minute circuits inside the chip may be destroyed or malfunction. Therefore, in the case of a semiconductor device, an antistatic circuit (hereinafter referred to as "ESD") is installed on the signal input path to discharge signals such as static electricity to protect the internal circuit. This ESD, commonly called ESD, is formed between the chip internal circuitry and the pad to which the external input / output pins are connected to prevent product destruction or product degradation by static electricity.

Recently, due to the reduction in chip size due to the high integration of semiconductor devices, the layout area of ESD is also minimized. In addition, as the speed of operation increases, a stacked output buffer which has a low leakage current and a short transistor channel length can be easily controlled without increasing pin capacitance. The structure is used.

However, when the stack output buffer structure is used for ESD, the turn-on time of the ESD circuit is easily configured since the stack output buffer is easily configured to breakdown through two transistors during ESD zapping. The parasitic transistor operation frequently occurs due to a delay of -on time. This causes the ESD level to be lowered.

In order to solve the above problem, the stack output buffer structure is configured by increasing the space between two transistors, increasing the drain area of the GMOS transistor, and increasing the space between the well pick-ups. However, such a structure increases the size of the chip as the parasitic capacitance increases and the layout area also takes up a lot. For this reason, in an integrated circuit requiring high-speed operation, the size of the pin parasitic capacitance is very small, which makes it difficult to solve this problem.

1 to 3 illustrate a semiconductor device according to the prior art, FIG. 1 is an ESD diagram of a series stack structure connected by a first GMOS and a second GMOS, and FIG. 2 is a layout diagram of FIG. 3 is a cross-sectional view illustrating an ESD cut along line AA of FIG. 2.

1 and 2, the antistatic circuit of the series stack structure connected to the drain of the first GMOS 200 and the second GMOS 300 has an N-well guard ring 25 having a predetermined range in a closed curve shape. The second device isolation layer 23, the P-well pickup 21, and the first device isolation layer 13 are disposed in the inner side of the N-well guard ring 25, respectively. The first and second GMOSs 200 and 300 are disposed in the separator 13, respectively, and are spaced apart from the N-well guard ring 25 and connected to a semiconductor circuit (not shown). Is placed.

As shown in FIG. 3, an N-well guard ring 25, a second device isolation film (not shown), a P-well pickup (not shown), and a first device isolation film 13 are disposed in the P-well 11. ), The first GMOS 200, the first device isolation film 13, the second GMOS 300, the first device isolation film 13, the P-well pickup (not shown), and the second device isolation film (not shown) ) And an N-well guard ring 25 are formed.

In addition, first and second GMOSs 200 and 300 are formed between the first device isolation layers 13, respectively, and a pad 200 is connected to the drain region 15 of the first GMOS 200. Vss is connected to the source region 19a of the second GMOS 300.

In this case, in the semiconductor device having the ESD having the series stack structure shown in FIG. 3, a current flows from the pad 100 to the drain region 15, the source region 19, and the second GMOS of the first GMOS 200. It has a main passage flowing to Vss via the drain region 15a and the source region 19a of 300. In addition, since the leakage current is generated through the two first GMOS 200 and the second GMOS 300, the semiconductor device has a small leakage current, thereby reducing the channel length and channel width of the first GMOS 200. By increasing only the channel width of the second GMOS 300, there is an advantage that can facilitate the current regulation without increasing the capacitance.

However, in the semiconductor device having the ESD having the series stack structure, the main current paths of the ESD stacking may include the drain region 15 of the first GMOS, the source region 19 of the first GMOS, NPN parasitic bipolar transistor between the drain region 15 of the first GMOS and the source region 19a of the second GMOS, rather than being formed in the drain region 15a of the second GMOS, and the source region 19a of the second GMOS. (NPN parasitic bipolar transistor) the operation of the current path is made. As a result, an overcurrent flows toward the drain region 15 of the first GMOS, thereby lowering the ESD level.

In addition, during the ESD zapping, a current path is formed through the operation of the NP diode into the drain region 15 and the P-well pickup 21 of the first GMOS, and an overcurrent flows through the drain region 15 of the first GMOS. Will be degraded.

As described above, the semiconductor device having the ESD according to the related art has a problem in that an overcurrent flows in the drain region of the first GMOS during ESD zapping, thereby lowering the ESD level of the semiconductor device and degrading the characteristics and reliability of the semiconductor device. .

Accordingly, the present invention has been made to solve the above problems, and by forming a floating junction region by sharing the source region of the first GMOS and the drain region of the second GMOS, to create a current path by the operation of the continuous bipolar transistor The purpose is to improve ESD.

1 is a circuit diagram showing a general antistatic circuit.

2 is a layout diagram illustrating an antistatic circuit according to FIG. 1.

3 is a cross-sectional view of the antistatic circuit cut along the line A-A shown in FIG.

4 is a layout showing an antistatic circuit according to an embodiment of the present invention.

5 is a cross-sectional view of the antistatic circuit cut along the line A-A shown in FIG.

<Explanation of symbols for the main parts of the drawings>

11, 31: P-well 13, 33: the first device isolation film

15, 15a, 35: drain region 17, 17a, 37, 37a: gate electrode

19, 19a, 39: source region 21, 41: P-well pickup

23, 43: second isolation layer 25, 45: N-well guard ring

40: floating junction area 27, 47: high concentration N-well

100, 500: pad 200, 600: first GMOS

300, 700: second GMOS

The present invention to achieve the above object is a P-well formed in the semiconductor substrate; An N-well guard ring formed outside the P-well; A P-well pickup formed inside the N-well guard ring; An isolation layer formed inside the P-well pickup; And a first transistor and a second transistor formed of a drain region, a floating junction region, and a source region formed between the device isolation layers, and sharing the floating junction region in common.

In addition, the present invention is a guard ring formed in the outermost; A plurality of gate electrodes disposed in the guard ring and separated from each other by a pair of device isolation layers; A floating junction region disposed between the pair of gate electrodes in a pair of gates; A source region disposed at one outer side of the pair of gate electrodes and connected to a pad; And a drain region disposed at the other outer side of the pair of gates and connected to Vss.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the present invention shares the source region of the first GMOS and the drain region of the second GMOS of the conventional stack structure to improve the ESD level while minimizing the parasitic capacitance and the layout of the ESD in the output buffer having the stacked GMOS structure. To form an N + floating junction region, and to generate a current path by continuous NPN parasitic bipolar transistor operation using the N + floating junction region.

4 is a layout diagram of an ESD according to an embodiment of the present invention, Figure 5 is a cross-sectional view of the ESD cut along the line A-A of FIG.

Referring to FIG. 4, an N-well guard ring 45 is disposed in a P-well 31 having a predetermined range in a closed curve shape, and the second device isolation layer 43 is disposed inside the N-well guard ring 45. ), A P-well pick-up 41, and a first GMOS disposed in the order of the first device isolation layer 33 and having the floating junction region 40 commonly connected to each other in the region of the first device isolation layer 33. 600 and a second GMOS 700 are disposed, and a pad 500 is spaced apart from the N-well guard ring 45 and connected to a semiconductor circuit (not shown).

In addition, as shown in FIG. 5, an N-well guard ring 45, a second device isolation film (not shown), a P-well pickup (not shown), and a first device isolation film 33 are interposed therebetween. The drain region 35 of the first GMOS, the gate electrode 37 of the first GMOS, the floating junction region 40, and the second GMOS 700, to which the first GMOS 600 and the second GMOS 700 are commonly connected. Gate electrode 37a and the source region 39 of the second GMOS.

Here, the width of the gate electrode 37 of the first GMOS is formed to be at least 1.0 times the area of the drain region 35 of the first GMOS, and the drain region 35 and the P-well pickup 41 of the first GMOS are formed. The interval of is formed to be at least twice the drain region 35 of the first GMOS. The channel length of the first GMOS 600 is greater than or equal to the channel length of the second GMOS 700.

In addition, a high concentration impurity region 47 is formed in the N-well guard ring 45, a pad 500 is formed in the drain region 35 of the first GMOS 600, and the second GMOS ( Vss is formed in the source region 39 of 700.

During ESD zapping of a semiconductor device having an ESD having a series stack structure as described above, the drain region 35 of the first GMOS, the floating junction region 40, and the source region 39 of the second GMOS are formed from the pad 500. The current path flowing through Vss is formed to prevent the overcurrent from being applied to the drain region 35 of the first GMOS even when a separate bipolar transistor is not formed, thereby improving ESD characteristics.

In addition, when the gate spacing between the first GMOS 600 and the second GMOS 700 decreases, the drain region 35 of the first GMOS and the source region 39 of the second GMOS are removed from the pad 500. A current passage flowing through Vss is formed to prevent overcurrent from being applied to the drain region 35 of the first GMOS. At this time, the level of the gate electrode 37a of the second GMOS can be maintained in the ground state or in the ground state.

According to the present invention, the floating junction region is formed by sharing the source region of the first GMOS and the drain region of the second GMOS, thereby making the current path by the operation of the continuous bipolar transistor to improve the ESD.

Claims (5)

A P-well formed in the semiconductor substrate; An N-well guard ring formed outside the P-well; A P-well pickup formed inside the N-well guard ring; An isolation layer formed inside the P-well pickup; And And a first transistor and a second transistor formed of a drain region, a floating junction region, and a source region formed between the device isolation layers, and sharing the floating junction region in common. The method of claim 1, And the gate electrode width of the first transistor is formed to be at least one times the area of the drain region of the first transistor. The method according to claim 1 or 2, And the gap between the drain region of the first transistor and the P-well pickup is at least twice that of the first drain region. The method of claim 1, And the channel length of the first transistor is greater than or equal to the channel length of the second transistor. Guard ring formed in the outermost; A plurality of gate electrodes disposed in the guard ring and separated from each other by a pair of device isolation layers; A floating junction region disposed between the pair of gate electrodes in a pair of gates; A source region disposed at one outer side of the pair of gate electrodes and connected to a pad; And And a drain region disposed on the other outer side of the pair of gates and connected to Vss.