KR20030000608A - Input buffer circuit - Google Patents

Abstract

PURPOSE: An input buffer circuit is provided to remove an abnormal pulse generated from noise included in an input signal or a ground line by improving a structure of the input buffer circuit. CONSTITUTION: The first and the second PMOS transistors(P11,P22) are serially between a supply voltage(Vcc) and a node(Nd11). The first and the second PMOS transistors(P11,P22) are controlled by an input signal(IN) and a chip selector bar signal(/CS). The first and the second NMOS transistors(N11,N22) are connected in parallel between the node(Nd11) and a ground node. The first and the second NMOS transistors(N11,N22) are controlled by the input signal(IN) and the chip selector bar signal(/CS). The third NMOS transistor(N44) is connected with the node(Nd11) and a drain terminal of the second NMOS transistor(N22). The third NMOS transistor(N44) is controlled by a signal(b1) of the node(Nd11). A buffer portion receives the signal(b1) of the node(Nd11), buffers an inverted signal(b2) of the signal(b1), and outputs the inverted signal(b2) to a node(Nd22). The buffer portion transmits the supply voltage(Vcc) to the node(Nd22) by a pull-up transistor(P33) if the signal(b1) is 'logic low'. In addition, the buffer portion discharges the signal(b2) of the node(Nd22) to a ground line by a pull-down transistor(N33) if the signal(b1) is 'logic high'. A plurality of inverters(I11,I22) are serially between the node(Nd22) and an output node(Nd33). The first and the second inverters(I11,I22) output a delayed signal(b3) to the output node(Nd33). The third inverter(I33) outputs an inverted signal(b3b).

Description

Input buffer circuit {INPUT BUFFER CIRCUIT}

The present invention relates to an input buffer circuit of a semiconductor memory device, and more particularly, to an input buffer circuit capable of eliminating abnormal pulses caused by noise introduced from an input signal or a ground (Vss) line. .

In general, an input buffer circuit of a semiconductor memory device converts a voltage of a TTL level applied from the outside into a CMOS level in accordance with a use environment inside a chip.

1 is a circuit diagram illustrating an input buffer circuit according to the prior art.

As shown in the drawing, in the conventional input buffer circuit, the PMOS transistors P1 and P2 are connected in series between the power supply voltage Vcc and the node Nd1, and the PMOS transistor P1 is connected to the chip selector bar signal ( When / CS) is enabled as 'logic low', the power supply voltage Vcc is transferred to the PMOS transistor P2, and the PMOS transistor P2 is connected to the input signal IN received through the pad PAD. When it becomes 'logic low', the power supply voltage Vcc received through the PMOS transistor P1 is transmitted to the node Nd1.

NMOS transistors N1 and N2 are connected in parallel between the node Nd1 and the ground Vss node, and the NMOS transistor N1 is input signal IN received through the pad PAD. ) Is discharged to the ground (Vss) node when the logic is 'high', the NMOS transistor (N2) when the chip selector bar signal / CS is 'logic high' The signal a1 of the node Nd1 is discharged to the ground Vss node.

And a buffer unit 1 which receives the signal a1 of the node Nd1, buffers the inverted signal a2 of the signal a1, and outputs the buffered signal to the node Nd2. When the signal a1 of the node Nd1 is 'logic low', the buffer unit 1 transmits a power supply voltage Vcc to the node Nd2 by the pull-up transistor P3, and the node Nd1. When the signal a1 is 'logic high', the pulldown transistor N3 discharges the signal a2 of the node Nd2 to the ground line Vss.

In addition, an inverter (I1) (I2) is connected in series between the node (Nd2) and the output node (Nd3), the inverter (I1) (I2) is a signal in which the signal of the node (Nd2) is delayed for a predetermined time ( a3) is output to the output node Nd3.

The inverter I3 receives the signal a2 of the node Nd2 and outputs the inverted signal a3b.

The input buffer circuit operates by an input signal IN received through a pad when the chip selector bar signal / CS is enabled as 'logic low', and the chip selector bar signal / CS is 'logic'. 'High' outputs a logic level 'CMOS' level signal a3 to the output node Nd3 regardless of the received input signal IN.

The output signal a3 of the input buffer circuit is input to an address transition detection circuit ADT (not shown) to generate a signal atd1 which detects an address transition.

2A is a simulation result waveform diagram of a conventional input buffer circuit, and FIG. 2B is an operation timing diagram of a conventional input buffer circuit.

However, in the conventional input buffer circuit configured as described above, as shown in the waveform diagram of the simulation result of FIG. 2A, the input signal IN is abnormal from 0.4V to 1.3V (the threshold voltage values of the PMOS transistor P2 and the NMOS transistor N1). When a glitch signal is applied, the ground node Vss is shaken as shown in FIG. 2A by a bouncy phenomenon, and thus the signal a1 of the node Nd1 swings several times from 1.7V to 1.1V. (swing). As shown in FIG. 2B, the signal a2 of the node Nd2 and the signal a3 of the output node Nd3 generate an unwanted logic high pulse by the signal a1 of the node Nd1. As a result, the address transition detection circuit that receives the signal a3 of the output node Nd3 generates an abnormal address transition detection signal atd1b, resulting in a malfunction of the semiconductor memory device.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to eliminate an abnormal pulse caused by noise introduced from an input signal or a ground (Vss) line. To provide a circuit.

1 is a circuit diagram of an input buffer according to the prior art.

2A is a waveform diagram of simulation results for a conventional input buffer circuit.

2B is an operation timing diagram for a conventional input buffer circuit.

3 is a circuit diagram of an input buffer according to the present invention.

4A is a waveform diagram of a simulation result of a conventional input buffer circuit.

4B is an operation timing diagram for a conventional input buffer circuit.

Explanation of symbols on the main parts of the drawings

11 buffer I11-I33 inverter

P11-P33: PMOS Transistor N11-N44: NMOS Transistor

In order to achieve the above object, the input buffer circuit according to the present invention is the first and second switching unit connected in series between the power supply voltage supply line and the first node and switched by the input signal and the control signal, respectively, A third and fourth switching unit connected in parallel between a first node and a ground line, respectively switched by the input signal and the control signal, and connected between the first node and the fourth switching unit, Characterized in that the capacitor unit for increasing the potential of one node to a certain level.

The control signal may be a chip selector bar signal.

The first and second switching units may be configured as PMOS transistors, respectively.

The third and fourth switching elements are each configured of NMOS transistors.

The capacitor unit is characterized by consisting of MOS transistors.

The MOS transistor is characterized by consisting of an NMOS transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

3 is a circuit diagram showing an input buffer circuit according to the present invention. The input buffer circuit is connected in series between the power supply voltage Vss and the node Nd11 and controlled by the input signal IN and the chip selector bar signal / CS, and the PMOS transistors P11 and P22, NMOS transistors N11 and N22 connected in parallel between the node Nd11 and the ground Vss node and controlled by the input signal IN and the chip selector bar signal / CS, and the node Nd11. And an NMOS transistor N44 connected between the drain terminal of the NMOS transistor N22 and controlled by the signal b1 of the node Nd11 to increase the potential of the node Nd11.

And a buffer unit 11 which receives the signal b1 of the node Nd11, buffers the inverted signal b2 of the signal b1, and outputs the buffered signal to the node Nd22. When the signal b1 of the node Nd11 is 'logic low', the buffer unit 11 transmits a power supply voltage Vcc to the node Nd22 by the pull-up transistor P33, and the node Nd11. If the signal b1 is 'logic high', the pulldown transistor N33 discharges the signal b2 of the node Nd22 to the ground line Vss.

In addition, an inverter (I11) (I22) is connected in series between the node (Nd22) and the output node (Nd33), the inverter (I11) (I22) is a signal in which the signal of the node (Nd22) is delayed for a predetermined time ( b3) is output to the output node Nd33.

In addition, an inverter I33 for receiving the signal b2 of the node Nd22 and outputting the inverted signal b3b is provided.

The input buffer circuit operates by an input signal IN received through a pad when the chip selector bar signal / CS is enabled as 'logic low', and the chip selector bar signal / CS is 'logic'. 'High' outputs a CMOS level signal b3 of 'logic low' to the output node Nd33 regardless of the received input signal IN.

The output signal b3 of the input buffer circuit is input to an address transition detection circuit ADT (not shown) to generate a signal atd2 that detects an address transition.

4A is a simulation result waveform diagram of an input buffer circuit according to the present invention, which is an experimental result when a power supply voltage Vcc of 3V and a temperature of 25 ° C. are applied.

The chip selector bar signal / CS is inputted as 'logic low' and the input signal IN is abnormal as 0.413V (threshold voltage value of PMOS transistor P22 and NMOS transistor N11) at 0.4V as shown in FIG. 4A. When a glitch signal is applied, the ground node Vss is shaken by the bounce phenomenon as shown in FIG. 4A. Accordingly, the signal b1 of the node Nd11 swings several times from 1.9V to 1.5V.

At this time, the NMOS transistor N44 is turned on in the vicinity (1.9V) where the signal b1 of the node Nd11 bounces high to subtract the signal b1 of the node Nd11 to the node Nd44. That is, the logic threshold voltage Vt of the node Nd11 is increased to about 0.3V.

In the conventional case illustrated in FIG. 2A, the signal a1 of the node Nd1 is shaken from 1.7V to 1.1V, whereas in the present invention illustrated in FIG. 4A, the signal b1 of the node Nd11 is It can be seen that it is slightly shaken from about 0.2V to 0.4V. This minimizes the effect on input noise by the NMOS transistor N44 raising the voltage level of the node Nd11.

4B is an operation timing diagram for the input buffer circuit of the present invention.

In FIG. 4B, the signal b2 of the node Nd22 and the signal b3 of the node Nd33 have 'logic low' due to the influence of the signal b1 generated at the node Nd11. Thus, the address transition circuit for inputting this signal b3 outputs a signal atd2b having a 'logic high' potential as shown in Fig. 4B even when an abnormal glitches signal of 1.3V is applied.

In conclusion, in the conventional input buffer circuit, when an abnormal glitch signal is applied at 1.13 V (threshold voltage values of the PMOS transistor P22 and the NMOS transistor N11), the glitches are as shown in FIGS. 2A and 2B. As a result, an abnormal pulse signal is generated at the ground Vss node and the node Nd1 to generate an unwanted signal atd1b in the address transition detection circuit.

However, in the input buffer circuit of the present invention, even when an abnormal signal is applied, the glitches can be removed by increasing the potential of the node Nd11 by the NMOS transistor N44.

As described above, according to the input buffer circuit according to the present invention, it is possible to eliminate abnormal pulses caused by noise introduced from the input signal or the ground (Vss) line.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (6)

In the input buffer circuit, First and second switching units connected in series between the power supply voltage supply line and the first node and switched by an input signal and a control signal, respectively; Third and fourth switching units connected in parallel between the first node and the ground line and switched by the input signal and the control signal, respectively; And a capacitor unit connected between the first node and the fourth switching unit and configured to increase a potential of the first node to a predetermined level. The method of claim 1, And the control signal is a chip selector bar signal. The method of claim 1, And the first and second switching units are each composed of PMOS transistors. The method of claim 1, And the third and fourth switching elements are each composed of NMOS transistors. The method of claim 1, And the capacitor unit comprises a MOS transistor. The method of claim 5, And said MOS transistor is comprised of an NMOS transistor.