KR20030000356A - Method for forming capacitor of semiconductor device using electrochemical etch - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device using electrochemical etching is provided to acquire a capacitor with high-capacitance and reliance of the fabrication process even though the area of a capacitor electrode is reduced and aspect ratio increases. CONSTITUTION: Gate electrodes(13) and a transistor, including source/drain region(14) are formed on a silicon substrate(11). An interlayer dielectrics(15) is formed on the whole surface of the substrate to cover the transistor. A contact hole is made to expose source/drain region by selectively etching a portion of the interlayer dielectrics and a plug(16) for the capacitor is formed by filling up the hole with poly silicon. Single crystal silicon is grown up to the predetermined thickness on the plug for the capacitor and the interlayer dielectrics by selective epitaxial growth. Many holes, with diameter between a few and a thousand nm, are made by electrochemical etching. A storage node(20) with many holes is formed by etching single crystal layer through mask process. A dielectric layer(21) and a plate node(22) are formed on the storage node in succession.

Description

METHODS FOR FORMING CAPACITOR OF SEMICONDUCTOR DEVICE USING ELECTROCHEMICAL ETCH}

The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor lower electrode using an electrochemical etching capable of securing process reliability while ensuring a high capacity.

As the demand for semiconductor memory devices has soared, various techniques for obtaining high capacity capacitors have been proposed. The capacitor is a structure in which a dielectric film is interposed between a capacitor lower electrode and an upper electrode, called a storage node and a plate node, respectively, and the capacitance of the capacitor is defined by the surface area of the electrode, in particular, the surface area of the lower electrode and the dielectric film. It is proportional to the dielectric constant and inversely proportional to the distance between the electrodes. Therefore, in order to obtain a high capacity capacitor, it is essential to use a dielectric film having a high dielectric constant, to enlarge the surface area of the electrode, or to reduce the distance between the electrodes.

However, reducing the distance between the electrodes, that is, the thickness of the dielectric film has a limitation. In order to manufacture a high capacity capacitor, it is preferable to use a dielectric film having a high dielectric constant or to use a method of increasing the surface area of the electrode. Do.

In the current technology trend, using a tantalum oxide film (Ta ₂ O ₅ ) as the material of the dielectric film is an example of increasing the capacitor capacity through the increase in the dielectric constant. In addition, forming a capacitor lower electrode with a three-dimensional structure such as a fin structure, a stack structure, and a cylinder structure is an example of increasing the capacitor capacity through an increase in the electrode surface area.

Among the above structures, since the cylinder structure has an advantage of securing a large electrode area by a relatively simple process, most capacitors are manufactured in the above-described cylinder structure, and moreover, in recent years, MPS is applied to the lower electrode of the cylinder structure. The technique of maximizing the electrode surface area by applying a (Meta-stable Poly Silicon) process is becoming popular.

1 is a cross-sectional view showing a conventional storage node formed through the MPS process, as shown, the capacitor lower electrode 10 is made of a polysilicon material, is formed in a cylindrical shape. In addition, after the formation, through the crystal growth on the surface by heat treatment, HSG (Hemi Spherical Grain) -Si (5) is formed on the surface, thereby maximizing the surface area. Unexplained reference numeral 1 denotes a silicon substrate, 2 an impurity diffusion region, 3 an interlayer insulating film, and 4 denotes a capacitor plug.

However, despite the application of the above-described technology, the capacitor formation area is reduced according to the high integration of the semiconductor device, which causes a problem in that it is difficult to obtain a capacitor having a uniform shape and high capacity in the conventional capacitor structure and method.

In addition, although the capacitor formation area is secured by increasing the height of the capacitor, in this case, another problem that it is difficult to secure process reliability due to an increase in the aspect ratio.

Accordingly, an object of the present invention is to provide a method for forming a capacitor of a semiconductor device capable of securing a high capacity, despite the reduction of the capacitor formation surface, which is devised to solve the above problems.

Another object of the present invention is to provide a method of forming a capacitor of a semiconductor device capable of securing process reliability despite an increase in the aspect ratio.

1 is a cross-sectional view showing a capacitor lower electrode formed according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a capacitor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 silicon substrate 12 gate oxide film

13 gate electrode 14 source / drain region

15: interlayer insulating film 16: plug for capacitor

17 silicon single crystal layer 18 groove

20 capacitor lower electrode 21 dielectric film

22 capacitor upper electrode 30 capacitor

Capacitor forming method of the present invention for achieving the above object comprises the steps of providing a silicon substrate having a transistor including a gate electrode and a source / drain region formed thereon; Forming an interlayer insulating film having a capacitor plug in contact with the source / drain region on a silicon substrate including the transistor; Forming a silicon single crystal layer with a predetermined thickness on the capacitor plug and the interlayer insulating film; Electrochemically etching the silicon single crystal layer to form several grooves on the surface thereof; Patterning a silicon single crystal layer having several grooves formed on the surface to form a capacitor lower electrode; And sequentially forming a dielectric film and a capacitor upper electrode on the capacitor lower electrode.

Here, the step of electrochemically etching the silicon single crystal layer, any one of 1 to 5V while immersing the silicon substrate on which the silicon single crystal layer is formed in a reaction tube containing a solution of HF and ethanol mixed in a volume ratio of 1: 1. It is made by constantly applying one voltage, and the groove is formed to have a diameter of several nm to several thousand nm.

According to the present invention, by performing an electrochemical etching on the silicon single crystal layer, several grooves having a diameter of several nm to several thousand nm can be formed on the surface of the silicon single crystal layer, and therefore, a capacitor having a high capacity is very easily Can be formed.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating processes of forming a capacitor according to an embodiment of the present invention.

First, as shown in FIG. 2A, a transistor including a gate electrode 13 having a gate oxide film 12 and a source / drain region 14 is formed on a silicon substrate 11, and then the transistor is formed. An interlayer insulating film 15 is formed on the entire surface of the silicon substrate 11 to cover the gap. Subsequently, a portion of the interlayer insulating layer 15 is selectively etched to form a contact hole exposing the source / drain region 14, and a conductive film, for example, a polysilicon film is embedded in the contact hole to form a plug for a capacitor. 16).

Next, as shown in FIG. 2B, the silicon single crystal layer 17 is grown to a predetermined thickness on the capacitor plug 16 and the interlayer insulating layer 15 through a selective epitaxial growth process.

Then, as shown in FIG. 2C, the silicon single crystal layer 17 is electrochemically etched to form several grooves 18 having a diameter of several nm to several thousand nm on the surface thereof. .

Here, the electrochemical etching of the silicon single crystal layer 17 is a state in which the resultant product of the silicon single crystal layer 17 is immersed in a reaction tube containing a solution in which HF and ethanol are mixed at a volume ratio of 1: 1. By applying a constant voltage of any one of 1 to 5V. For electrochemical etching of single crystal silicon, see LT canham, Appl. Lett 56, 1056 (1990).

Next, as shown in FIG. 2D, the single crystal silicon layer is etched through a known mask process to form a capacitor lower electrode 20 having several grooves 18 on the surface thereof. Then, the dielectric film 21 and the capacitor upper electrode 22 are sequentially formed on the capacitor lower electrode 20, and as a result, the capacitor 30 according to the present invention is completed.

The capacitor according to the present invention, which is formed through the above process, forms a silicon single crystal layer as a material for the lower electrode, and forms a capacitor lower electrode having a maximum surface area only by performing electrochemical etching on the silicon single crystal layer. Can be.

Therefore, by using the method of the present invention, despite the reduction in the capacitor formation area, it is possible to ensure a high capacity of the desired degree even in a small volume, in particular, it is possible to ensure the process reliability because of easy control in the process do.

On the other hand, in forming the capacitor lower electrode having a porous surface, since electrochemical etching is possible only in the silicon single crystal layer, the use of the silicon single crystal layer as the material for the capacitor lower electrode must be accompanied.

As described above, the present invention forms a capacitor lower electrode having a maximum surface area through the electrochemical etching of the silicon single crystal layer, so that a capacitor having a high capacity can be formed very easily despite the reduction of the capacitor formation area. In addition, since the process control is easy, process reliability and reproducibility can be improved.

As a result, by using the method of the present invention, a high capacity memory device can be manufactured very easily and reliably.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Providing a silicon substrate having a transistor formed thereon including a gate electrode and a source / drain region; Forming an interlayer insulating film having a capacitor plug in contact with the source / drain region on a silicon substrate including the transistor; Forming a silicon single crystal layer with a predetermined thickness on the capacitor plug and the interlayer insulating film; Electrochemically etching the silicon single crystal layer to form several grooves on the surface thereof; Patterning a silicon single crystal layer having several grooves formed on the surface to form a capacitor lower electrode; And And sequentially forming a dielectric film and a capacitor upper electrode on the capacitor lower electrode. The method of claim 1, wherein the etching of the silicon single crystal layer electrochemically comprises: immersing the silicon substrate on which the silicon single crystal layer is formed in a reaction tube containing a solution in which HF and ethanol are mixed at a volume ratio of 1: 1. A method for forming a capacitor of a semiconductor device, characterized by applying a constant voltage of -5V. The method of claim 1, wherein the groove is formed to have a diameter of several nm to several thousand nm.