KR200296152Y1 - clock observing device of the transmission system - Google Patents

Abstract

According to the present invention, a first asynchronous counter outputs a clock comparison pulse by counting a clock signal of a transmission board providing a reference clock during clock monitoring based on a reference latch value, and a reference latch of a clock signal of a transmission board requiring clock monitoring. Comparing the second asynchronous counter counting the value based on the value and outputting a clock comparison pulse with each clock comparison pulse signal inputted from the first asynchronous counter and the second asynchronous counter to determine whether the monitored clock signal is in error. Provides a clock monitoring value of a transmission system consisting of a clock comparison module unit.

The present invention as described above comprises a counter means capable of counting a reference and a watched clock, respectively, and a clock comparison module that compares a plurality of clock signals outputted from the counter means to determine whether there is an error. The error can be determined using the comparison count clock signal, so the board clock monitoring efficiency can be maximized and the error of the monitoring clock signal to be compared can be accurately determined through the counter. This greatly improves the accuracy of board clock monitoring.

Description

Clock observing device of the transmission system

The present invention relates to a clock monitoring apparatus of a transmission system, and more particularly, comprising a counter means capable of counting reference and monitoring clocks respectively and a clock comparison module for comparing an error by comparing a plurality of clock signals output from the counter means. The present invention relates to a clock monitoring apparatus of a transmission system.

In general, the transmission technology began with the spiral carrier in the 1910s, developed into the analog transmission technology, and in the form of the digital transmission technology. Later, the digital transmission technology has been developed since the 1960s with the development of the DS1 channel bank with a 1.544Mbps transmission rate. It was. Moreover, such digital technology has been applied to the field of exchange technology in the mid-1970s. It has revolutionized the multiplexing of wired transmission systems by introducing the digital relay switch called 4ESS. In addition, the digital transmission method has been developed into an optical transmission method using an optical cable as a transmission medium. Currently, the digital transmission method is changing from an asynchronous PDH transmission system to a synchronous SDH transmission system.

However, such transmission systems, in particular, a digital cross-connect system (DCS) generally includes a clock generation circuit for synchronizing signals transmitted between nodes, for example, between exchanges or within nodes. In this clock generation circuit, a phase locked loop (PLL) is usually formed. The phase locked loop is designed in an analog manner, called a PDH (PLESIOCHRONOUS DIGITAL HIERARCHY) method, while the digital synchronization method is SDH (SYNCHRONOUS) It is called DIGITAL HIERARCHY) method. Recently, a digitally designed SDH device is widely used, and the DCS device of such a transmission system includes an offset detection device for offset detection of a reference clock signal input from the outside for signal synchronization in a feedback manner. Therefore, each of the hierarchical devices such as the SDH or PDH, for example, the transmission boards have a built-in device that monitors the internal clock to check whether the internal device is operating normally.

Then, referring to the clock monitoring value of the conventional transmission system as described with reference to Figure 1, the reference transmission board 70 for generating a system clock signal for implementing the function of the set system, and synchronized with the system clock signal The watch transmission board 71 that generates a self-clock signal required by the board, and a clock error discrimination unit that compares each clock signal input from the reference transmission board 70 and the watch transmission board 71 to determine an error ( 72).

In addition, the monitoring transmission board 71 PLL processes the clock signal generated by the clock generator 73 and the clock signal generated by the clock generator 73 by using the input frequency. PLL section 74 for generating a clock is included.

On the other hand, referring to the operation of the clock monitoring apparatus of the conventional transmission system as described above, first, the clock error determination unit 72 monitors the clock signal between each board for the normal operation of the system, at this time, the monitoring transmission to be monitored The clock generator 73 of the board 71 generates the set clock signal and outputs it to the PLL unit 74. Then, the PLL unit 74 converts the clock signal inputted from the clock generator 73 into the clock signal necessary for the board 71 by using the input frequency, and supplies it to the corresponding board 71 and at the same time the corresponding clock signal. The signal is output to the clock error discrimination unit 72.

Accordingly, the clock error discrimination unit 72 compares the clock signal of the monitoring target input from the monitoring transmission board 71 with the system clock signal serving as the reference input from the reference transmission board 70 to perform error discrimination. .

For example, as illustrated in FIG. 2, the clock error discrimination unit 72 has a clock signal (clock A) of the reference transmission board 70 and a clock signal (clock B) of the monitoring transmission board 71 as a comparison target. If the same and different phase, the clock signal (clock B) of the monitoring transmission board 71 is divided by two and compared. At this time, when reading the clock signal (clock B), which is divided using the rising edge of the clock signal (Clock A) of the monitoring transmission board 71, once high is normal, and then LOW will be read. This means that the clock signal of the transmission board 71 to be monitored is normally converted to high and low, so that the clock error discrimination unit 72 processes this normally. However, when the clock signal (clock B) to be monitored disappears in the middle, as shown in FIG. 3, the clock error discrimination unit 72 continuously reads the value of clock B low, thereby performing error processing.

Further, in the clock error discrimination unit 72, when monitoring the case where the phases are the same and the frequencies are different, for example, when the low frequency (clock B) monitors the high frequency (clock A), the high frequency is lower than the low frequency. The frequency can be divided and monitored. That is, the clock A is divided into eight and the frequency of the clock A is converted to a frequency lower than the frequency of the clock B. Then, the clock A can be monitored as described above.

However, the clock monitoring value of the conventional transmission system as described above can be monitored because the number of clocks in which the trigger occurs within a predetermined time is constant when any one of the frequency and phase of the clock signal to be compared is the same. If the frequency and phase of the clock signal to be compared are all different, the clock signal cannot be monitored at all, which causes a problem of significantly lowering the clock synchronization characteristic of the transmission board.

Therefore, the present invention is designed to solve the above-mentioned problems. Since the error can be determined by using a clock clock signal having a different frequency and phase, the transmission clock maximizes the efficiency of the board clock monitoring accordingly. The purpose is to provide a clock monitoring value for the system.

In addition, another object of the present invention is to provide a clock monitoring value of a transmission system that can accurately determine the error of the monitoring clock signal to be compared through a counter, thereby significantly improving the accuracy of the board clock monitoring.

The present invention for achieving the above object is a first asynchronous counter for outputting a clock comparison pulse by counting the clock signal of the transmission board providing a reference clock during the clock monitoring based on the reference latch value, and the clock monitoring is required The second asynchronous counter which counts the clock signal of the transmission board based on the reference latch value and outputs a clock comparison pulse, and compares each clock comparison pulse signal inputted from the first asynchronous counter and the second asynchronous counter to be monitored. Provided is a clock monitoring value of a transmission system comprising a clock comparison module unit for determining whether or not an error of a clock signal occurs.

1 is an explanatory diagram illustrating a clock monitoring value of a conventional transmission system.

2 and 3 are explanatory diagrams for explaining a monitoring waveform applied to the apparatus of FIG.

4 is an explanatory diagram illustrating a clock monitor value of the present invention.

5 (a) to 5 (b) are explanatory diagrams for explaining a clock signal provided to the apparatus of FIG. 4;

(c) is explanatory drawing explaining the reference latch value of the 1st asynchronous counter of the apparatus of FIG.

(d) is explanatory drawing explaining the clock comparison pulse of the 1st asynchronous counter of the apparatus of FIG.

(e) is explanatory drawing explaining the asynchronous load pulse of the 1st asynchronous counter of the apparatus of FIG.

(f) is explanatory drawing explaining the reference latch value of the 2nd asynchronous counter of the apparatus of FIG.

<Detailed Description of Codes>

1: transfer board 2: first asynchronous counter

3: transmission board 4: second asynchronous counter

5: Clock comparison module

Hereinafter, the present invention will be described in detail based on the accompanying drawings.

The apparatus of the present invention counts a clock signal of a transmission board 1 that provides a reference clock during clock monitoring based on a pre-defined latch value, and thus a clock compare pulse. A clock compare pulse by counting a clock signal of the first asynchronous counter 2 and a transmission signal 3 requiring the clock monitoring based on a pre-defined latch value. Comparing the second asynchronous counter 4 outputting a clock signal with each clock comparison pulse signal inputted from the first asynchronous counter 2 and the second asynchronous counter 4 to determine whether an error of the monitored clock signal is detected. It consists of a clock comparison module unit (5).

In addition, an output terminal of the first asynchronous counter 2 is connected to one end of the first asynchronous counter 2 and the second asynchronous counter 4 to receive an asynchronous load pulse for reset.

Here, the reference latch values of the first asynchronous counter 2 and the second asynchronous counter 4 are frequency values already known by the system developer.

Next, the operation and effects of the present invention as described above will be described.

First, the value of the first asynchronous counter 2 and the second asynchronous counter 4 of the device of the present invention increases by one for each trigger time of the input clock, and counts regardless of the trigger of the input clock when an asynchronous load pulse is input. Reset the value to zero.

When the clock comparison pulse of the first asynchronous counter 2 is present, the clock comparison module unit 5 outputs an error discrimination signal with respect to the clock signal of the second asynchronous counter 4. The unit 5 determines that the error is not the pulse value according to the reference latch value of the second asynchronous counter 4 when the clock comparison pulse of the first asynchronous counter 2 is high.

For example, a clock output terminal (clock A) of the transmission board 1 that generates a system clock signal as a reference is connected to an input terminal of the first asynchronous counter 2, as shown in FIG. The clock output terminal (clock B) of the transmission board 3, which requires monitoring, is connected to the input terminal of the second asynchronous counter 4 as shown in FIG.

At this time, the clock comparison module unit 5 presets each pulse value according to the reference latch value of the first asynchronous counter 2 and the second asynchronous counter 4.

For example, it is assumed that the reference latch value of the first asynchronous counter 2 is set to "C" and the reference latch value of the second asynchronous counter 4 is set to "2" as shown in FIG. When monitoring the clock output from the transmission board (1, 3) respectively

The first asynchronous counter 2 and the second asynchronous counter 4 count clock signals respectively inputted from the respective transmission boards 1 and 3 until the reference latch values "C" and "2" are reached. When the respective reference latch values are reached, the first asynchronous counter 2 and the second asynchronous counter 4 generate clock comparison pulses and output the clock comparison pulses to the clock comparison module unit 5.

At this time, when the count output value of the second asynchronous counter 4 to be monitored is normal, the clock comparison module unit 5 inputs the clock comparison pulse value of the first asynchronous counter 2 as "C". In this case, "2" is inputted, and these two values are compared and judged as normal.

However, when the clock comparison pulse value of the first asynchronous counter 2 is input as "C", as shown in (c) and (d) of FIG. When the clock comparison pulse value of the second asynchronous counter 4 is not input as "2" as shown in FIG. 5 (f) but is input to other values such as 0, 1 and 3, the second asynchronous counter 4 It is determined that an abnormality has occurred in the clock of the transmission board (3) inputted at) and outputs an error generation signal.

On the other hand, the first asynchronous counter 2 generates a "high signal" as shown in FIG. 5E at the rising time immediately after the clock comparison pulse signal is "C", that is, the "high signal" is generated. To the first asynchronous counter 2 and the second asynchronous counter 4 using an asynchronous load pulse. Then, the first asynchronous counter 2 and the second asynchronous counter 4 are reset regardless of whether the clock is input and then start counting again.

Therefore, according to the present invention as described above, even if the phase or frequency of the clock to be compared does not match each other, it becomes possible to monitor the clock.

Here, the reference latch value of the second asynchronous counter 4 should always be set to a value less than or equal to the reference latch value of the first asynchronous counter 2. The reason is that the reference latch value of the second asynchronous counter 4 should always have a value equal to or less than the reference latch value of the first asynchronous counter 2. This is because the first asynchronous counter 2 and the second asynchronous counter 4 can be reset.

As described above, the present invention includes a counter means capable of counting a reference and a watched clock, respectively, and a clock comparison module that compares a plurality of clock signals outputted from the counter means to determine whether there is an error. Different clock signals can be distinguished by using the comparison count clock signal, which has the advantage of maximizing the efficiency of the board clock monitoring.

In addition, according to the present invention, since the error of the monitoring clock signal to be compared can be accurately determined by the counter, the accuracy of the board clock monitoring can be improved accordingly.

Claims (2)

A first asynchronous counter that counts a clock signal of a transmission board providing a reference clock during clock monitoring based on a reference latch value and outputs a clock comparison pulse; and a clock signal of the transmission board requiring clock monitoring based on a reference latch value A clock comparison module which compares a second asynchronous counter for outputting a clock comparison pulse with each clock comparison pulse signal inputted from the first asynchronous counter and the second asynchronous counter and determines whether an error of the monitored clock signal is present; Clock monitoring device of a transmission system, characterized in that consisting of. 2. The clock monitoring apparatus of claim 1, wherein the reference latch value of the second asynchronous counter is always set equal to or less than the reference latch value of the first asynchronous counter.