KR200288567Y1 - Reference Clock Receiving Device in Electronic Switching System - Google Patents

Abstract

The present invention relates to a reference clock receiving apparatus in an electronic switching system, and in particular, a receiving port is allocated to receive a clock supplied from a DOTS and a satellite positioning system in addition to a receiving port of a clock input through a digital interface. The present invention relates to a reference clock receiving apparatus in an all-electronic switch that enables the clock to be diversified.

Since the reference clock receiving apparatus in the conventional all-electronic switch is only capable of clock signals through the digital interface unit, in order to receive the clock signal supplied from other equipment, the other terminal may be manufactured after removing the port received through the corresponding digital interface unit. There is a problem that must be used.

The present invention diversifies the reference clock signal by adding a port for receiving the reference clock signal from the DOTS and the standard clock signal from the GPS in addition to the port for receiving the reference clock signal through the digital interface. Electronic switchboards can also be used when constructing digital communication networks using DOTS or GPS.

Description

Reference Clock Receiving Device in Electronic Switching System

The present invention relates to a reference clock receiving apparatus in an electronic switching system, and in particular, a receiving port is allocated to receive a clock supplied from a DOTS and a satellite positioning system in addition to a receiving port of a clock input through a digital interface. The present invention relates to a reference clock receiving apparatus in an all-electronic switch that enables the clock to be diversified.

In general, network synchronization is to synchronize the frequency of each country in the network to handle the timing slot exchange of the switching or transmitting end station, the branch insertion of the circuit in the digital network, there are independent synchronization, dependent synchronization, mutual synchronization.

The reference clock receiving apparatus in the conventional all-electronic exchange includes a digital interface unit 11, a clock receiving unit 12, a clock selector 13, a frequency divider circuit 14, and a phase locked as shown in FIG. Loop) circuit section 15 is provided.

The digital interface unit 11 transmits and receives a signal as an interface with a digital relay line and uses a digital T1 interface (DTI) or a digital CEPT interface (DCI). DTI directly controls T1 type digital relay line to perform signal transmission / reception and operation state monitoring and test. DCI directly controls CEPT type digital relay line to transmit / receive signal and operation state monitoring and test. do.

The clock receiver 12 receives a clock signal applied through the digital interface 11 and applies the clock signal to the clock selector 13, and the clock selector 13 is a reference among the clock signals applied from the clock receiver 12. One clock signal to be used as the clock signal is selected and applied to the division circuit unit 14.

The frequency divider circuit 14 divides the clock signal applied from the clock selector 13 to generate a clock signal having a predetermined period (4Khz) and applies the clock signal to the PLL circuit portion 15. The PLL circuit portion 15 divides the clock signal 14. Determining the phase difference between the clock signal applied from the oscillator and the oscillation output of the voltage controlled oscillator to determine the frequency, phase of the voltage controlled oscillator to generate a clock synchronized with the clock signal and transmit it to use as a reference clock signal.

Since the reference clock receiving apparatus in the conventional all-electronic switch as described above can only use the clock signal through the digital interface unit, in order to receive the clock signal supplied from other equipment, the port received through the corresponding digital interface unit is removed, and then the other. There is a problem that a transmission path must be manufactured and used.

The present invention has been made to solve the above-described problems, and an object thereof is to receive a PCM signal from DOTS and a standard clock signal from GPS in addition to a port for receiving a reference clock signal through a digital interface in an electronic switchboard. By adding a number of ports, the reference clock signal can be diversified to enable the use of an electronic switch in the construction of a digital communication network using DOTS or GPS.

A feature of the present invention for achieving the above object is a reference clock receiving apparatus in an electronic switch, comprising: a PCM signal receiving unit (27) for receiving a PCM signal applied from the DOTS (26); A first selection circuit section (28) for selecting one of the PCM signals applied from the PCM signal receiving section (27) to be used as a reference clock signal; A second dividing circuit portion 29 for dividing the PCM signal applied from the first selecting circuit portion 28 to generate a clock signal of a predetermined period; A second selection circuit section 30 for selecting one clock signal to be used as a reference clock signal from a clock signal applied from the PLL circuit section 25 and a clock signal applied from the second division circuit section 29; A standard clock receiver 32 for receiving a standard clock signal generated by the GPS 31; A third selection circuit section (33) for selecting a standard clock signal from one of the standard clock signals applied from the standard clock receiving section (32); A third divider circuit part 34 for dividing a standard clock signal applied from the third selector circuit part 33 to generate a clock signal of a predetermined period; Select one clock signal to be used as a reference clock signal from the clock signal applied from the second selection circuit unit 30 and the clock signal applied from the fourth selection circuit unit 35 to use as a reference clock signal in the all-electronic exchange. And a fourth selection circuit section 35 for transmitting.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a configuration of a reference clock receiving apparatus in a conventional all-electronic exchange.

2 is a block diagram of a reference clock receiving apparatus in an all-electronic exchange according to the present invention;

Explanation of symbols on the main parts of the drawings

11, 21: digital interface unit 12, 22: clock receiving unit

13, 23: clock selector 14: frequency divider circuit

15, 25: PLL circuit section 24: first division circuit section

26: DOTS (Digital Office Timing System) 27: PCM Signal Receiver

28: first selection circuit portion 29: second division circuit portion

30: second selection circuit 31: satellite positioning system

32: standard clock receiver 33: third selection circuit portion

34: third division circuit section 35: fourth selection circuit section

Hereinafter, with reference to the accompanying drawings, an embodiment of the present invention in detail as follows.

As shown in FIG. 2, the reference clock receiving apparatus in the all-electronic switch according to the present invention includes the digital interface 21, the clock receiving unit 22, the clock selecting unit 23, and the first division circuit unit 24. , PLL circuit section 25, DOTS (Digital Office Timing Supply), PCM signal receiving section 27, first selection circuit section 28, second division circuit section 29, second selection circuit section 30, GPS ( 31; a Global Positioning System), a standard clock receiver 32, a third select circuit 33, a third divider 34, and a fourth select circuit 35.

The digital interface unit 21 uses DTI or DCI to perform transmission and reception of signals and tests as an interface with a digital relay line. DTI directly controls T1 type digital relay line to perform signal transmission / reception and operation state monitoring and test. DCI directly controls CEPT type digital relay line to transmit / receive signal and operation state monitoring and test. do.

The clock receiver 22 receives a clock signal applied through the digital interface 21 and applies the clock signal to the clock selector 23. The clock selector 23 is a reference among the clock signals applied from the clock receiver 22. One clock signal to be used is selected and applied to the first frequency divider circuit 24.

The first frequency divider circuit 24 divides the clock signal applied from the clock selector 23 to generate a clock signal having a predetermined period (4Khz) and apply the clock signal to the PLL circuit portion 25, and the PLL circuit portion 25 has a design accuracy. An oscillation circuit having an arbitrary frequency is formed, and the phase difference between the clock signal applied from the first frequency division circuit section 24 and the oscillation output of the voltage controlled oscillator is detected to determine the frequency and phase of the voltage controlled oscillator to synchronize with the clock signal. The clock is generated and applied to the second selection circuit unit 30.

The DOTS 26 generates a PCM signal and applies it to the PCM signal receiver 27, and the PCM signal receiver 27 receives a PCM signal applied from the DOTS 26 and applies it to the first selection circuit 28.

The first selection circuit unit 28 selects one of the PCM signals from the PCM signal receiving unit 27 to be used as a reference clock signal and applies the PCM signal to the second division circuit unit 29, and the second division circuit unit 29. Divides the PCM signal applied from the first selection circuit section 28 to generate a clock signal of a predetermined period (4Khz) and applies it to the second selection circuit section 30.

The second selection circuit section 30 selects one clock signal to be used as a reference clock signal from the clock signal applied from the PLL circuit section 25 and the clock signal applied from the second division circuit section 29, and thereby selects the fourth selection circuit section 35. GPS 31 is a receiver that can know the time, location, speed, and information using satellites. In particular, the GPS 31 can calculate the exact position of various moving objects by continuously using accurate time signals. The reception strength can be measured accurately, and a standard clock (100Mhz) is generated and applied to the standard clock receiver 32.

The standard clock receiver 32 receives a standard clock signal generated by the GPS 31 and applies it to the third select circuit 33, and the third select circuit 33 is a standard applied from the standard clock receiver 32. One of the clock signals to be used as the reference clock signal is selected and applied to the third frequency divider circuit 34.

The third division circuit unit 34 divides the standard clock signal applied from the third selection circuit unit 33 to generate a clock signal having a predetermined period (4Khz) and applies it to the fourth selection circuit unit 35, and the fourth selection circuit unit 35. Reference numeral 35 selects one clock signal to be used as a reference clock signal from a clock signal applied from the second selection circuit section 30 and a clock signal applied from the fourth selection circuit section 35, and selects one clock signal from the electronic switch as a reference clock signal. Send to use.

As described above, the present invention provides a reference clock signal by adding a port capable of receiving a PCM signal from DOTS and a standard clock signal from GPS in addition to a port for receiving the reference clock signal through the digital interface in the electronic switchboard. By diversifying the digital communication network using DOTS or GPS, it is possible to use the electronic switchboard.

Claims (1)

In the reference clock receiving apparatus in the all-electronic switch, A PCM signal receiver 27 for receiving a PCM signal applied from the DOTS 26; A first selection circuit section (28) for selecting one of the PCM signals applied from the PCM signal receiving section (27) to be used as a reference clock signal; A second dividing circuit portion 29 for dividing the PCM signal applied from the first selecting circuit portion 28 to generate a clock signal of a predetermined period; A second selection circuit section 30 for selecting one clock signal to be used as a reference clock signal from a clock signal applied from the PLL circuit section 25 and a clock signal applied from the second division circuit section 29; A standard clock receiver 32 for receiving a standard clock signal generated by the GPS 31; A third selection circuit section (33) for selecting a standard clock signal from one of the standard clock signals applied from the standard clock receiving section (32); A third divider circuit part 34 for dividing a standard clock signal applied from the third selector circuit part 33 to generate a clock signal of a predetermined period; Select one clock signal to be used as a reference clock signal from the clock signal applied from the second selection circuit unit 30 and the clock signal applied from the fourth selection circuit unit 35 to use as a reference clock signal in the all-electronic exchange. And a fourth selection circuit section (35) for transmitting.