KR200252734Y1 - Feedback circuit - Google Patents

Abstract

The present invention relates to a feedback circuit, and the conventional feedback circuit has a problem in that its output is changed by noise. In consideration of such a problem, the present invention provides a feedback circuit in which a source side signal of an NMOS transistor or a PMOS transistor is inverted through an inverter and applied to a gate of the NMOS transistor or PMOS transistor. The drain and gate of the PMOS transistor are commonly connected to the output side connection point of the inverter, and when the source side voltage of the NMOS transistor PMOS transistor is changed by noise by increasing the conversion region of the inverter, the output voltage is It is less susceptible to noise and increases stability.

Description

Feedback circuit

The present invention relates to a feedback circuit, and more particularly to an inverter type feedback circuit with increased amplification and stability.

In the conventional feedback circuit, as shown in FIGS. 1A and 1B, the signal of the source S side of the NMOS transistor NM or the PMOS transistor PM is applied to the inverter I. It is configured to be inverted through and applied to its gate G, and the operation of the feedback circuit configured as described above will be described in detail.

First, in the feedback circuit diagram consisting of the NMOS transistor NM and the inverter I shown in FIG. 1A, it is assumed that the voltage at the source S side of the NMOS transistor NM is rising to high potential. The voltage applied to the gate G of the NMOS transistor NM by the inverter I which inverts the source S side signal of the NMOS transistor NM becomes a low potential so that the NMOS transistor ( NM) is turned off. Accordingly, the voltage of the source S side of the NMOS transistor NM decreases to a low potential. When the voltage of the source S side of the NMOS transistor NM approaches the low potential as described above, the voltage applied to the gate G through the inverter I becomes a high potential and the NMOS transistor in the off state. Turn on (NM). As a result, the voltage on the source S side of the NMOS transistor NM increases to a high potential again.

Also, the feedback circuit of FIG. 1 (b) is operated similarly to the feedback circuit of FIG. 1 (a). That is, assuming that the voltage of the source S side of the PMOS transistor PM rises to high potential, the voltage applied to the gate G of the PMOS transistor PM through the inverter I becomes low potential. As the PMOS transistor PM is turned on, the voltage of the source S side drops to low potential. In this manner, as the source S side voltage approaches the low potential, the voltage applied to the gate G through the inverter I becomes high potential, thereby turning off the conducting PMOS transistor PM. The source S side voltage again increases to high potential.

As described above, the output voltage of the inverter applied to the gates of the NMOS transistor and the PMOS transistor has an arbitrary constant bias as shown in FIG. 3 (a).

However, the conventional feedback circuit described above has a problem in that the inverter does not operate normally because the conversion area of the inverter is narrow, affecting the output of the inverter when the voltage change on the source side is caused by noise.

The present invention in view of the above problems is an object of the present invention to provide a feedback circuit that operates normally even when the voltage on the source side changes due to noise.

1 is a conventional feedback circuit diagram.

2 is a feedback circuit diagram according to the present invention.

3 is a diagram showing characteristics of an inverter in FIGS. 1 and 2;

* Explanation of symbols for main parts of the drawings

NM1: NMOS transistor PM1 to PM2: PMOS transistor

I1: Inverter

The object of the present invention as described above is achieved by connecting a PMOS transistor subjected to conduction control by the output signal of the inverter to the output side of the inverter, thereby widening the conversion region of the inverter, which will be described in detail with reference to the accompanying drawings. The explanation is as follows.

2 (a) and 2 (b) are feedback circuit diagrams according to the present invention, and as shown therein, the signal of the source S1 side of the NMOS transistor NM1 or PMOS transistor PM1 is the inverter I1. In the feedback circuit inverted through the NMOS transistor NM1 or the gate G1 of the PMOS transistor PM1, the PMOS transistor PM2 to which the power supply voltage VCC is applied to the source S2 is applied. The drain D2 and the gate G2 are commonly connected to the output side connection point of the inverter I1. The operation of the feedback circuit according to the present invention configured as described above will be described in detail as follows.

First, in the feedback circuit composed of the NMOS transistor NM1, the inverter I1, and the PMOS transistor PM2 shown in FIG. 2 (a), the voltage on the source S1 side of the NMOS transistor NM1 is Assuming that the potential is reduced to low potential, voltages applied to the gates G1 and G2 of the NMOS transistor NM1 and the PMOS transistor PM2 through the inverter I1 are applied at a high potential to the NMOS transistor. The NM1 is turned on and the PMOS transistor PM2 is turned off. When the voltage of the source S1 side of the NMOS transistor NM1 increases as the above operation approaches the high potential, the gate G1 and the PMOS transistor PM2 of the NMOS transistor NM1 are passed through the inverter I1. The voltage applied to the gate G2 of) becomes low potential. Accordingly, the NMOS transistor NM1 is turned off and the PMOS transistor PM2 is turned on. At this time, a current flows to the output side of the inverter I1 by the power supply voltage VCC applied to the source S2 of the PMOS transistor PM2, thereby delaying the time when the NMOS transistor NM1 is turned off. That is, the turn-off time of the NMOS transistor NM1 is delayed compared to the amount at which the voltage of the source S1 side of the NMOS transistor NM1 increases, resulting in an increase in the conversion region of the inverter I1.

Also, the feedback circuit composed of the PMOS transistors PM1, PM2 and inverter I1 shown in FIG. 2 (b) also operates similarly to the feedback circuit of FIG. 2 (a). That is, assuming that the voltage on the source S1 side of the PMOS transistor PM1 decreases to a low potential, the gates G1 and G2 of the PMOS transistors PM1 and PM2 through the inverter I1. The voltage applied to is applied at high potential to turn off the PMOS transistors PM1 and PM2. When the source-side voltage of the PMOS transistor PM1 increases to approach high potential by the above-described operation, the inverter I1 is connected to the gates G1 and G2 of the PMOS transistors NM1 and PM2 through the inverter I1. The voltage applied becomes low potential. As a result, the PMOS transistors PM1 and PM2 are turned on. At this time, a current flows to the output side of the inverter I1 by the power supply voltage VCC applied to the source S2 of the PMOS transistor PM2, thereby delaying the time that the PMOS transistor PM1 is turned on. That is, the time at which the PMOS transistor PM1 is turned on is delayed compared to the amount at which the voltage of the source S1 side of the PMOS transistor PM1 increases, resulting in an inverter as shown in FIG. 3 (b). The conversion area of (I1) becomes wider.

As described in detail above, the feedback circuit according to the present invention increases the conversion area of the inverter by the PMOS transistor connected to the output side of the inverter, whereby the source voltage of the NMOS transistor or PMOS transistor is changed by noise. Even though the output voltage is less affected by noise, stability is increased.

Claims (2)

A feedback circuit in which a source side signal of a MOS transistor is inverted through an inverter and applied to a gate of the MOS transistor, the PMOS transistor having a source voltage applied to a source and having a drain and a gate commonly connected to an output side connection point of the inverter. Feedback circuit comprising a. The feedback circuit according to claim 1, wherein the MOS transistor is an NMOS transistor or a PMOS transistor.