KR200233843Y1 - Additional Annealing Prevention Device - Google Patents

Abstract

The present invention relates to an additional annealing prevention device, and more particularly, to an additional annealing prevention device for preventing an abnormal operation caused by a mistake on a Furnace's PYRO equipment operation panel.

To this end, a plurality of switches, charges and discharges capable of selecting a processor / dummy / monitor wafer of the present annealing prevention apparatus of the present invention, a plurality of counter IC units and BCD code ICs operating under the control of the switches, the plurality of switches It characterized in that it comprises a plurality of relay driver for operating the relay in accordance with the control of the BCD code IC

Description

Additional Annealing Prevention Device

1 is a conventional operation panel circuit diagram

2 is a circuit diagram of the operation panel according to the present invention

3 is a three-circuit diagram of a switch according to the present invention

* Description of the symbols for the main parts of the drawings *

20: operation panel portion 21: processor switch

22: dummy switch 23: monitor switch

24: Charge 25: Discharge

26,27,28: 1st, 2nd and 3rd counter IC unit

29,30,31: first, second and third BCD code IC

32, 33, 34: first, second and third relay drive unit

The present invention relates to an additional annealing prevention device, and more particularly, to an additional annealing prevention device for preventing an abnormal operation due to a mistake on a PYRO equipment operation panel of a furnace.

FIG. 1 is a circuit diagram of a conventional annealing prevention device, which includes a processor switch 10, a dummy switch 11, a monitor switch 12, and a charge selectable wafer. Charge button 13 and a discharge button (14).

Referring to the operation of the conventional annealing prevention system configured as described above are as follows.

After placing the cassette on the loader part of the device, selecting the wafer type, the preparatory operation is performed when the charge pattern is pressed once, and when the button is pressed again, it is transported to the stage of the selected wafer, and when the stage is completely filled Repeat until.

When the stage is completely filled, the transfer machine carries the wafer of the stage to the elevator. When the transfer is completed, the transfer machine moves to the home position, and the elevator moves into the tube. When is completed, Anneal (Anneal) proceeds.

When the annealing is completed, the elevator moves again, and the transfer machine carries the wafer of the elevator back to the stage.

The sequence from the stage to the elevator to complete the process and back to the stage is automatically operated, the function of transporting from the loader to the stage is executed by the operator pressing five buttons.

However, when annealing is completed and one of the five buttons of the loader part is pressed in a sequence in which the elevator descends from the tube, there is a problem in that the wafer is damaged due to data impulse on the CPU.

The present invention is to solve the problems according to the prior art, the purpose according to the present invention is provided with a counter IC and BCD code IC automatically when a certain time elapses when the button is pressed due to a worker mistake and other situations When the reset is completed and the process is completed in the tube, the open button is initialized to provide an additional annealing prevention device that can prevent a sequence stop state due to a data collision in advance.

Features of the additional annealing prevention apparatus according to the present invention for achieving the above object is a plurality of switches, charge and discharge that can select the processor / dummy / monitor wafer, and a plurality of counters operating under the control of the switch An IC unit and a BCD code IC and a plurality of relay driving units for operating a relay under control of the plurality of BCD code ICs are provided.

Hereinafter, with reference to the accompanying drawings a preferred embodiment of the additional annealing prevention apparatus according to the present invention.

2 is a circuit diagram of a further annealing vehicle according to the present invention, the processor switch 21, the dummy switch 22, the monitor switch 23, the charge button 24 and the discharge button to receive the power supply voltage (12V) An operation panel portion (20) composed of (25), first, second and third counter IC portions (26) (27) (28) for receiving an input signal by the control of the charge button (24); First, second and third BCD code ICs 29 which receive a plurality of signals output from the first, second and third counters 26, 27 and 28 and output one output signal. (30) (31) and relay drivers (32) (33) (34) for receiving a signal output from the first, second and third BCD code ICs (29) (30) (31) to drive a relay. It is composed of

The first, second, and third counter IC units 26, 27, and 28 are first, second, and third counter ICs 26a, 27a that receive the power supply voltage 12V at the second and third times. 28a, a 7414 NAND gate connected to 14 each of the first, second, and third counter ICs 26a, 27a, 28a, and a resistor connected to each of the 7414 NAND gates. R8), R9, and the resistors R4 / R6 / R8 and capacitors C1 / C2 / C3 connected to the midpoints of LED4 / LED5 / LED6.

The first, second, and third relay drivers 32, 33, and 34 are transistors Q1, Q2, and Q3, and resistors connected to the bases of the transistors Q1, Q2, and Q3. (R10) and resistor (R11) and resistor (R12), relays (L1) / (L2) / (L3), LED7 / LED8 / LED9, which are connected to the drain terminals of the transistors Q1, Q2, and Q3. It consists of resistors R13 / R14 / R15.

Referring to the operation of the additional annealing prevention apparatus according to the present invention configured as described above are as follows.

After placing the cassette on the loader part of the device and selecting the wafer type, the power supply voltage (12V) input to the processor, dummy, and monitor is input, and when the charge button is pressed once, the first, second, and third counter IC parts The power supply voltage (12V) is input to the (26), (27), and (28) to make the correct square wave through each 7414 NAND gate and then input to the 7490 IC (26a) (27a) (28a).

The output terminals 12, 8, 9, and 11 of the 7490 ICs 26a, 27a, and 28a are 14, 14, 13, of the first, second, and third BCD code ICs 29, 30, 31; It is input to 12 terminals.

Signals input to the first, second and third BCD code ICs 29, 30 and 31 are connected to terminals 11 of the first, second and third BCD code ICs 29, 30 and 31. Low is output at once.

On the other hand, the transistors Q1, Q2 and Q3 of the first, second and third relay drivers 32, 33 and 34 are always turned on before the first, second and third BCD code ICs. When terminals 11 of (29) (30) and (31) fall low, the transistors (Q1) (Q2) (Q3) of the first, second, and third relay drivers (32), (33), (34) It is turned off and the relays L1 / L2 / L3 are also turned off.

Therefore, the contact of the relays L1 / L2 / L3 is closed, so the dummy switch 22 is pressed.

Referring to FIG. 3 of the detailed operation of the dummy switch 22, when the dummy switch 22 is pressed for 1 to 2 seconds, the charge voltage of the transistor Q4 is supplied when it is charged to 470 ㎌. Relay L4 is turned on.

The contact of the relay L4 is opened to become low at terminals 2 and 3 of the first, second and third counter ICs 26a, 27a and 28a, and are reset to the initial state.

In addition, when the dummy switch 22 is pressed, all buttons on the operation panel are initialized to operate in the normal sequence without data collision when the process is completed, and the operation of the remaining switches 21 and 23 is also the same. Proceeds.

As described above, the additional annealing prevention device according to the present invention has an advantage of preventing abnormal operation due to a mistake on the pyro equipment operation panel of the furnace.

Claims (3)

An operation panel portion composed of first to fifth switches which control the cassette to perform a repetitive operation until the cassette selects the wafer from the loader portion and fills the stage; A counter IC unit comprising N counter ICs operating under input of a power supply voltage according to the control of the fourth switch of the operation panel unit, and receiving one signal from N counter ICs of the counter IC unit and outputting one signal And a BCD code IC unit comprising N BCD code ICs and N relay drive units for relay driving by the control of the second switch and the signals output from the N BCD code ICs. Annealing prevention device. The apparatus of claim 1, wherein the first to fifth switches comprise a processor, a dummy, a monitor, a charge and a discharge button in order. The method of claim 1, wherein when the second switch is turned on, the N relay operations are started, the N counter IC units are initialized, and all the switches of the operation panel unit are initialized, and data collision occurs when the process is completed. Additional annealing prevention device, characterized in that the occurrence of abnormal operation is prevented.