KR200223987Y1 - Flag generation circuit for FIFO memory - Google Patents

Abstract

A flag generation circuit according to the present invention includes a first write processor for generating a first write memory enable signal, a first read processor for generating a first read memory enable signal, the first write memory enable signal and the first write processor. An empty flag generating circuit having an empty flag generating unit configured to receive a first read memory enable signal and compare and determine an empty flag when data is currently empty in a memory area of the first-in first-out memory;

A second read processor for generating a second read memory enable signal, a second write processor for generating a second write memory enable signal, the second read memory enable signal and the second write memory enable signal; And a full flag generation circuit having a full flag generation unit for generating a full flag when data is in a full state in the first-in first-out memory.

The present invention is simpler than the flag generation circuit of the conventional first-in-first-out memory, and in particular, when the period difference between the first clock and the second clock is large, the width of the flag is increased by the capacity of the designated memory to reduce the frequency of flag generation. There is an advantage to increase the stability of the operation.

Description

Flag generation circuit for first-in-first-out memory {Flag generation circuit for FIFO memory}

The present invention relates to a full flag and empty flag generation circuit of a first-in-first-out memory. More specifically, the present invention relates to a flag generation circuit that guarantees stability of a first-in-first-out operation of a memory by widening a flag by performing a flag operation using a memory. It is about.

Today, electronic circuits require high speed data movement, and therefore, first-in, first-out memory is frequently used for high speed data movement between devices. The first-in first-out memory, which mainly deals with data that is processed at high speed, needs to indicate the current magnetic state in particular, and a device for generating the status display flag of the first-in first-out memory is a flag generation circuit.

1 is a block diagram of a conventional empty flag generation circuit.

Referring to FIG. 1, a first light detector 11 for receiving a write enable signal, counting in synchronization with a first clock signal, and outputting a first light counting signal in synchronization with a second clock signal, A first read detection unit 12 which receives an enable signal, counts in synchronization with the input of the second clock signal, and outputs a first read count signal and a next read count signal; and the first write count signal and the first read count signal. An empty flag generation determining unit 13 for generating an empty flag when the first read counting signal and the next read counting signal are input and determined and data is currently in an empty state of the first-in first-out memory; An empty flag output unit 14 receiving the output of the tee flag generation determining unit and outputting the empty flag in synchronization with the second clock signal. There is off.

The empty flag generation circuit receives a first clock signal CLK1, a second clock signal CLK2, a write enable signal Wren, and a read enable signal Rden having different periods, and receives a first-in first-out memory. The empty flag EF is output when all the data is read in the predetermined memory area of.

In other words, the empty flag generation determining unit may be the same as all values of the write counter and the read counter, or the next read counter and the write counter have the same value, and the read enable signal Rden is '1'. In case of, an empty flag EF is output in synchronization with the second clock signal CLK2.

2 is a block diagram of a conventional full flag generation circuit.

Referring to FIG. 2, a second read detector 21 which receives the read enable signal, counts in synchronization with the second clock signal, and outputs a second read counting signal in synchronization with the first clock signal. And a second write detector 22 receiving the write enable signal and counting in synchronization with the input of the first clock signal to output a second write counting signal and a next write counting signal; A full flag generation determiner 23 which receives a counting signal, the second write counting signal and a next write counting signal, and determines a full flag when data is currently in the memory area of the first-in first-out memory; And a full flag output unit 24 which receives the output of the full flag generation determining unit and outputs the full flag in synchronization with the first clock signal. Lost

The full flag generator receives the first and second clock signals CLK1 and CLK2, a write enable signal Wren, and a read enable signal Rden, and transmits data to a predetermined memory area of the first-in first-out memory. When all are written, the full flag FF is output.

In other words, the full flag generation determining unit may satisfy the full conditions of the write counter and the read counter, or the values of the next write counter and the light counter satisfy the full condition and the write enable signal. When Wren is '1', the full flag FF is output in synchronization with the first clock signal CLK1.

The empty flag generator circuit and the full flag generator circuit flip the first light detector in the empty flag generator circuit and the second lead detector in the full flag generator circuit so as to synchronize the blocks operating at different clocks. Flop was used. However, when using a small flip-flop, when the period difference between the first clock and the second clock is large, the flag may not be recognized due to a narrow cycle range of the flag indicating that the memory is empty or full. In addition, if a flag is generated once, a flag is generated every clock, thereby degrading the stability of the operation.

An object of the present invention is to provide a flag generation circuit of a first-in, first-out memory that can be improved in order to reduce the frequency of occurrence of a flag and increase the stability of the operation by widening the flag cycle.

1 is a block diagram of a conventional empty flag generation circuit.

2 is a block diagram of a conventional full flag generation circuit.

3 is a block diagram of an empty flag generation circuit according to the present invention.

4 is a block diagram of a full flag generation circuit according to the present invention;

<Explanation of symbols for main parts of the drawings>

11, 22 ... light detector 12, 21 ... lead detector

13 ....... Empty flag occurrence determination unit

14 ......... Empty flag output

23 ......... Full flag generation judgment section 24 ......... Full flag output section

31, 42 ..... light processing section 32, 41 ..... lead processing section

33 ......... Empty flag generator 43 ......... Full flag generator

31a, 42a ... light counter 32a, 41a ... lead counter

31b, 42b ... Write memory selector 32b, 41b ... Lead memory selector

32c, 42c ... logical elements 33a, 43a ... comparative

33b, 43b ... logical circuit

In order to achieve the above object, a flag generating circuit according to the present invention includes a first write processor for generating a first write memory enable signal, a first read processor for generating a first read memory enable signal, and the first write processor. An amplifier having an empty flag generator for generating an empty flag when data is currently empty in a memory area of the first-in first-out memory by receiving and comparing a write memory enable signal and the first read memory enable signal. Tee flag generating circuit,

A second read processor for generating a second read memory enable signal, a second write processor for generating a second write memory enable signal, the second read memory enable signal and the second write memory enable signal; And a full flag generation circuit including a full flag generator for generating a full flag when data is in a full state in the first-in first-out memory.

3 is a block diagram of an empty flag generation circuit according to the present invention.

Referring to FIG. 3, the empty flag generation circuit according to the present invention receives a write enable signal Wren, counts in synchronization with the first clock signal CLK1, outputs a first write memory selection signal, and outputs a second write memory selection signal. A first write processor 31 for converting and outputting the first write memory selection signal into a first write memory enable signal and a read enable signal Rden in synchronization with a clock signal CLK2, and receiving the second write signal A first read memory selection signal is output by counting in synchronization with the input of the clock signal CLK2, and the first read memory selection signal is converted into a first read memory enable signal in synchronization with the second clock signal CLK2. The first read processor 32 and the first write memory enable signal and the first read memory enable signal are received and compared to determine the current memory of the first-in first-out memory. An empty flag generation unit 33 for generating an empty flag when data is empty in the area.

The write processor 31 includes a write counter 31a and a write memory selector 31b. The write counter 31a receives the write enable signal Wren and converts the count result into a signal for selecting a memory to be written in synchronization with the first clock signal CLK1. The write memory selector 31b receives and decodes the memory selection signal in synchronization with the second clock signal CLK2 and generates a write memory enable signal for enabling the corresponding memory.

The read processing section 32 is composed of a read counter section 32a, a read memory selector 32b, and an AND product 32c including an inverter. The read counter 31a receives the read enable signal Rden when the result of the empty flag generator 33 is not in the empty flag generation state, and is synchronized with the second clock signal CLK2. The count result is converted into a signal for selecting a memory to be read and output. The read memory selector 32b receives and decodes the memory select signal in synchronization with the second clock signal CLK2 and generates a read memory enable signal that enables the corresponding memory.

The empty flag generator 33 is composed of a comparator 33a and a logic circuit 33b. The comparator 33a is a logical logic circuit, and the logic circuit 33b is a logical logic circuit. Can be configured.

The comparator 33a logically multiplies the write memory enable signal of the write processor 31 and the read memory enable signal of the read processor 32 by the signals allocated to each memory. After the comparison, the result is output to the logic circuit 33b, and the logic circuit 33b performs an OR operation on the signal sent from the comparator 33a.

As described above, when any one of the write processing unit 31 and the read processing unit 32 is the same, an empty flag EF is output in synchronization with the second clock signal CLK2, and the empty flag is output. Since the generation circuit uses the memory, the flag generation width is widened by the memory capacity since there is no change in the memory enable signal until the capacity of the enabled memory is full.

4 is a block diagram of a full flag generating circuit according to the present invention.

Referring to FIG. 4, the full flag generation circuit according to the present invention receives a read enable signal Rden, counts in synchronization with the second clock signal CLK2, outputs a second read memory selection signal, and outputs a first clock. A second read processor 41 for converting and outputting the second read memory selection signal into a second read memory enable signal and a write enable signal Wren in synchronization with the signal CLK1 to receive the first clock; A second write memory selection signal that is counted in synchronization with the input of the signal CLK1 and outputs a second write memory selection signal, and converts the second write memory selection signal into a second write memory enable signal in synchronization with the first clock signal CLK1; A second write processing unit 42 and the second read memory enable signal and the second write memory enable signal are received and compared to determine the current memory zero of the first-in first-out memory. When the data is a full state it consists of a full flag generating part 43 for generating the full flag.

The read processing section 41 is composed of a read counter section 41a and a read memory selection section 41b. The read counter 41a receives the read enable signal Rden and converts the count result into a signal for selecting a memory to be read in synchronization with the second clock signal CLK2. The read memory selector 41b receives and decodes the memory select signal in synchronization with the first clock signal CLK1 and generates a read memory enable signal that enables the corresponding memory.

The write processing section 42 includes a write counter section 42a, a write memory selector 42b, and an AND product 42c including an inverter. The write counter 41a receives the write enable signal Wren when the result of the full flag generator 43 is not in the full flag generation state, and is synchronized with the first clock signal CLK1 to count the result. Is converted into a signal for selecting the memory to be written and output. The write memory selector 42b receives and decodes the memory select signal in synchronization with the first clock signal CLK1 and generates a write memory enable signal for enabling the corresponding memory.

The empty flag generator 43 is composed of a comparator 43a and a logic circuit 43b. The comparator 43a is a logical logic circuit, and the logic circuit 43b is a logical logic circuit. Can be configured.

The comparator 43a logically multiplies the read memory enable signal of the read processor 41 and the write memory enable signal of the write processor 42 by signals allocated to each memory. After the comparison, the result is output to the logic circuit 43b, and the logic circuit 43b performs an OR operation on the signal sent from the comparator 43a.

As described above, when any one of the read processor 41 and the write processor 42 is the same, the full flag FF is output in synchronization with the first clock signal CLK1, and the full flag generator circuit Since the memory enable signal remains unchanged until the capacity of the enabled memory is full by using the memory, the flag generation width is widened by the memory capacity.

The present invention is simpler than the flag generation circuit of the conventional first-in-first-out memory, and especially when the period difference between the first clock and the second clock is large, the width of the flag is increased by the capacity of the designated memory, thereby increasing the frequency of flag generation. There is an advantage to increase the stability of the operation.

Claims (7)

A first write processor configured to generate a first write memory enable signal; A first read processor configured to generate a first read memory enable signal; An empty flag generator configured to receive and compare the first write memory enable signal and the first read memory enable signal and generate an empty flag when data is currently in an empty state of the first-in first-out memory; An empty flag generation circuit provided; A second read processor configured to generate a second read memory enable signal; A second write processor configured to generate a second write memory enable signal; A full flag generator configured to receive and compare the second read memory enable signal and the second write memory enable signal and generate a full flag when data is currently in the memory area of the first-in first-out memory; A flag generation circuit of a first-in first-out memory, comprising a flag generation circuit. The method of claim 1, The first write processing unit includes a write counter unit for counting and converting the first write signal into a first write memory selection signal in synchronization with the first clock signal; And a write memory selector for converting and outputting the first write memory selection signal to the first write memory enable signal in synchronization with the second clock signal. The method of claim 1, The first read processing unit may be synchronized with the second clock signal and counted to read and convert the first read memory selection signal into a read counter unit; And a read memory selector for converting the first read memory selection signal into the first read memory enable signal in synchronization with the second clock signal. The method of claim 1, The empty flag generator is a comparison unit consisting of several logical AND circuits, A flag generation circuit of a first-in first-out memory, comprising a logic circuit composed of one logical sum circuit. The method of claim 1, The second read processing unit includes a read counter unit for counting and converting a second read memory signal into a second read memory selection signal in synchronization with the second clock signal; And a read memory selector for converting the second read memory selection signal into the second read memory enable signal in synchronization with the first clock signal. The method of claim 1, The second write processing unit includes a write counter unit for counting and converting the second write memory selection signal into a second write memory selection signal in synchronization with the first clock signal; And a write memory selection unit for converting and outputting the second write memory selection signal to the second write memory enable signal in synchronization with the first clock signal. The method of claim 1, The full flag generator comprises a comparison unit consisting of several logical AND circuits, A flag generation circuit of a first-in first-out memory, comprising a logic circuit composed of one logical sum circuit.