KR100226025B1 - Plag generation circuit of nonsynchronous fifo memory - Google Patents

Abstract

The present invention relates to a flag generation circuit of a first in first out memory (FIFO) capable of first-in first-out operation of data at high speed even between blocks operated at clocks of different periods. A first input signal WEN, counted in synchronization with the first clock signal CLK1 having a predetermined period, and outputting a first light counting signal in synchronization with the second clock signal CLK2 having a predetermined period; A light detection unit 110; A first lead sensing unit 120 which receives a predetermined lead enable signal REN, counts in synchronization with the input of the second clock signal CLK2, and outputs a first lead counting signal and a next row counting signal; ; An empty flag to generate an empty flag (EF) when the first light counting signal, the first read counting signal, and the next read counting signal are received and determined and data is empty in a memory area of the first-in first-out memory. A flag generating unit 130; An empty flag output unit 140 which receives the output of the empty flag generation determining unit 130 and outputs the empty flag EF in synchronization with the second clock signal CLK2; A second lead sensing unit configured to receive the lead enable signal REN, count in synchronization with the second clock signal CLK2, and output a second lead counting signal in synchronization with the first clock signal CLK1. 210; A second light detection unit 220 receiving the write enable signal WEN and counting the same to the first clock signal CLK1 and outputting a second light counting signal and a next light counting signal; Determining the second lead counting signal, the second light counting signal, and the next light counting signal to determine the full flag generation when the data is currently in the memory area of the first-in first-out memory in a full state. Section 230; And a full flag output unit 240 for receiving the output of the full flag generation determining unit 230 and outputting the full flag FF in synchronization with the first clock signal CLK1.

Description

Flag generation circuit of asynchronous first-in first-out memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first in first out memory (FIFO), and more specifically, a flag generation circuit of a first in first out memory capable of first-in first-out operation of data even between blocks operated at clocks of different periods. It is about.

At present, with the development of the semiconductor chip manufacturing process, the integration is also increasing, and many single chips incorporating various functions into one semiconductor chip have appeared. In addition, a first-in, first-out memory is often used for an interface between blocks in order to speed up data movement between blocks configured in the single chip.

On the other hand, a plurality of clocks are often present in such a single chip. This is because the blocks configured therein have different operating characteristics, and thus the clock used for this may have different periods.

At this time, the first-in, first-out memory should inform each block of its own state. In this case, the read / write counters operating in different clocks are compared, and the result is synchronized to the clock in which each block operates. Must be provided. Due to the operation characteristics as described above, there has been a problem that a delay occurs and a desired operation speed cannot be obtained. In addition, there has been a problem that adverse effects due to wire delay occurs when each block is separated by a predetermined interval or more.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide a flag generation circuit of a first-in first-out memory that enables high-speed interfacing between blocks having different operating frequencies.

1 is a block diagram showing a schematic configuration of an empty pull flag generating unit according to an embodiment of the present invention,

2 is a detailed circuit diagram of the empty flag generating unit shown in FIG.

3 is a detailed circuit diagram of the full-flag generation unit shown in FIG.

4 is a timing diagram according to an operation of an important part of the empty flag generating unit shown in FIG.

5 is a timing diagram according to an operation of an important part of the full flag generating unit shown in FIG.

* Description of the symbols for the main parts of the drawings *

100: empty flag generating unit 110: light detection unit

112, 222: light counters 114, 142, 214, 242: flip flops

120: lead detection unit 122, 212: lead counter

124, 224: Multiplexer 126: Nexttrial Counter

130: empty flag generation determination unit 132, 134: comparison unit

136, 138, 236, 238: logic circuit 140: empty flag output section

200: full flag generator 210: lead detection unit

220: light detection unit 226: next light counter

230: full flag generation determination section 232, 234: determination unit

240: full flag output unit

(Configuration)

According to one aspect of the present invention for achieving the above object, a flag generation circuit of a first-in first-out memory: receives a predetermined write enable signal, counts in synchronization with a first clock signal having a predetermined period, A first light detecting unit outputting a first light counting signal in synchronization with a second clock signal having a period of? A first lead sensing unit configured to receive a predetermined lead enable signal and to count in synchronization with the input of the second clock signal to output a first read counting signal and a next read counting signal; An empty flag generation decision that generates an empty flag when the first light counting signal, the first lead counting signal, and the next read counting signal are received and determined and data is empty in a memory area of the first-in first-out memory. Wealth; An empty flag output unit receiving the output of the empty flag generation determining unit and outputting the empty flag in synchronization with the second clock signal; A second lead sensing unit configured to receive the lead enable signal, count in synchronization with the second clock signal, and output a second lead counting signal in synchronization with the first clock signal; A second light sensing unit configured to receive the write enable signal and count in synchronization with the input of the first clock signal to output a second light counting signal and a next light counting signal; A full flag generation determining unit configured to receive the second read counting signal, the second write counting signal and the next light counting signal, and generate a full flag when data is currently in the memory area of the first-in first-out memory; And a full flag output unit configured to receive an output of the full flag generation determining unit and output the full flag in synchronization with the first clock signal.

The light counter may include: a light counter configured to receive the light enable signal and output a counting result in synchronization with the first clock signal; And a flip-flop configured to output the first light counting signal in synchronization with the counting result in response to the second clock signal.

In this embodiment, the light counter is composed of a gray code counter.

In an embodiment, the first read detection unit may include: a read counter configured to output the first read counting signal in synchronization with the second clock signal; A necked counter which receives the first read counting signal and increases a predetermined number to output the nexted counting signal; And a multiplexer configured to receive the first read counting signal and the next street counting signal and output a corresponding input to the read counter according to the input of the lead enable signal.

In this embodiment, the lead counter is comprised of a gray code counter.

The empty flag generation determining unit may include: a first comparing unit configured to receive the first light counting signal and the next street counting signal, compare the received signal, and output a predetermined signal corresponding to the result; A second comparing unit which receives the first light counting signal and the first read counting signal, compares the first light counting signal, and outputs a predetermined signal corresponding to the result; A first logic circuit unit for outputting the output of the first comparator and the read enable signal to perform a predetermined logic operation to output the first comparator; And a second logic circuit part configured to receive the output of the first logic circuit part and the output of the second comparator and perform a logical operation on the output.

In this embodiment, the first logic circuit portion is composed of an AND gate.

In this embodiment, the second logic circuit portion is composed of an oragate.

In this embodiment, the empty flag output unit includes a flip-flop that outputs an empty flag in synchronization with the second clock signal.

In this embodiment, the second lead detection unit receives the lead enable signal, and a read counter for outputting a counting result in synchronization with the second clock signal; And a flip-flop configured to output the second read counting signal in synchronization with the counting result in response to the first clock signal.

In this embodiment, the lead counter is comprised of a gray code counter.

In an embodiment, the second light detection unit may include: a light counter configured to output the second light counting signal in synchronization with the first clock signal; A next light counting signal receiving the second light counting signal and increasing a predetermined number to output the next light counting signal; And a multiplexer configured to receive the second light counting signal and the next light counting signal and output a corresponding input to the light counter according to the input of the light enable signal.

In this embodiment, the light counter is composed of a gray code counter.

In this embodiment, the full-flag generation judging unit receives the second lead counting signal and the next strike counting signal to determine a counting state and outputs a predetermined signal corresponding to the result; A second determination unit which receives the second read counting signal and the second light counting signal, determines a counting state, and outputs a predetermined signal corresponding to the result; A first logic circuit unit configured to input an output of the first determination unit and the write enable signal to perform a predetermined logic operation to output the first enabler; And a second logic circuit unit configured to receive the output of the first logic circuit unit and the output of the second determination unit to perform logical operation on the output.

In this embodiment, the first logic circuit portion is composed of an AND gate.

In this embodiment, the second logic circuit portion is composed of an oragate.

In this embodiment, the full flag output unit is composed of a flip flop which outputs a full flag in synchronization with the first clock signal.

(Action)

According to the present invention as described above, the operating frequency of the corresponding block is increased by directly outputting the full empty flag indicating the state of the first-in first-out memory from the flip-flop.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a schematic configuration of an empty full flag generating unit according to an embodiment of the present invention, Figure 2 is a detailed circuit diagram of the empty flag generating unit shown in Figure 1, Figure 3 is shown in Figure 1 Is a detailed circuit diagram of the full-flag generator.

As shown in FIG. 1, an empty full flag generating unit according to an exemplary embodiment of the present invention includes an empty flag generating unit 100 and a full flag generating unit 200.

The empty flag generation unit 100 receives the first clock signal CLK1, the second clock signal CLK2, the write enable signal WEN, and the read enable signal REN having different periods. When all data is read into a predetermined memory area of the first-in first-out memory, the empty flag EF is output. The full flag generator 200 receives the first and second clock signals CLK1 and CLK2, the write enable signal WEN, and the read enable signal REN, and stores a predetermined memory of the first-in first-out memory. When all data is written to the area, the full flag EF is output.

Specifically, the empty flag generation unit 100 and the full flag generation unit 200 will be described with reference to FIGS. 2 and 3.

First, as shown in FIG. 2, the empty flag generating unit 100 has a large light detecting unit 110, a lead detecting unit 120, an empty flag generating determining unit 130, and an empty group. It is configured to include a flag output unit 140.

The light detecting unit 110 includes a light counter 112 and a flip-flop 114. The light counter 112 includes a gray code counter, receives the write enable signal WEN, and outputs a counting result in synchronization with the first clock signal CLK1. The flip-flop 114 receives and outputs the output in synchronization with the second clock signal CLK2. Since the light counter 112 is configured as a gray code counter to change by one bit, an error may be prevented from being clocked in the flip-flop 114.

The lead detecting unit 120 includes a lead counter 122, a multiplexer 124, and a next read counter 126. The read counter 122 includes a gray code counter and outputs a counting result in synchronization with an input of the multiplexer 124 and the second clock signal CKL2. The output of the lead counter 122 is provided to the multiplexer 124 and the necked counter 126. The multiplexer 124 receives the output of the necked counter 126 and the output of the read counter 122, and outputs a corresponding signal according to the input of the lead enable signal REN to read the read counter. 122).

The empty flag generation determining unit 130 is composed of first and second comparison units 132 and 134 and first and second logic circuits 136 and 138. The first and second logic circuits 136 and 138 may be composed of an AND gate and an OR gate, respectively.

The first comparator 132 compares the output of the flip-flop 114 with the output of the next-counter counter 126 and outputs the result to the first logic circuit 136. In operation 136, the signal is ANDed according to the input of the lead enable signal REN and output to the second logic circuit 138. The second comparator 134 compares the output of the flip-flop 114 with the output of the read counter 122 and outputs the result to the second logic circuit 138. The second logic circuit 138 performs an OR operation on this and outputs it.

The empty flag output unit 140 includes a flip-flop 142. The empty flag output unit 140 receives the output of the second logic circuit 138 to synchronize the empty flag EF in synchronization with the second clock signal CLK2. Will print.

As described above, the empty flag generation determination unit 130 is the case that all the values of the light counter 112 and the lead counter 122 is the same, or the necked counter 126 and the light counter 112 Is equal to and the lead enable signal REN is a predetermined high level '1', an empty flag EF is output in synchronization with the second clock signal CLK2.

Next, as shown in FIG. 3, the full flag generating unit 200 includes a lead detecting unit 210, a light detecting unit 220, a full flag generating determining unit 230, and a full flag output unit. And 240.

The lead detecting unit 210 includes a lead counter 212 and a flip-flop 214. The read counter 212 includes a gray code counter. The read counter 212 receives the read enable signal REN and synchronizes with the second clock signal CLK2 to output a counting result. The flip-flop 214 receives the output in synchronization with the first clock signal CLK1 and outputs the output. Since the read counter 212 is configured as a gray code counter to change by one bit, an error may be prevented from occurring when clocked in the flip-flop 214.

The light detector 220 includes a light counter 222, a multiplexer 224, and a next write counter 226. The light counter 222 includes a gray code counter and outputs a counting result in synchronization with the input of the multiplexer 224 and the first clock signal CKL1. The output of the light counter 222 is provided to the multiplexer 224 and the nextlite counter 226. The multiplexer 224 receives the output of the next light counter 226 and the output of the light counter 222, and outputs a corresponding signal according to the input of the write enable signal WEN to output the light counter. 222).

The full flag generation determination unit 230 includes first and second determination units 232 and 234 and first and second logic circuits 236 and 238. The first and second logic circuits 236 and 238 may be composed of an AND gate and an OR gate, respectively.

The first determiner 232 compares the output of the flip-flop 214 with the output of the next light counter 226 and outputs the result to the first logic circuit 236. In operation 236, the signal is ANDed according to the input of the write enable signal WEN, and is output to the second logic circuit 238. The second comparator 234 compares the output of the flip-flop 214 with the output of the lead counter 222 and outputs the result to the second logic circuit 238. The second logic circuit 238 outputs the result of OR calculation.

The full flag output unit 240 includes a flip-flop 242. The full flag output unit 240 receives the output of the second logic circuit 238 and is synchronized with the first clock signal CLK1 to provide a full flag FF. Will print

As described above, the full flag generation determination unit 230 satisfies the gray code full conditions of the light counter 212 and the lead counter 222, or the next light counter 226 and the When the value of the light counter 222 satisfies the gray code full condition and the write enable signal WEN is a predetermined high level '1', the full flag FF is synchronized with the first clock signal CLK1. Is output.

Next, operations of the empty flag generating unit 100 and the full flag generating unit 200 will be described with reference to the timing diagrams of FIGS. 4 and 5.

FIG. 4 is a timing diagram according to the operation of the important part of the empty flag generating unit shown in FIG. 2, and FIG. 5 is a timing diagram according to the operation of the important part of the full flag generating unit shown in FIG.

4 and 5, when the write enable signal WEN and the read enable signal REN reach a high level '1', an empty flag EF and a full flag FF become the first flag. And waveforms generated in synchronization with the second clock signals CLK1 and CLK2, respectively. In this example, it is assumed that the lead counters 122 and 212 and the light counters 112 and 222 are increased to # 4. That is, the case where the depth of the first-in first-out memory is 4 is taken as an example.

3 and 4, at the rising edge of the first clock signal CLK1 while the write enable signal WEN is '1' in the full flag generator 200. Since the lead counter 212 is # 0 and the light counter 222 is # 4, the full flag FF is output as '1'. When the read counter 212 is increased to # 1 when data is read from the memory area of the first-in first-out memory in the state that the full flag FF is '1', the full flag FF is the first clock signal. It is changed to '0' in synchronization with (CLK1).

Next, referring to FIGS. 2 and 5, when the light counter 112 is # 3 and the lead counter 122 is # 2 in the empty flag generator 100, that is, data is stored in the first-in, first-out memory. When one is left, when the lead enable signal REN becomes '1', one piece of data is read and the empty flag EF is synchronized with the second clock signal CLK2. Becomes In this state, when the data is written to the first-in, first-out memory and the light counter 112 becomes # 4, the empty counter EF is not present at the rising edge of the second clock signal CLK2. ) Becomes '0'.

According to the present invention as described above, the operating frequency of the corresponding block is increased by directly outputting the full empty flag indicating the state of the first-in first-out memory from the flip-flop. When the integration is performed, even if two adjacent blocks of the first-in, first-out memory are separated from each other on the layout, the circuit operates stably without being affected by the wire delay.

Claims (17)

In the flag generation circuit of the first-in first-out memory: Receives a predetermined write enable signal WEN, counts in synchronization with the first clock signal CLK1 having a predetermined period, and first light counting in synchronization with the second clock signal CLK2 having a predetermined period. A first light detector 110 for outputting a signal; A first lead sensing unit 120 which receives a predetermined lead enable signal REN, counts in synchronization with the input of the second clock signal CLK2, and outputs a first lead counting signal and a next row counting signal; ; An empty flag to generate an empty flag (EF) when the first light counting signal, the first read counting signal, and the next read counting signal are received and determined and data is empty in a memory area of the first-in first-out memory. A flag generating unit 130; An empty flag output unit 140 which receives the output of the empty flag generation determining unit 130 and outputs the empty flag EF in synchronization with the second clock signal CLK2; A second lead sensing unit configured to receive the lead enable signal REN, count in synchronization with the second clock signal CLK2, and output a second lead counting signal in synchronization with the first clock signal CLK1. 210; A second light detection unit 220 receiving the write enable signal WEN and counting the same to the first clock signal CLK1 and outputting a second light counting signal and a next light counting signal; Determining the second lead counting signal, the second light counting signal, and the next light counting signal to determine the full flag generation when the data is currently in the memory area of the first-in first-out memory in a full state. Section 230; And a full flag output unit 240 for receiving the output of the full flag generation determining unit 230 and outputting the full flag FF in synchronization with the first clock signal CLK1. Memory flag generation circuit. The method of claim 1, The first light detection unit 110 A light counter 112 for receiving the write enable signal WEN and outputting a counting result in synchronization with the first clock signal CLK1; And a flip-flop (114) outputting the first write counting signal in synchronization with the counting result in synchronization with the second clock signal (CLK2). The method of claim 2, The light counter 112 is a flag generation circuit of the first-in first-out memory, characterized in that consisting of a gray code counter. The method of claim 1, The first lead detecting unit 120 is A read counter 122 outputting the first read counting signal in synchronization with the second clock signal CLK2; A necked counter 126 that receives the first read counting signal and increases a predetermined number to output the nexted counting signal; And a multiplexer 124 that receives the first read counting signal and the next street counting signal and outputs a corresponding input to the read counter 122 according to the input of the lead enable signal REN. The flag generation circuit of the first-in first-out memory. The method of claim 4, wherein The lead counter 122 is a flag generation circuit of the first-in first-out memory, characterized in that consisting of a gray code counter. The method of claim 1, The empty flag generation unit 130 is A first comparator 132 which receives the first light counting signal and the next street counting signal, compares the first light counting signal, and outputs a predetermined signal corresponding to the result; A second comparator 134 which receives the first light counting signal and the first read counting signal, compares the first light counting signal, and outputs a predetermined signal corresponding to the result; A first logic circuit part 136 for inputting the output of the first comparator 132 and the lead enable signal REN to perform a predetermined logical operation to output the first comparator; And a second logic circuit unit 138 which receives the output of the first logic circuit unit 136 and the output of the second comparison unit 134 and outputs a logical operation. . The method of claim 6, And the first logic circuit section (136) is configured as an AND gate. The method of claim 6, The flag generation circuit of the first-in first-out memory, characterized in that the second logic circuit section (138) is composed of an oragate. The method of claim 1, The empty flag output unit 140 comprises a flip-flop (142) for outputting an empty flag (EF) in synchronization with the second clock signal (CLK2). The method of claim 1, The second lead detecting unit 210 is A read counter 212 which receives the read enable signal REN and outputs a counting result in synchronization with the second clock signal CLK2; And a flip-flop (214) for outputting said second read counting signal in synchronization with said counting result in synchronism with said first clock signal (CLK1). The method of claim 10, The lead counter (212) is a flag generation circuit of the first-in first-out memory, characterized in that consisting of a gray code counter. The method of claim 1, The second light detecting unit 220 is A light counter 222 outputting the second light counting signal in synchronization with the first clock signal CLK1; A next light counting unit 226 which receives the second light counting signal and increases a predetermined number to output the next light counting signal; And a multiplexer 224 which receives the second light counting signal and the next light counting signal and outputs a corresponding input to the light counter 222 according to the input of the light enable signal WEN. The flag generation circuit of the first-in first-out memory. The method of claim 12, The light counter 222 is a flag generation circuit of the first-in first-out memory, characterized in that the gray code counter. The method of claim 1, The full flag generation portion 230 is A first determination unit 232 receiving the second read counting signal and the next light counting signal to determine a counting state and outputting a predetermined signal corresponding to the result; A second determination unit 234 which receives the second read counting signal and the second light counting signal, determines a counting state, and outputs a predetermined signal corresponding to the result; A first logic circuit unit 236 for outputting the output of the first determination unit 232 and the write enable signal WEN to perform a predetermined logic operation and output the predetermined logic operation; And a second logic circuit unit 238 which receives the output of the first logic circuit unit 236 and the output of the second determination unit 234 and performs a logical operation to output the flag logic circuit of the first-in first-out memory. . The method of claim 14, And the first logic circuit part (236) is composed of an AND gate. The method of claim 14, The flag generation circuit of the first-in first-out memory, characterized in that the second logic circuit section (238) is composed of an oragate. The method of claim 1, The full flag output unit (240) is a flag generation circuit of the first-in first-out memory, characterized in that the flip-flop (242) for outputting a full flag (FF) in synchronization with the first clock signal (CLK1).