KR200221586Y1 - Electronic equipment checking device - Google Patents

Abstract

The present invention relates to an inspection device for checking a board or an IC of an electronic device, and solves a problem in that a test performance is not good because a conventional automatic inspection device (ATE) does not cope with high function and high integration of an IC. To this end, in the present invention, the inspection apparatus is configured by using a microcomputer for executing the inspection program by the JTAG, a JTAG controller controlled by the microcomputer, and a JTAG buffer constituting the JTAG bus according to the signal of the JTAG controller. . That is, the present invention is configured to check the IC for general purpose using the JTAG function. By using this inspection device, not only the functions of each IC but also the internal hardware configuration can be inspected, so that the reliability of the inspection can be improved compared to the conventional ATE. In addition, since there is no cost and development period of the adapter according to the conventional manufacturing of the adapter required for using the ATE, it is possible to quickly test the newly developed IC. This electronic equipment inspection device can be useful for the inspection of products developed in the semiconductor production site or ASIC design laboratory.

Description

Electronic equipment checking device

The present invention relates to an electronic device inspection device of a printed board level, and more particularly, to an inspection device using a Joint Test Action Group (JTAG) function.

Conventionally, the equipment for checking electronic equipment has become the mainstream of the test equipment of the ATE (Automatic Test Equipment) type. Automatic inspection equipment (ATE) is used in the manufacturing and inspection line of LSI or digital circuit board (board), etc., a model of this automatic inspection equipment is shown in FIG. The automatic inspection equipment checks the board using the bus of the personal computer (control bus, data bus, address bus, etc.). And when checking the board with automatic test equipment, you need a kind of adapter called a fixture. Since automatic test equipment is a general-purpose standard, it is impossible to support all ICs.

If the configuration of the IC to be inspected is changed, it is inconvenient to rebuild the adapter. In addition to the high cost of automated inspection equipment, testing multiple boards requires the creation of multiple fixtures. However, the development of this fixture takes considerable time, so it takes a long time to test the board and finally develop some equipment.

In the method of checking a board or an IC using an automatic inspection device, a method of giving an input signal and examining an output signal is used. This check is called a functional test. It is simply a check of whether the board or IC is operating normally or abnormally. In situations where ICs are becoming highly integrated and highly functional, such a simple and normal inspection only reduces the reliability of the inspection. And the test point (Test Point) is placed on the board, but because of the high integration, the circuit line width of the board is fine, and the test point has to be placed in several places, so the inspection by the test point is limited. In addition, in the past, DIP (Dual Inline Package) type ICs were the mainstream, but now they are manufactured in QFP (Quad Flat Package) or BGA (Ball Grid Array) type due to the high integration and high functionality of the IC. Access by test pin is not possible. That is, the conventional inspection method using the automatic inspection equipment has a problem that it is impossible to test the IC individually and the test capability is low.

Therefore, an object of the present invention is to provide a new inspection equipment that can accurately check the IC or board of the trend of high integration and high functionality.

1 is a schematic diagram of a conventional electronic device checking apparatus.

2 is a block diagram of an inspection apparatus according to an embodiment of the present invention.

3 is an internal configuration diagram of an IC having a JTAG function.

* Description of the symbols for the main parts of the drawings *

U1: Microprocessor U2: RAM

U3: ROM U4: JTAG Controller

U5: JTAG Buffer 10: Personal Computer

20: check board 21: JTAG bus

In order to achieve the above object, the electronic device inspection apparatus according to the present invention includes a microcomputer executing a inspection program by JTAG, a JTAG controller controlled by the microcomputer, and a JTAG bus or a microcontroller according to the signal of the JTAG controller. It is characterized by having a JTAG buffer constituting a processor compatible bus.

Hereinafter, the present invention will be described in detail with reference to the embodiment of FIG. 2. In the embodiment of Fig. 2, most of the ICs currently developed have a built-in JTAG function. Thus, the inspection apparatus is configured as a board type using a main computer and a JTAG IC. Also, the JTAG buffer is used to check ICs without JTAG function.

JTAG was standardized by the Institute of Electrical and Electronic Engineers (IEEE) 1149.1 in 1990 and imposes a test function on ICs to enable testing of increasingly sophisticated and highly integrated ICs. Most recently developed ICs have this JTAG function. Fig. 3 shows a schematic hardware configuration of the IC having this JTAG function.

Referring to Figure 3, the IC has a JTAG bus consisting of three input pins TDI (Test Data Input), TMS (Test Mode Select), TCK (Test Clock) and one output pin TDO (Test Data Output), and the core The input and output of the logic logic core are surrounded by a boundary cell. In addition, there are various registers (User Data Register, Bypass Register, Instruction Register) that hold the information necessary for inspection, and TAP (Test Access Port) controller for controlling abnormal registers.

The boundary cell is positioned between the external input / output pin of the IC and the internal core logic to surround the IC. The basic structure of the boundary cell can be viewed as a kind of shift register composed of a plurality of flip-flops, and can electrically disconnect or connect between the IC's internal logic and external I / O pins according to a control signal. Since the input / output of the boundary cell can be controlled according to the signal from the TAP controller, the signal can be applied to the internal logic of the IC by controlling the boundary cell without passing through the external input / output pins of the IC. Thus, using these boundary cells enables testing of ICs and boards, regardless of whether pin spacing is minimized. By properly controlling the boundary cell, the section to be tested can be freely adjusted, and various tests can be performed, enabling precise testing. In this embodiment, the inspection apparatus is configured to check the IC or the board by using the JTAG function.

Referring to FIG. 2, there is a personal computer (PC) 10 that outputs a command for board inspection and a board 20 connected through an RS232C interface. The board 20 has a microprocessor U1, and a ROM (U3), a RAM (U2) and a JTAG controller U4 are connected to the bus of the microprocessor U1. JTAG buffer U5 is connected to JTAG controller U4 via JTAG bus 21.

The PC 10 is required to execute a check program, and the electronic device checking device according to the present embodiment is a check device that can be used by being connected to a communication port of a PC to enable a check operation on a general-purpose PC. However, it is also possible to configure the inspection equipment by integrating the PC 10 and the board 20 without following this embodiment. However, in this embodiment, since the entire equipment becomes larger, heavier, and less mobile, in this embodiment, it is configured as a board type so that it can be easily connected to a general purpose PC to check IC or board.

Next, the microprocessor U1 on the board 20 is configured to communicate with the PC 10 to execute the inspection program. The microprocessor U1 is one with the surrounding RAM U2 and ROM U3. Form a small system. That is, the RAM U2 and the ROM U3 are connected to a data bus, an address bus, a control bus, etc. of the microprocessor U1. The ROM U3 stores instructions necessary for the microprocessor U1 to control the JTAG controller U4, and the RAM U2 is used as a data memory of the microprocessor U1.

In this embodiment, the microprocessor (U1), RAM (U2) and ROM (U3) are separately configured as described above, but a microcomputer in which the microprocessor, the RAM, the ROM, and other peripheral devices are built in one chip is also used. It is possible. In this case, however, the memory capacity and processing speed should be taken into consideration.

When the PC 10 outputs a command according to the execution of the inspection program, the command is inputted to the microprocessor U1 through the communication port of the board 20 through the RS232 cable. This microprocessor (U1) outputs the input command to the JTAG controller (U4) in 8-bit, 16-bit, or 32-bit via the data bus.

The JTAG controller U4 is a JTAG IC, which is provided in this embodiment in order to convert 8-bit or 16-bit instructions of the microprocessor U1 into a JTAG bus instruction system. In the present embodiment, the JTAG buffer U5 is used in addition to the JTAG controller U4. The JTAG IC is a generic term for various ICs related to JTAG, and is different from an IC having a JTAG function.

Previously, the JTAG controller U4 converts an 8-bit or 16-bit signal of the microprocessor U1 into a JTAG bus signal to control the next JTAG buffer U5. The JTAG controller U4 outputs a communication protocol required for inspection of a board or IC via the JTAG bus 21 in time division.

Next, the JTAG buffer U5 operates similarly to the functions of a general three-state bus transceiver or bus driver. That is, it has multiple bidirectional tri-state buffers, enabling 8-bit input and 8-bit output in both directions. In addition, when the JTAG buffer U5 is controlled using the JTAG controller U4, each pin of the JATG buffer U5 can be individually controlled. That is, bit-by-bit control is possible.

In this embodiment, the equipment to be checked is connected to the board 20 through a slot or a 4-pin connector, and the slot or 4-pin connector is configured to be connected to the pin of the JTAG buffer U5. Therefore, the inspection object is connected to the buses of the JTAG controller U4 and the microprocessor U1 through the JTAG buffer U5, so that any inspection object can be inspected regardless of which I / O bus.

Computers, peripheral devices, or devices designed to be connected to a computer have a variety of port types and I / O bus arrangements. Therefore, it is difficult to manufacture the inspection equipment supporting all input and output buses. However, as described above, since the JTAG buffer U5 can individually control each pin, it is possible to switch freely, to an address bus, or to a data bus, and as a result, it can cope with any input / output bus. In other words, by using the JTAG buffer, it is possible to construct a general-purpose inspection equipment. This feature of the JTAG buffer (U5) allows the creation of a PC bus used in conventional ATE, and the creation of a JTAG bus to check the IC or PCB board.

The operation of this embodiment will be described below based on the above configuration.

To test a board or IC using this tester, the board or IC to be checked must be connected to the JTAG buffer (U5). When connecting the inspection target and JTAG buffer (U5), use a slot or a 4-pin connector.

Connect the inspection target to the JTAG buffer (U5) and then run the inspection program on the PC (10). When the command is output from the PC 10 according to the inspection program, the output command is transmitted to the board 20 through the RS232C communication port. The microprocessor U1 is then input to the microprocessor U1 on the board 20, and the microprocessor U1 executes an inspection program using the RAM U2 and the ROM U3 through communication with the PC 10. That is, the microprocessor U1 interprets the command output from the PC 10 in the command system used by the JTAG controller U4, and outputs the interpreted command to the JTAG controller U4. The JTAG controller U4 then starts the check by controlling the JTAG buffer U5 in accordance with the command.

When checking ICs without JTAG function, use JTAG buffer (U5) to give JTAG function to IC. Since the JTAG function checks through communication between the inspection equipment and the inspection target, the inspection target can only be checked if there is a JTAG function. Therefore, the IC is provided with a JTAG function by surrounding the input / output pins of the IC with a boundary cell as shown in FIG. As described above, the present embodiment using the JTAG buffer U5 can create a general-purpose bus that can check all ICs, such as ICs with built-in JTAG functions or ICs without them.

Next, when the JTAG buffer U5 forms a JTAG bus between the JTAG controller U4 and the check IC, the JTAG controller U4 communicates with the check IC via this JTAG bus to check the IC.

As described above, the electronic device checking apparatus according to the present invention generates a general-purpose input / output port using the JTAG function, so that the adapter does not need to be manufactured every time the configuration of the target to be checked is changed as in the related art. Therefore, the cost required for manufacturing the adapter can be reduced, and the production period can be shortened.

In addition, not only a functional test for input and test output performed in the conventional ATE, but also a memory built into the IC can be checked, and the CPU can be checked. That is, not only the function of the IC but also the internal hardware configuration can be checked. And you can get detailed information about the part judged to be abnormal during the inspection.

This electronic equipment inspection device can be used for testing digital devices or final products at semiconductor production sites, and can be useful for testing products developed in ASIC design labs.

Claims (1)

A microcomputer executing the inspection program by JTAG, A JTAG controller controlled by the microcomputer, And a JTAG buffer constituting a JTAG bus or a microprocessor compatible bus according to the signal of the JTAG controller.