KR200201196Y1 - Video ram owing in common input path of mask and color resistor - Google Patents

Abstract

The video RAM sharing the input path of the mask and the color register of the present invention can share the path from the data line to the mask register and the color register, thereby reducing the area of the memory device and the power consumption.

Description

Video RAM Shares Input Paths of Mask and Color Registers

1 is a circuit diagram showing a portion of a video RAM including a conventional mask and color register.

2 is a circuit diagram showing a portion of a video RAM sharing an input path of a mask and a color register according to an embodiment of the present invention.

3 is an input / output waveform diagram according to the circuit diagram shown in FIG.

* Explanation of symbols for main parts of the drawings

10: data input buffer 20: logic combination unit

30: data line 40: latch portion

50, 70: NAND gate 60, 80 register

The present invention relates to a semiconductor video ram, and more particularly, a mask that reduces the area and power consumption of a memory device by sharing a path from a data line to a mask register and a color register. And video RAM sharing the input path of the color register.

FIG. 1 is a circuit diagram showing a portion of a video RAM including a conventional mask and a color register. An input buffer 1 buffers data from the outside and a bus line GWD carrying data from the input buffer 1. LINE, 2, a latch circuit 3 for latching data from the bus line 2 for a predetermined period, and a NAND gate 7 for logical combination of a signal from the latch circuit 3 and a control signal from the outside. ), A mask register 4 for storing a signal from the NAND gate 7, a latch circuit 5 for latching data from the bus line 2 for a predetermined period, and from the latch circuit 5 And a color register 6 for storing a signal from the NAND gate 8 in a logical combination of a signal and a control signal from the outside.

Referring to FIG. 1, during the load mask register (hereinafter referred to as LMR) cycle, the data input buffer 1 buffers data from the outside and supplies the buffer to the bus line 2. The data on the bus line 2 is latched in the latch circuit 3 for a predetermined time in accordance with a control signal lmr, / lmr from the outside, and then the mask register 4 in accordance with a controller signal A from the outside. Are stored in. The load color register (hereinafter referred to as LCR) cycle also performs the same operation as the load mask cycle.

However, the masks and kali registers of the video RAM have the same structure and have the same operation, and have the respective paths despite the cycle being not performed at the same time, thereby increasing the layout area. There is this.

Therefore, the present invention provides the advantage of saving the layout area by integrating separate paths into one.

In order to achieve the above object, the mask and the color register of the video RAM of the present invention are configured to use the input path of each register in common by using the fact that the LMR cycle and the LCR cycle do not occur at the same time.

Hereinafter, with reference to the accompanying drawings of the present invention will be described.

2 is a circuit diagram showing a portion of a video RAM including a mask and a color register according to the present invention. The data input buffer 10 buffers data from the outside, and cycle selection signals lmr and lcr from the outside. A logic combination unit 20 to combine, a bus line (GWD LINE) 30 carrying data from the data input buffer 10, and the bus line 30 in accordance with a signal from the logic combination unit 20; A latch unit 40 for latching data from the latch unit for a predetermined period, a NAND gate 50 for logically combining a signal from the latch unit 40 and a control signal A from the outside, and the NAND gate 50. A mask register 60 for storing signals from the NAND gate, a NAND gate 70 for logically combining the signal from the latch unit 40 and the control signal B from the outside, and the NAND gate 70 from the NAND gate 70. It is provided with a color register 80 for storing a signal.

The logic combination unit 20 inverts the output of the NOR gate 27 that negates the cycle selection signals lmr 21 and lcr 22 and the output N1 of the NOR gate 23 to the latch. An inverter 24 for outputting a signal N2 for controlling the unit 40 is included.

The latch unit 40 includes transfer transistors Q1 and Q2 connected between the bus line 30, the node N1, the node N2, and the node N3, and the transfer transistors Q1 and Q2. And an inverter IN1 connected between the node N3, transfer transistors Q3 and Q4 having gates connected to the node N1 and the node N2, and a signal on the node N3 by inverting the signal. Inverter IN2 is supplied to the transfer transistors Q3 and Q4.

The operation of the mask and the color register of the video RAM will be described with reference to FIG. 3, which shows an operation timing diagram of the circuit related to FIG. 2.

Referring to the operation of the LMR cycle, data from the outside via the buffer 10 is applied to the data bus 30. At this time, assuming that the input data is at a high level, the logic combining unit 27 which inputs the cycle selection signals lmr and lcr from the outside supplies a driving signal to the transfer transistors Q1 and Q2 to supply the node N3. Supply a low level signal. In addition, as the signal from the logic combination unit 20 is inverted, the signal on the node N3 forms a loop through the inverter 42 and the transfer transistors Q3 and Q4 and the inverter 41. To latch the signal. As the control signal A from the outside becomes high, the NAND gate 50 supplies a high level signal to the mask register 60.

Since the operation of the LCR cycle is also the same as the operation of the LMR, a detailed description thereof will be omitted.

The above-described video light and color registers share the paths loaded to each register, and the load color register cycle and the load mask register cycle are used independently in the video RAM, thereby providing area and control signals. It also reduces the number of lines and power consumption.

Claims (4)

First logical combining means for logically combining the first selection signal for selecting the load write register cycle and the second selection signal for selecting the load color register cycle to generate a first control signal and a second control signal, and data from outside Data buffer means for buffering the data; a data line for loading data from the buffer means; and latch means for selectively latching data from the data line according to the first and second control signals of the first logical combining means. Second logical combining means for logically combining the signal from the latching means and the third control signal from the outside and supplying it to the mask register; and the logical combination of the signal from the latching means and the fourth control signal from the outside. Mask and color registers comprising a third logical combination means for supplying to a register A video RAM shared input path of the emitter. The electronic device of claim 1, wherein the latch unit comprises: first and second inverters connected in series, and first to selectively transmit data of the data line to the first inverter according to the first and second control signals. And a second transfer transistor connected between a transfer transistor and the first and second inverters to supply a signal from the second inverter to the first inverter in accordance with the first and second control signals. Video RAM that shares the input path of the mask and color registers. 2. The NOR gate according to claim 1, wherein the first logical combining means comprises: a NOR gate for outputting a first control signal by inverting the first and second selection signals and a second control signal by inverting the output of the NOR gate. A video RAM sharing an input path of a mask and a color register, characterized by having an inverter for outputting. The video RAM according to claim 1, wherein the second and third logical combining means are NAND gates.