KR20020096836A - Semiconductor circuit and apparatus having clock-synchronized circuit and internal power generating circuit - Google Patents

Abstract

PURPOSE: A semiconductor device having a clock synchronization circuit and an internal voltage circuit is provided to form a data parallel device operated under low voltage and low power by minimizing a loss of current. CONSTITUTION: An input process portion(400) receives an external clock(CLK), a clock bar(CLKB) and a power-down activation signal(PDNB,160), serial data(RXIN,162;RXINB,164), and a bonding pad input signal(BSIVC,440) from an external pin. The input process portion(400) provides signals(PDNB,RLB,PSIVC,RST,RSTB) for driving a data mapping portion(420) and an error correction portion(430) by using predetermined circuits. A PLL(Phase Locked Loop) device(110) is connected with an internal power generation portion including an inactive reference voltage generation portion(404), an active state internal power generation portion for peripheral device(406), an inactive state internal power generation portion for peripheral device(408), and an active state internal power generation portion for PLL device(406). A coding portion(414) is connected with the PLL device(110).

Description

Semiconductor circuits and apparatus having a clock synchronizing circuit and an internal voltage circuit TECHNICAL FIELD The present invention relates to a semiconductor circuit and a device having a clock synchronizing circuit and an internal voltage circuit.

The present invention relates to a semiconductor circuit and an apparatus for parallelizing serialized data for high speed data transfer.

In today's growing high-end processor systems, multimedia, virtual reality, and networks, higher data rates are required. However, the standard standards so far cannot respond to these demands.

Thus, in order to increase the processing power and performance of the device, a method of converting a conventional serial interface into a synchronous parallel interface has been shown. Further, a method of extending the transmission width from 8 bits to 32 bits or more, and using an ECL (Emitter Coupled Logic) and an optical fiber, were devised.

However, for this purpose, there are many problems such as the pros and cons of each interface, the complexity of countermeasures against electromagnetic interference (EMI), the increase in wire rods, the increase in power consumption, and the increase in price.

In order to satisfy the requirements of the high-speed data transmission, a new signal transmission method is an electrical specification for differential high-speed transmission called low voltage differential signaling (LVDS).

In order to serialize or parallelize high-speed data, the semiconductor chip has a phase-locked loop (PLL) or delay lock loop (DLL) synchronized with an external clock and synchronizes signals and data with an external clock to provide high speed data. Enable the transfer.

However, when 3.3V or 5.0V is used as an external power supply (External VCC or EVCC) and the chip is manufactured through a micro process for low power consumption, the operation of the internal circuit requires the circuit to operate at a lower voltage than the external power supply. There is.

In other words, according to the current market trend to reduce the chip size and lower the power, a control circuit that adopts an internal power source to embed a separate internal power generator inside the chip and adjusts it is required.

1 is a block diagram showing a schematic configuration of a data parallelizing apparatus incorporating a conventional clock synchronizing circuit, and FIGS. 2A to 2D are an input processing unit and a data mapping unit in a data parallelizing apparatus incorporating a conventional clock synchronizing circuit, respectively. 3 is a circuit diagram showing the configuration of an error correction unit and an output buffer unit, and FIG. 3 is a timing diagram of a data mapping circuit of a data parallelizing apparatus incorporating a conventional clock synchronizing circuit. A description of a transmission chip for parallelizing such serialized data is described in IEEE Journal of Solid State Circuits Vol. 33 NO.5 May 1998, "1.04 GBd Low EMI Digital Video Interface System Using Small Serial Link Technique".

Referring to FIG. 1, a data parallelizing apparatus incorporating a conventional clock synchronizing circuit includes an input processor 100, a power down mode setting switch 102, a PLL 110, a coding unit 118, and a plurality of data parallelizing apparatuses. The channel stage 120 includes a data mapping unit 130, an error correction unit 140, and an output buffer unit 150.

The input processing unit 100 includes a clock CLK, which is an external clock signal provided from a pin outside the chip, a clock bar CLKB, which is an inverted external clock signal, a power down enable signal PDNB, 160, serialized data RXIN, 162 and a signal for driving the power down mode setting switch 102, the data mapping unit 130, and the error correction unit 140 by using the inverted serialized data RXINB 164. (PDNB, RLB).

The power down activation signal PDNB 160 is normally maintained in the HIGH state and is set to the power down mode when the LOW signal is applied. The power down mode setting switch 102 of FIG. 1 serves to switch the power down mode by the power down activation signal PDNB 160. That is, the power down mode setting switch 102 serves as a switch to cut off powers of the respective circuits in the chip in the power down mode.

The PLL 110 includes a voltage controlled oscillator (VCO) 112, a phase frequency detector 114, a current amplifier 116, and the like. The PLL 110 generates seven distributed internal signals (for example, PLL <0>, PLL <1>, ..., PLL <6>) to synchronize and parallelize data to an external clock CLK. Create

The coding unit 118 receives and codes an output signal of the PLL 110 synchronized to an external clock CLK, and then outputs each PLL 110 output signal (for example, PLL <0>, PLL <1>, ..., PLL <6>) is applied to the plurality of channel stages 120. Data is separated into a plurality of channels through the channel stage 120. The data mapping unit 130 receives an output signal of the channel stage 120 and converts serial data into parallel data. The parallelized data is set through the error correction unit 140 (see FIG. 2C) provided in front of the output buffer unit 150, and the timing between each parallel data is adjusted and output through the output buffer unit 150 (see FIG. 2D). do.

Referring to FIG. 2A, when the HIGH signal is applied to the RXIN 162 and the LOW signal is applied to the RXINB 164, the RLB 202 output value becomes HIGH, and serial data input through the RXIN 162 is transferred to the output as it is. 2A may include a differential amplifier that is generally used.

2B is an example of a data mapping circuit implementing the data mapping unit 130. Referring to FIG. 2B, the data mapping circuit may be configured of a NAND gate and an inverter. The output RLD <i> 204-i of the data mapping circuit has a value of RLB <i> 202-i at the rising edge of PLL <i> 166-i, which is one of the PLL 110 outputs, and RLB has a LOW level value (eg, "0") at the falling edge of &lt; i &gt; For example, referring to FIG. 3, when the PLL <1> 166-1 is a rising edge, the RLB <1> 202-i value in the HIGH state is output as the RLD <1> 204-1. RLD <1> 204-1 falls to LOW on the falling edge where RLB <1> 202-1 falls from HIGH to LOW. The same applies to the PLL <6> (166-6), and a detailed description thereof will be omitted.

2C is an example of an error correction circuit implementing the error correction unit 140. Referring to FIG. 2C, the error correction circuit serves to adjust the timing between each parallel data parallelized through the data mapping unit 130. FIG. do. FIG. 2D illustrates an example of an output buffer circuit implementing the output buffer unit 150. Referring to FIG. 2D, the output buffer circuit outputs parallel data in which the timing is adjusted through the error correction unit 140 for high speed transmission. It plays a role.

In the conventional data paralleling apparatus incorporating a clock synchronizing circuit, 3.3 V or 5 V is used as an external power supply (EVCC), and the external power supply (EVCC) is used as an internal power supply of an internal component circuit of each data paralleling device without decompression. In particular, the external power supply EVCC is also used as the internal power supply without decompression in the voltage controlled oscillator VCO 112, the phase frequency detector PFD 114, and the current amplifier 116 of the PLL 110. In addition, even in the power-down mode, there is no separate circuit that can block the power inside the chip from being input to the internal component circuits of the data paralleling apparatus, and only the power-down mode setting switch 102 is used as the power-off switch.

That is, each internal configuration circuit of the conventional data paralleling device is operated at the same voltage as the external power supply EVCC in normal times and is operated so that the external power supply EVCC is cut off even in the power down mode. Low-voltage, low-power chips could not be implemented that operate at lower voltages and can effectively reduce current loss in power-down mode.

Accordingly, an object of the present invention is to provide a data paralleling circuit and a device having an internal power generation circuit that can operate at low voltage and low power by minimizing current loss. have.

In addition, an object of the present invention is to provide a data paralleling circuit and an apparatus incorporating an internal power generation circuit that can operate at low voltage and low power by minimizing current loss during power down.

In addition, an object of the present invention is to provide a data paralleling circuit and apparatus incorporating an internal power generator capable of ensuring a stable operation regardless of external voltage fluctuation by separating the internal power generating circuit into a plurality of supplies and supplying the internal power independently. Has its purpose.

1 is a schematic block diagram of a data parallelizing apparatus incorporating a conventional clock synchronizing circuit;

2A and 2D are circuit diagrams showing the configuration of an input processing unit, a data mapping unit, an error correcting unit, and an output buffer unit, respectively, in a data parallelizing apparatus incorporating a conventional clock synchronizing circuit.

3 is a timing diagram of a data mapping circuit of a data parallelizing device incorporating a conventional clock synchronizing circuit;

4A is a schematic structural block diagram of a data parallelizing apparatus incorporating a clock synchronizing circuit according to an exemplary embodiment of the present invention.

4B and 4C are schematic block diagrams of a data parallelizing apparatus incorporating a clock synchronizing circuit according to another exemplary embodiment of the present invention.

5A and 5B are circuit diagrams illustrating an input processing unit in a data parallelizing apparatus incorporating a clock synchronizing circuit according to a preferred embodiment of the present invention.

Fig. 6A is a circuit diagram showing the configuration of an active state internal power generation unit for a peripheral device of a data paralleling device incorporating a clock synchronizing circuit according to an embodiment of the present invention.

FIG. 6B is a circuit diagram illustrating a configuration of an inactive state internal power generation unit for a peripheral device of a data paralleling device incorporating a clock synchronizing circuit according to an exemplary embodiment of the present invention.

Fig. 7A is a circuit diagram showing the configuration of an active state internal power generation unit for a PLL device of a data paralleling device incorporating a clock synchronizing circuit according to a preferred embodiment of the present invention.

Fig. 7B is a circuit diagram showing the configuration of an inactive state internal power generation unit for the PLL device of the data paralleling device incorporating a clock synchronizing circuit according to an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating a configuration of a peripheral device and a PLL device in an inactive state internal power generation unit of a data parallelizing device incorporating a clock synchronization circuit according to an exemplary embodiment of the present invention. FIG.

Fig. 9 is a circuit diagram showing the configuration of a voltage controlled oscillator (VCO) of a PLL device in a data paralleling device incorporating a clock synchronizing circuit according to an embodiment of the present invention.

Fig. 10A is a circuit diagram showing the configuration of a data mapping unit in a data parallelizing apparatus incorporating a clock synchronizing circuit according to an embodiment of the present invention.

Fig. 10B is a circuit diagram showing the configuration of a data mapping unit in a data parallelizing apparatus incorporating a clock synchronizing circuit according to another preferred embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of an error correction unit in a data parallelizing apparatus incorporating a clock synchronizing circuit according to an exemplary embodiment of the present invention. FIG.

12A is a timing diagram of an inactive state internal power generation circuit of FIGS. 6B and 7B in accordance with one preferred embodiment of the present invention.

12B is a timing diagram of an activated state internal power generation circuit of FIGS. 6A and 7A according to one preferred embodiment of the present invention.

FIG. 13A is a timing diagram when the peripheral and PLL device combined inactive state internal power generation circuit of FIG. 8 operates in an inactive state according to one preferred embodiment of the present invention. FIG.

FIG. 13B is a timing diagram when the peripheral and PLL device combined inactive state internal power generation circuit of FIG. 8 operates in an active state according to one preferred embodiment of the present invention. FIG.

14 is a timing diagram illustrating an output signal generated by parallelizing serialized data using a data mapping circuit having a different number of inverter latches in a data parallelizing apparatus having an internal power generator according to an exemplary embodiment of the present invention. Degree.

<Description of the symbols for the main parts of the drawings>

110: PLL112: voltage controlled oscillator (VCO)

160: power down mode setting signal (PDNB)

406: activation state internal power generation unit for the peripheral device

408: Inactive state internal power generator for the peripheral device

410: active state internal power generation unit for the PLL device

412: Inactive state internal power generator for PLL device

420: data mapping unit 430: error correction unit

440: bonding pad input signal (BSIVC)

According to a first aspect of the present invention, a semiconductor device converts input data from serial to parallel or converts from parallel to serial by synchronizing an input signal and input data with an external clock using a clock synchronization circuit. A semiconductor device having an internal power generation circuit including an input processor, a reference voltage generator, and an internal power generator is provided. The input processor receives at least one of an external clock, data, a power down mode setting signal, and an internal power level setting signal, and the reference voltage generator receives the external power to provide a reference voltage obtained by depressing the external power to a predetermined magnitude. The internal power generator is coupled to an output terminal of the input processor and an output terminal of the reference voltage generator, respectively, and receives the reference voltage in response to the power down mode setting signal to generate internal power to be supplied to an internal circuit of the semiconductor device. .

The reference voltage generator may include an activation reference voltage generator providing an activation state reference voltage and an inactivation reference voltage generator providing an inactivation state reference voltage.

The internal power generator includes an active state internal power generator for a peripheral device, an active state internal power generator for a clock synchronizing circuit, an inactive state internal power generator for a peripheral device, and an inactive state internal power generator for a clock sync circuit. The activation state internal power generation unit for the peripheral device receives the activation state reference voltage in the activation state, and supplies the activation state internal power to an internal component circuit except the clock synchronizing circuit among the component circuits of the semiconductor device. The activation state internal power generator for the clock synchronization circuit receives the activation state reference voltage in the activation state, and supplies the activation state internal power to the clock synchronization circuit among the circuits of the semiconductor device. Deactivation state for the peripheral device The internal power generating unit receives the deactivation state reference voltage and the internal power level setting signal in the deactivation state, and supplies the deactivation state internal power to an internal configuration circuit except the clock synchronization circuit among the circuits of the semiconductor device. do. The inactive state internal power generator for the clock synchronizing circuit receives the inactive state reference voltage and the internal power level setting signal in the inactive state, and supplies the inactive state internal power to the clock synchronizing circuit among the circuits of the semiconductor device.

In the activation state, the activation state internal power generation unit for the peripheral device, the activation state internal power generation unit for the clock synchronization circuit, the deactivation state internal power generation unit for the peripheral device, and the deactivation state internal power generation unit for the clock synchronization circuit may be activated. . In an inactive state, the inactive state internal power generator for the peripheral device and the inactive state internal power generator for the clock synchronization circuit may be activated.

In an activated state or an inactivated state, an internal power level output from the internal power generator for the clock synchronizing circuit and an internal power level output from the internal power generator for the peripheral device may be different from each other. In addition, in an activated state or inactivated state, the internal power level output from the internal power generator for the clock synchronizing circuit may be higher than the internal power level output from the internal power generator for the peripheral device.

When the internal power level setting signal is the first level in the inactive state, the output voltage of the inactive state internal power generation unit for the clock synchronizing circuit is set to a voltage having a predetermined level lower than the external power level, and the internal in the inactive state. When the power supply level setting signal is the second level, the output voltage of the inactive state internal power generation unit for the clock synchronizing circuit may be set to the ground potential level.

The active state internal power generator for the peripheral device includes first and second PMOS transistors having a source terminal coupled to an external power source, a gate terminal coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor coupled to the drain terminal of the first PMOS transistor and having a reference voltage in the activation state as a gate input, and a drain terminal coupled to a source terminal of the first NMOS transistor and supplying a power down activation signal to a current path; A third NMOS transistor that forms a current path to a ground potential as a gate input for use as a switch of a third transistor; a third PMOS transistor whose source terminal is coupled to the external power source and whose power-down enable signal is a gate input; The terminal is coupled with the external power supply and the gate terminal is A fourth PMOS transistor coupled with the drain terminal of the third PMOS transistor, the drain terminal being used as an output terminal for outputting an internal power source of the active state internal power generation unit for the peripheral device, and a source terminal coupled with the external power source; A fifth PMOS transistor and a drain terminal, the gate terminal of which is coupled with the drain terminal of the third PMOS transistor and the drain terminal of the first PMOS transistor, are coupled to the drain terminal of the second PMOS transistor, and the source terminal of the first NMOS transistor. A second NMOS transistor coupled to a source terminal of a second gate terminal coupled to a drain terminal of the fourth and fifth PMOS transistors and feeding an output internal power of an active state internal power generation unit for the peripheral device as a gate input; Can be.

The inactive state internal power generator for the peripheral device includes first and second PMOS transistors having a source terminal coupled to an external power source, a gate terminal coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor coupled to a drain terminal of the first PMOS transistor and having the inactive state reference voltage as a gate input, and a drain terminal coupled to a source terminal of the first NMOS transistor and the inactive state reference voltage as a gate input A third NMOS transistor, a fourth NMOS transistor having a drain terminal coupled to a source terminal of the third NMOS transistor, a source terminal coupled to a ground power supply, and having an internal power supply level setting signal as a gate input when in an inactive state; Is coupled with the external power source A third PMOS transistor having a gate terminal coupled to a drain terminal of the first PMOS transistor, a first resistor having one end coupled to a drain terminal of the third PMOS transistor, and a second end coupled to the other end of the first resistor A fifth NMOS transistor having a resistor, a drain terminal coupled to the other end of the second resistor, a source terminal coupled to the ground power supply, and a gate input for using an internal power level setting signal as a switch of a current path in the inactive state And a drain terminal coupled to the drain terminal of the second PMOS transistor, a source terminal coupled to the source terminal of the first NMOS transistor, and connected to one end of the second resistor to be divided by the first and second resistors. The second NMOS transistor may be fed back to form a gate input. The deactivation state internal power generation unit for the peripheral device uses the drain terminal of the third PMOS transistor as an output terminal, and the output terminal voltage is smaller than the ground potential level or the external power supply in response to the internal power level setting signal in the deactivation state. It can have an internal power supply potential level of magnitude.

The active state internal power generation unit for the clock synchronizing circuit includes first and second PMOS transistors having a source terminal coupled to an external power source, a gate terminal coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; Are coupled to a drain terminal of the first PMOS transistor, and the first and second NMOS transistors connected in parallel with each other with the activation state reference voltage as a gate input, and the drain terminals are coupled to source terminals of the first and second NMOS transistors. And a fourth NMOS transistor configured as a gate input to form a current path to the ground potential for use as a switch of the current path, and a source terminal coupled to the external power supply, and a power down activation signal to the gate input for use as a switch of the current path. A third PMOS transistor and a source terminal A fourth PMOS transistor coupled to a circle and having a gate terminal coupled to a drain terminal of the third and first PMOS transistors, the drain terminal being used as an output terminal for outputting an internal power supply of an active state internal power generation portion for the clock synchronization circuit; And a drain terminal is coupled to the drain terminal of the second PMOS transistor, a source terminal is coupled to the source terminal of the first and second NMOS transistors, and a gate terminal is coupled to the drain terminal of the fourth PMOS transistor. And a third NMOS transistor which feeds back the output internal power of the active state internal power generator to serve as a gate input.

The inactive state internal power generation unit for the clock synchronizing circuit includes first and second PMOS transistors having a source terminal coupled to an external power source, a gate terminal coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; Is coupled to the drain terminal of the first PMOS transistor, the first NMOS transistor having the inactive state reference voltage as its gate input, and the drain terminal is coupled to the source terminal of the first NMOS transistor, and the inactive state reference voltage is gated in. A third NMOS transistor and a drain terminal coupled to a source terminal of the third NMOS transistor, and forming a current path to a ground potential by using a gate input to use the internal power level setting signal as a switch of a current path. Fourth NMOS transistor and source terminal A third PMOS transistor coupled to the external power source and having a gate terminal coupled to the drain terminal of the first PMOS transistor, a first resistor having one end coupled to the drain terminal of the third PMOS transistor, and the other end of the first resistor; A fifth NMOS transistor and a drain terminal having a second resistor coupled at one end, a drain terminal coupled to the other end of the second resistor, a source terminal coupled to the ground power supply, and the internal power level setting signal serving as a gate input; A gate input coupled to a drain terminal of a second PMOS transistor and a source terminal coupled to a source terminal of the first NMOS transistor and coupled to one end of the second resistor to feed back the divided voltages of the first and second resistors. And a second NMOS transistor. The inactive state internal power generator for the clock synchronizing circuit uses a drain terminal of a third PMOS transistor as an output terminal, and the output terminal voltage is smaller than the ground potential level or the external power source in correspondence with the internal power level setting signal. Can have a power supply potential level.

In addition, the inactive state internal power generator for the clock synchronizing circuit and the inactive state internal power generator for the peripheral device may have a source terminal coupled to an external power source and gate terminals coupled to each other, and the gate terminal may be connected to a drain terminal of the second PMOS transistor. A first NMOS transistor coupled to the first and second PMOS transistors, a drain terminal coupled to the drain terminal of the first PMOS transistor, the first NMOS transistor having a reference voltage in the inactive state as a gate input, and a drain terminal connected to the first NMOS transistor; A third NMOS transistor coupled to the source terminal of the transistor as a gate input of the reference voltage in the inactive state, and a drain terminal coupled to the source terminal of the third NMOS transistor, and configured to supply the internal power level setting signal to a switch in a current path; Grounded as a gate input for use as A fourth NMOS transistor forming a current path to a potential, a third PMOS transistor having a source terminal coupled to the external power supply and a gate terminal coupled to the drain terminal of the first PMOS transistor, and a drain terminal being the third PMOS A fifth NMOS transistor and a drain terminal coupled to the drain terminal of the transistor and serving as the gate input of the internal power level setting signal are coupled to the drain terminal of the second PMOS transistor, and a source terminal coupled to the source terminal of the first NMOS transistor The gate terminal may include a fifth NMOS transistor coupled to the drain terminal of the third PMOS transistor. The deactivation state internal power generation unit for the clock synchronizing circuit and the deactivation state internal power generation unit for the peripheral device use the drain terminal of the third PMOS transistor as an output terminal, and the output terminal voltage corresponding to the internal power level setting signal level. It may have an internal power supply potential level of a predetermined magnitude smaller than this ground potential level or the external power supply.

The activation reference voltage generator and the deactivation reference voltage generator are connected between the external power source and the ground potential to generate an output voltage according to a predetermined resistance ratio or resistance ratio of a transistor, respectively, and the output voltage of the activation reference voltage generator is deactivated. The output voltage of the reference voltage generator may be greater than twice.

According to another embodiment of the present invention, there is provided a data parallelizing apparatus having an internal power generation circuit including an input processing unit, a reference voltage generator, an internal power generator, a clock synchronizing circuit, a data mapping unit, an error correction unit, and an output buffer unit. do. The input processor receives at least one of an external clock, data, a power down mode setting signal, and an internal power level setting signal. The reference voltage generator receives an external power and provides a reference voltage by depressing the external power to a predetermined size. The internal power generation unit is coupled to an output terminal of the input processor and an output terminal of the reference voltage generator, respectively, and receives the reference voltage in response to the power down mode setting signal to generate internal power to be supplied to an internal circuit of the semiconductor device. The clock synchronizing circuit includes a voltage control oscillator coupled to an output terminal of the internal power generation unit to generate a predetermined number of clock synchronizing signals having different phases synchronized with an external clock. The data mapping unit is coupled to an output terminal of the internal power generation unit and converts the serially input data into a plurality of channels by coding the clock synchronizing signal and converting the data into parallel data. The error correction unit is coupled to an output terminal of the internal power generation unit to receive output data of the data mapping unit and corrects timing errors between respective parallel data. The output buffer unit receives the external power and combines with the output terminal of the error correction unit to transmit the output data of the error correction unit at high speed. The reference voltage generator may include an activation reference voltage generator providing an activation state reference voltage and an inactivation reference voltage generator providing an inactivation state reference voltage.

Here, the internal power generation unit is an activation state internal power supply for the peripheral device that receives the activation state reference voltage in the activation state and supplies the activation state internal power to the internal configuration circuits other than the voltage control oscillator among the component circuits of the semiconductor device. An activation state internal power generation unit for a clock synchronization circuit which receives the activation state reference voltage and supplies an activation state internal power to the voltage control oscillator among the circuits of the semiconductor device; A deactivation state internal power generation unit and a deactivation state for the peripheral device receiving the deactivation state reference voltage and the internal power level setting signal and supplying the deactivation state internal power to an internal configuration circuit except the voltage control oscillator among the circuits of the semiconductor device; Status And an inactive state internal power generator for a clock synchronization circuit configured to receive the inactive state reference voltage and the internal power level setting signal and supply an inactive state internal power to the voltage control oscillator among the circuits of the semiconductor device. The predetermined number of clock synchronizing signals may be seven clock synchronizing signals.

The data mapping circuit may include a first data mapping unit and a second data mapping unit. The first data mapping circuit receives a serially input data and is coupled to a first transfer transistor configured to pass the serially inputted data using the first clock synchronizing signal as a control input, and coupled to an output terminal of the first transfer transistor. A first inverter latch for latching an output of a first transfer transistor, a second transfer transistor for passing an output of the first inverter latch using the second and third clock synchronization signals as a control input, and And a second inverter latch coupled to an output terminal for latching an output of the second transfer transistor. The first data mapping unit uses the output voltage of the internal power generation unit as a power source, receives the first to third clock synchronization signals, and uses a plurality of inverter latches to refer to a predetermined number of data serially referenced to an external clock. In this state, the latch is latched for one period to convert to parallel data. The second data mapping circuit receives a serially input data and is coupled to a third transfer transistor configured to pass the serially input data through the fourth clock synchronizing signal as a control input, and coupled to an output terminal of the third transfer transistor. A third inverter latch for latching an output of a third transfer transistor, and an output terminal of the third inverter latch as an input, and a fifth and sixth clock synchronizing signal as a control input to pass the output of the third transfer transistor. A fourth transfer transistor, a fourth inverter latch coupled to an output terminal of the fourth transfer transistor to latch an output of the fourth transfer transistor, and an output of the fourth inverter latch as an input to control the fourth clock synchronizing signal; A fifth transfer passing through the output of the fourth inverter latch as an input; And a fourth inverter latch coupled to an output terminal of the fifth transfer transistor, the fourth inverter latch for latching the output voltage of the fifth transfer transistor, and an inverter for inverting and outputting the output of the fourth inverter latch. The second data mapping unit uses the output voltage of the internal power generation unit as a power source, receives the fourth to sixth clock synchronizing signals, and outputs a predetermined number of data serially inputted using an inverter latch of three stages. As a reference, it latches in parallel for one period and converts to parallel data.

According to a second aspect of the present invention, an external clock, data, a power down mode setting signal and an internal power level setting signal may be input, generate a reference voltage obtained by depressing an external power supply to a predetermined magnitude, and generate the reference. A voltage is used to generate an internal power source to be supplied to an internal circuit of the semiconductor device in response to the power down mode setting signal, and a predetermined number of predetermined phases of different phases synchronized with an external clock are generated by using the generated internal power source voltage as a power source. There is provided a data paralleling method using an internal power supply, including generating a clock synchronizing signal, and converting a predetermined number of serially input data into parallel data using the clock synchronizing signal for one period. The data parallelization method using the internal power supply may further include receiving the converted parallel data, correcting a timing error between the parallel data, and outputting the converted parallel data using an output buffer.

Hereinafter, a preferred embodiment of a data parallelizing apparatus and method having an internal power generation circuit according to the present invention will be described in detail with reference to the accompanying drawings.

4A is a schematic block diagram illustrating a data parallelizing apparatus incorporating an internal power generator according to an exemplary embodiment of the present invention. FIGS. 5A and 5B are diagrams illustrating an internal power generator in accordance with an exemplary embodiment of the present invention. It is a circuit diagram which comprises an input processing part in a data parallelizing apparatus.

Referring to FIG. 4A, a data paralleling apparatus incorporating an internal power generator includes an input processor 400, an activation reference voltage generator 402, an inactivation reference voltage generator 404, and an active state internal power generator for a peripheral device ( 406, peripheral state inactive power source generator 408, PLL device in active state internal power generator 410, PLL device inactive state internal power generator 412, internal power generator 404, PLL device 110 connected to the outputs of 406, 408, and 410, a coding unit 414 connected to the PLL device 110, a plurality of channel stages 120, a data mapping unit 420, and an error correction unit 430. And an output buffer unit 150.

The input processor 400 includes an external clock CLK, a clock bar CLKB, a power down enable signal PDNB 160, serialized data RXIN 162 RXINB 164, and a bonding pad provided from pins outside the chip. The input signal BSIVC 440 is received. The bonding pad input signal BSIVC 440 refers to a signal for setting an output internal power level of an inactive state internal power generator to a voltage or GND of a predetermined size through a bonding pad on a wafer of a semiconductor device.

Examples of the circuit for implementing the input processor 400 may be the circuits of FIGS. 5A and 5B and the circuits shown in FIG. 2A although omitted in FIGS. 5A and 5B. The input processor 400 provides signals PDNB, RLB, PSIVC, RST, and RSTB for driving the data mapping unit 420 and the error compensator 430 using the circuits of FIGS. 2A, 5A, and 5B. do.

FIG. 5A illustrates an internal power generator using a bonding pad to generate a PSIVC 502 signal for controlling ON / OFF of an internal power generator, which will be described later, using the bonding pad input signals BSIVC and 440 in the input processing unit 400. OFF control circuit.

Referring to FIG. 5A, an internal power generator ON / OFF control circuit using a bonding pad includes three series-connected inverter circuits that use a BSIVC 440 as an input and use an external power source (EVCC) as a power source.

According to the internal power generator ON / OFF control circuit using the bonding pad, the PSIVC 502 value is determined according to the BSIVC 440 value. That is, if the BSIVC 440 value is HIGH, the PSIVC 502 value is LOW. If the BSIVC 440 value is the floating state or the LOW state, the PSIVC 502 value is HIGH. (FIGS. 13A and FIG. 13b)

FIG. 5B is a circuit for generating a reset signal for controlling the operation of each component circuit such as the data mapping unit 420 and the error correction unit 430 of the data parallelizing apparatus having the internal power generator.

Referring to FIG. 5B, a circuit for generating the reset signal is an external power source (EVCC) as a power source, and is connected to a NAND gate and a NAND gate output having a power down enable signal (PDNB) 160 and a power on application signal as inputs. It includes two inverter circuits combined.

The circuit for generating the reset signal may have the RST (504) signal high when the power down activation signal (PDNB) 160 is HIGH in a state where power is applied to a data paralleling device having an internal power generator. Keep it. When the power down enable signal PDNB 160 is LOW—in power down mode—or when power is not yet applied to the data paralleling device incorporating an internal power generator, the RST 504 value is LOW.

In the present invention, in order to supply low voltage and low power to the PLL 110 device and other component circuits in the data paralleling device, an internal power generation circuit for generating an internal power source separate from an external power source is provided. In other words, the chip operation is divided into a power down mode (hereinafter referred to as an inactive state) and a non power down mode (hereinafter referred to as an activated state). The low power chip is implemented using the voltage VREFP 403 and using the reference voltage VREF 405 lower than the reference voltage in the inactive state.

The power down mode is a case where the value of the power down activation signal PDNB 160 is LOW. In an inactive state, the internal power level value may be preferably selected from two levels. In the present invention, the internal power level is set to a value smaller than the external power level or lowered to the GND level using the BSIVC 440, which is a bonding pad input signal.

For example, when a floating state or a LOW value is applied to the BSIVC 440, which is a bonding pad input signal, the internal power level is set to a value smaller than the external power level, and the HIGH value is set to the BSIVC 440. In the case of application, the internal power level may be set to the GND level. Alternatively, the BSIVC 440 value may be set in the reverse direction.

12A and 13A, when the BSIVC 440 value has a floating state or a LOW value when the power down enable signal PDNB 160 is LOW, the PSIVC 502 value is changed. It can be seen that the value of IVC 409 and PLL_IVC 413, which are output voltages of the internal power generation circuit, is set to 0.1V lower than the reference voltage VREFP.

12B and 13B, when the BSIVC 440 has a HIGH value when the power down activation signal PDNB 160 is LOW, the PSIVC 502 value is LOW, and Accordingly, it can be seen that the values of IVC 409 and PLL_IVC 413, which are output voltages of the internal power generation circuit, fall to the VND value of the GND level when the current is consumed after a predetermined time.

In order to set the internal power as above to a value smaller than the external power level, for example, the output terminal of the internal power generation circuit may be divided by a constant resistance ratio (see R1 and R2 of FIG. 6B and R3 and R4 of FIG. 7B). . Also, in order to set the internal power level to the GND level, for example, the output terminal of the internal power generation circuit-the drain terminal of the NMOS 812 in FIG. 8-using the PSIVC 502 controlled by the BSIVC 440 as a control signal. Can be controlled. Detailed description will be described later.

The activation reference voltage generator 402 generates a reference voltage VREFP 403 to be used as an internal power supply in an activated state, and a detailed implementation thereof can be easily performed using a voltage divider circuit using a resistor. The deactivation reference voltage generator 404 generates a reference voltage VREF 405 to be used as an internal power supply in a power-down mode (or deactivation state) and can be easily implemented by using a voltage divider circuit using a resistor.

The active state internal power generation unit 406 for the peripheral device is to supply the internal power in the active state to the peripheral device except the PLL 110 device in the data parallelization device, and the inactive state internal power generation unit 408 for the peripheral device. Is to supply internal power to the peripheral device in an inactive state. The active state internal power generator 410 for the PLL device is for supplying internal power in the activated state to the PLL 110 device in the data parallelization device. The inactive state internal power generator 412 for the PLL device is the PLL 110. This is to supply internal power when the device is in inactive state. Detailed description will be described later.

In the present invention, different internal power sources are applied to the PLL 110 circuit and other peripheral circuits among the internal configuration circuits of the data paralleling apparatus. For example, the internal power level for the PLL 110 device may be set higher than the internal power level for the peripheral device. Referring to FIG. 4B, the PLL_IVC 413, which is an internal power supply for the PLL device, is applied to the voltage controlled oscillator VCO 112, the phase frequency detector PFD 114, and the current amplifier 116, which are the PLL 110 configuration circuits. The IVC, which is an internal power source for the peripheral device, is applied to the data mapping unit 420, the error correcting unit 430, and the like.

Alternatively, among the PLL 110 devices, only the voltage control oscillator VCO 112 may apply a higher internal power source than other internal configuration circuits. Referring to FIG. 4A, the PLL_IVC 413, which is an internal power supply, is applied only to the voltage controlled oscillator VCO 112, and the phase frequency detector PFD 114, the current amplifier 116, the data mapping unit 420, and an error are provided. The correction unit 430 or the like is applied with IVC, which is an internal power source for the peripheral device.

Alternatively, the same internal power source may be applied to all internal configuration circuits. Referring to FIG. 4C, an internal power supply IVC 409 is applied to all internal configuration circuits.

The PLL device 110 is composed of a voltage controlled oscillator (VCO) 112, a phase frequency detector (PFD) 114, a current amplifier 116, and the like, and a PLL output signal synchronized with an external clock (eg, PLL <0). >, PLL <1>, ..., PLL <6>).

FIG. 9 is a circuit diagram illustrating a configuration of a voltage controlled oscillator (VCO) 112 of a PLL 110 apparatus in a data paralleling apparatus having an internal power generator according to an exemplary embodiment of the present invention.

Referring to FIG. 9, in the data paralleling device of the present invention, the voltage controlled oscillator (VCO) 112 has seven inverters connected in series in a feedback manner, and the PLL_IVC 413 which is an internal power supply for the PLL 110 device from an internal power generator. It works by being supplied. The voltage-controlled oscillator (VCO) 112 used in the data parallelizer uses PLL outputs -PLL <0>, PLL <1>, ..., PLL <divided into seven phases with different phases using an external clock (CLK) signal. 6>- The PLL output signal is provided to the data mapping unit 420 via a plurality of channel stages 120 and used to parallelize the serialized data.

The PLL output signal is connected to a plurality of channel stages-for example, channels <0>, channels <1>, ..., channels <N>-by the coding unit 414 connected to the PLL device 110. After being allocated in a predetermined order, it is input to the data mapping unit 420.

The data parallelizing apparatus of the present invention may use a delay lock loop (DLL) circuit instead of the PLL 110 circuit as a clock synchronization circuit.

The data mapping unit 420 parallelizes serially input data using a PLL output signal. 10A and 10B illustrate specific implementation circuits of the data mapping unit 420 in the data parallelizing apparatus incorporating an internal power generator of the present invention. Detailed description will be described later.

The error correcting unit 430 removes skew between the inputs of the data mapping unit 420 and writes them to the output buffer unit 150 (see FIG. 11).

The output buffer unit 150 is configured as a TTL (Transfer to Transfer Logic) buffer and is an output terminal for high-speed transmission of each parallelized data that has passed through the error correction unit 430.

FIG. 6A is a circuit diagram illustrating a configuration of an active state internal power generator 406 for a peripheral device of a data paralleling apparatus incorporating an internal power generator according to an exemplary embodiment of the present invention. The activation state internal power generation unit 406 for the peripheral device may be configured as a differential amplifier as a device for generating internal power supplied to the peripheral device in the activation state.

Referring to FIG. 6A, an active state internal power generator 406 for a peripheral device includes a portion 602 configured in a current mirror type using two PMOS transistors, and a drain terminal is connected to the drain terminal of the PMOS transistor. The drain terminal is coupled to the drain terminal of the NMOS transistor 604a and NMOS transistor 604a having the reference voltages VREFP and 403 as gate inputs in an activated state, and the power-down activation signal PDNB 160 is used as the gate input. NMOS transistor 606, the source terminal is coupled to an external power supply (EVCC), the PMOS transistor 608 having a power down enable signal (PDNB, 160) as a gate input, the source terminal is coupled to an external power supply (EVCC) and gate A PMOS transistor 612 whose terminal is coupled with the drain terminal of the PMOS transistor 608, the source terminal is coupled with an external power supply (EVCC) and the gate terminal is the drain of the PMOS transistor 608 Here, the PMOS transistor 610 is coupled with the gate terminal of the PMOS transistor 612 and the drain terminal of the current mirrored PMOS transistor, the drain terminal is coupled to the drain terminal of the current mirrored PMOS transistor, and the source terminal is the NMOS transistor. A NMOS transistor 604b coupled to the source terminal of 604a and having a gate terminal coupled to the drain terminal of the PMOS transistors 610 and 612 and feeding back the IVC 409 as a gate input.

In the activated state, the active state internal power generation circuit 406 for the peripheral device is activated and its output voltage operates to maintain the VREFP 403 level, and in the inactive state the activated state internal power generation circuit 406 for the peripheral device is active. Is deactivated (OFF).

Current state is interrupted by using the NMOS transistor 606 with the power-down enable signal PDNB 160 as the gate input to turn off the internal power generation circuit 406 for peripheral devices in the inactive state. do.

FIG. 6B is a circuit diagram illustrating a configuration of an inactive state internal power generator 408 for a peripheral device of a data paralleling device incorporating an internal power generator according to an exemplary embodiment of the present invention. The inactive state internal power generator 408 for the peripheral device may be configured as a differential amplifier as a device for generating internal power supplied to the peripheral device in the inactive state.

Referring to FIG. 6B, an inactive state internal power generator 408 for a peripheral device may include a portion 602 configured as a current mirror using two PMOS transistors, and a drain terminal coupled to a drain terminal of the current mirror PMOS transistor. And a drain terminal is coupled to the drain terminal of the NMOS transistor 620a having the reference voltages VREF and 405 as gate inputs in the inactive state, and the NMOS transistor 622 having the VREF 405 as a gate input. NMOS transistor 624 having a drain terminal coupled to the source terminal of the NMOS transistor 622 and having an internal power level setting signal PSIVC 502 as a gate input when inactive, and a source terminal coupled with an external power supply EVCC. And a gate terminal in series with the drain terminal of the PMOS transistor 626 and the PMOS transistor 626 coupled to the drain terminal of the current mirrored PMOS transistor. The combined resistors R1 and R2, the drain terminal is coupled to one end of the R2 resistor, the NMOS transistor 632 having the PSIVC 502 signal as the gate input, the drain terminal is coupled to the drain terminal of the current mirrored PMOS transistor. The source terminal is coupled to the source terminal of the NMOS transistor 620a and includes an NMOS transistor 620b connected to a connection point of the R1 and R2 resistors to feed back the divided voltage by the R1 and R2 resistors as a gate input.

In the activated state, the inactive state internal power generation circuit 408 for the peripheral device is activated and its output voltage operates to maintain the VREFP 403 level, and in the inactive state controls the internal power level setting signal PSIVC 502. Use the input to adjust the output voltage level. In order to adjust the output voltage level using the PSIVC 502, the PSIVC 502 is used as a gate input of the NMOS transistors 624 and 632 as a switch of the current path, thereby blocking the current path to the ground potential in the inactive state. .

Referring to the operation of the inactive state internal power generation circuit 408 for the peripheral device, when the PSIVC 502 is HIGH, the NMOS transistors 622, 624, and 632 are turned on so that the output voltage is divided by a predetermined resistance ratio. In the case where the PSIVC 502 is LOW, the NMOS transistors 624 and 632 are turned off and have a potential of the GND level when the current is consumed after a predetermined time.

FIG. 7A is a circuit diagram illustrating a configuration of an active state internal power generator 410 for a PLL device of a data paralleling device having an internal power generator according to an exemplary embodiment of the present invention. Hereinafter, the differences from the circuit of FIG. 6A will be described.

In FIG. 6A, one NMOS transistor 604a having a VREFP 403 as a gate input is used, and in FIG. 7A, two NMOS transistors 604a and 604b are used to connect the NMOS transistors than in FIG. 6A. The area is large.

In addition, as a PMOS transistor existing between an external power supply (EVCC) and an internal power supply as an output, a PMOS transistor is used in FIG. 7A using one PMOS transistor 610 in FIG. 6A than in the case of using two PMOS transistors 610 and 612 in FIG. The junction area of is small.

In the activated state, the active state internal power generation circuit 410 for the PLL device is activated and its output voltage operates to maintain the VREFP 403 level, and in the inactive state, the active state internal power generation circuit 410 for the peripheral device is inactive. Is deactivated (OFF).

7B is a circuit diagram illustrating a configuration of an inactive state internal power generator 412 for a PLL device of a data paralleling device having an internal power generator according to an exemplary embodiment of the present invention. Since the circuit configuration and operation of FIG. 6B are the same as those of FIG. 7B, descriptions thereof will be omitted. The difference from FIG. 6A is that the internal power supplied to the PLL device in the inactive state in FIG. 7B is greater than the internal power level supplied to the peripheral device of FIG. 6B.

FIG. 8 is a circuit diagram illustrating a configuration of a peripheral device and a PLL device in a deactivated state internal power generator of a data parallelizing device having an internal power generator according to an exemplary embodiment of the present invention. Hereinafter, the difference between the implementation circuit of the peripheral power supply unit and the PLL device combined inactive state internal power generation unit of FIG. 8 and the circuits of FIGS. 6B and 7B will be described.

The internal power generator circuit of the peripheral device and the PLL device in a deactivated state of FIG. 8 is different from the circuits of FIGS. 6B and 7B in that the internal power output circuit has no resistance. The operating principle is the same as the circuit of FIGS. 6B and 7B and operates to bring the output internal power supply value down to the GND level in an inactive state by the PSIVC 502 control signal.

In the present invention, serialized data is parallelized by using two first and second data mapping units having different numbers of inverter latches used.

The first data mapping unit (FIG. 10A) uses the output voltage of the internal power generation unit as a power source, receives three PLL output signals, and uses a plurality of inverter latches to input a predetermined number of data based on a clock. It latches for one period in parallel and converts it to parallel data. The second data mapping unit (see FIG. 10B) receives the PLL output signal used in the first data mapping unit and the remaining three clock synchronization signals and clocks a predetermined number of data serially input using three inverter latches. Based on this, the data is latched for one period in parallel and converted into parallel data.

Referring to FIG. 10A, a first data mapping unit of the data mapping unit 420 receives an RLB 202 signal as an input, an input of the inverter, and a PLL <6> as a control input via two serially connected inverters. An inverter having an inverter connected to the output terminal of the transfer transistor 1012 and the transfer transistor 1012 and having a drain terminal of a PMOS transistor having an RSTB 506 as a gate input at an input terminal thereof, and feedback between the output terminal and the input terminal. Transfer transistor 1016 and transfer transistor 1016 which use the output of the latch 1014 and the inverter latch 1014 as inputs, and the PLL <2> and PLL <3> signals as control inputs through the NAND circuit 1010 and the inverter. The output of the inverter latch 1018 and the inverter latch 10180, in which an NMOS transistor having an RST (504) signal as a gate input is coupled to the input terminal as an input. And comprises an inverter coupled between the input return ever.

The first data mapping unit of the data mapping unit 420 receives serially input data through an inverter and receives PLL <6> through two inverters as gates of a PMOS transistor and an NMOS transistor of the transfer transistor 1012.

The inverter latch 1014 of the first stage is coupled to the output terminal of the transfer transistor 1012 to latch the output of the transfer transistor 1014.

The transfer transistor 1016 receives the output terminal of the inverter latch 1014 as an input and receives the PLL <2> and PLL <3> signals as inputs of the NAND circuit 1010, and the output of the NAND circuit 1010 as a gate input. When the signals <2> and PLL <3> are all at the HIGH level, the output of the transfer transistor 1012 is passed through. The inverter latch 1018 of the second stage is coupled to the output terminal of the transfer transistor 1016 to latch and output the output of the transfer transistor 1016. Each of the inverter latches 1014 and 1018 may be turned off using a reset (RST) signal 504 (RSTB, 506).

Referring to FIG. 10B, the second data mapping unit (see FIG. 10B) is configured to receive an RLB 202 signal as an input, an inverter as an input, and a PLL <1> as a control input via two serially connected inverters. A drain terminal of a PMOS transistor having an output of the transfer transistor 1052 and the transfer transistor 1052 as an input and an RSTB 506 as a gate input is connected to the input terminal, and an inverter for feedbackly connecting the input terminal and the output terminal is coupled. A transfer transistor 1056 and a transfer transistor which input the outputs of the inverter latch 1054 and the inverter latch 1054 and control the PLL <4> and PLL <5> signals as control inputs through the NAND circuit 1010 and the inverter. An NMOS transistor having an output of 1056 as an input and an RST (504) signal as a gate input is coupled to the input terminal, and an inverter connected feedback between the output terminal and the input terminal. Inputs of the outputs of the transfer transistor 1060 and the transfer transistor 1060 having the output of the inverter latch 1058 and the inverter latch 1058 having the control input and the PLL <1> as control inputs through two series-connected inverters And an inverter coupled to the output terminal of the inverter latch 1058 and an inverter latch 1058 having an inverter coupled back to the output terminal and the input terminal coupled to the PMOS transistor having the RSTB 506 signal as a gate input. do.

The second data mapping unit (see FIG. 10B) receives serially input data through an inverter input terminal, and the transfer transistor 1052 receives a PLL <1> signal as a gate input of a PMOS transistor and an NMOS transistor.

The inverter latch 1054 of the first stage is coupled to the output terminal of the transfer transistor 1052 to latch the output of the transfer transistor 1052.

The transfer transistor 1056 receives the output terminal of the inverter latch 1054 of the first stage and receives the PLL <4> and PLL <5> signals as the inputs of the NAND circuit 1050, and the output of the NAND circuit 1050 is gated. In this case, when the PLL <4> and PLL <5> signals are both at the HIGH level, the output of the transfer transistor 1056 is passed through. The inverter latch 1058 of the second stage is coupled to the output terminal of the transfer transistor 1056 to latch the output of the transfer transistor 1056.

The transfer transistor 1060 receives the output of the inverter latch 1056 of the second stage as an input and receives the PLL <1> signal as a gate input, and outputs the inverter latch 1056 of the second stage when the PLL <1> signal is HIGH. Pass it through. The inverter latch 1062 of the third stage is coupled to the output terminal of the transfer transistor 1060 to latch the output voltage of the transfer transistor 1060. The output of the inverter latch 1062 of the third stage is inverted again and output as an RLD 204 signal. Each of the inverter latches 1054, 1058, and 1062 may be turned off using a reset (RST, 504) signal.

FIG. 11 is a circuit diagram illustrating a configuration of an error correcting unit 430 in a data parallelizing apparatus incorporating an internal power generator according to an exemplary embodiment of the present invention.

Referring to FIG. 11, the error compensator 430 receives two PMOS transistors and an RLD <i> signal, each of which has its gate terminal connected to the drain of another PMOS transistor, by receiving an external power supply EVCC. The NMOS transistor 1106 and RSTB 506 signal serving as a gate input are applied as gate inputs, and an NMOS transistor 1110 and an external power source (EVCC) having a drain terminal coupled to a source terminal of the NMOS transistor 1106 are applied thereto. A NOR circuit 1112 that receives the drain outputs of two PMOS transistors and an RST 504 signal as inputs, a drain terminal coupled with the drain outputs of the two PMOS transistors, and a source terminal coupled with the source terminal of the NMOS transistor 1106. And an NMOS transistor 1108 having a RLD <i> signal as a gate input via two inverters 1102 and 1104.

The error correction unit 430 converts the internal power level into a signal of the external power level using the level shifter composed of the differential amplifier and the NOR circuit 1112 as described above, and skews according to the difference in delay time between the data. ) It prevents the phenomenon.

14 is a timing diagram illustrating an output signal generated by parallelizing serialized data using a data mapping circuit having a different number of inverter latches in a data parallelizing apparatus having an internal power generator according to an exemplary embodiment of the present invention. It is also.

Referring to FIG. 14, RLB <6> which is data input in series with PLL <6> is subjected to parallelization through a two-step inverter latch as described in FIG. 10A, and RLB which is data input in series with PLL <1>. <1> goes through the parallelization process through the inverter latch of the three stages as described in Figure 10b. That is, RLB <6>, which is serial input data, is latched in parallel on the falling edge of the PLL <6> signal synchronized to the external clock, and RLB <, which is serial input data on the falling edge of the PLL <1> signal synchronized to the external clock. 1> to latch and parallelize.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Data parallelizing apparatus and method having an internal power generation circuit according to the present invention has the effect that can operate at low voltage and low power by minimizing the current loss by reducing the external power supply to generate an independent internal power supply.

In addition, the present invention, in particular, has the effect of operating at low voltage and low power by minimizing current loss during power down.

In addition, the present invention has the effect of ensuring a stable operation irrespective of external voltage fluctuations by separating the internal power generating circuit into a plurality and supplying the internal power independently.

Claims (24)

A semiconductor device which converts input data from serial to parallel or converts from parallel to serial by synchronizing an input signal and input data with an external clock using a clock synchronization circuit. An input processor configured to receive at least one of an external clock, data, a power down mode setting signal, and an internal power level setting signal; A reference voltage generator configured to receive an external power and provide a reference voltage obtained by depressing the external power to a predetermined magnitude; And An internal power generation unit coupled to an output terminal of the input processing unit and an output terminal of the reference voltage generator, respectively, and receiving the reference voltage in response to the power down mode setting signal to generate internal power to be supplied to an internal circuit of the semiconductor device; Semiconductor device having an internal power generation circuit comprising a. The method of claim 1, The reference voltage generator An activation reference voltage generator providing an activation state reference voltage; And Deactivation reference voltage generator providing an inactive state reference voltage A semiconductor device having an internal power generation circuit comprising a. The method of claim 2, The internal power generation unit An activation state internal power generation unit for a peripheral device which receives the activation state reference voltage and supplies an activation state internal power to an internal component circuit except the clock synchronizing circuit among the component circuits of the semiconductor device in an activation state; An activation state internal power generation unit for a clock synchronization circuit which receives the activation state reference voltage and supplies an activation state internal power to the clock synchronization circuit among the circuits of the semiconductor device in an activation state; In an inactive state, an inactive state internal power source for a peripheral device which receives the inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to an internal component circuit except the clock synchronizing circuit among the component circuits of the semiconductor device part; And In an inactive state, an inactive state internal power generator for a clock synchronizing circuit which receives an inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to the clock synchronizing circuit among the circuits of the semiconductor device. A semiconductor device having an internal power generation circuit comprising a. The method of claim 3, In the activation state, the activation state internal power generation unit for the peripheral device, the activation state internal power generation unit for the clock synchronization circuit, the deactivation state internal power generation unit for the peripheral device, and the deactivation state internal power generation unit for the clock synchronization circuit are activated. And a deactivation state internal power generation unit for the peripheral device and a deactivation state internal power generation unit for a clock synchronization circuit in the deactivation state. The method of claim 3, In an active state or in an inactive state, the internal power level output from the internal power generator for the clock synchronization circuit and the internal power level output from the internal power generator for the peripheral device is different from each other. Semiconductor device. The method of claim 3, The internal power generation circuit having an internal power level output from the internal power generation unit for the clock synchronizing circuit is higher than the internal power level output from the internal power generation unit for the peripheral device in the activated state or the inactive state. Semiconductor device. The method of claim 3, When the internal power level setting signal is the first level in the inactive state, the output voltage of the inactive state internal power generation unit for the clock synchronizing circuit is set to a voltage having a predetermined level lower than the external power level, When the internal power level setting signal is the second level in the inactive state, the output voltage of the inactive state internal power generation unit for the clock synchronizing circuit is set to the ground potential level A semiconductor device having an internal power generation circuit, characterized in that. The method of claim 3, The active state internal power generator for the peripheral device First and second PMOS transistors having a source terminal coupled to an external power source, gate terminals coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor having a drain terminal coupled to a drain terminal of the first PMOS transistor and having a gate voltage as a reference voltage in the activation state; A third NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor and forming a current path to ground potential by using a gate input as a gate input for using a power down activation signal as a switch of a current path; A third PMOS transistor having a source terminal coupled to the external power supply and having a power down activation signal as a gate input; A fourth PMOS having a source terminal coupled to the external power source, a gate terminal coupled to the drain terminal of the third PMOS transistor, and the drain terminal being used as an output terminal for outputting the internal power source of an active state internal power generator of the peripheral device; transistor; A fifth PMOS transistor having a source terminal coupled to the external power supply and a gate terminal coupled to a drain terminal of the third PMOS transistor and a drain terminal of the first PMOS transistor; And A drain terminal is coupled to the drain terminal of the second PMOS transistor, a source terminal is coupled to the source terminal of the first NMOS transistor, a gate terminal is coupled to the drain terminals of the fourth and fifth PMOS transistors and is activated for the peripheral device. A second NMOS transistor which feeds back the output internal power of the state internal power generator to serve as a gate input. A semiconductor device having an internal power generation circuit comprising a. The method of claim 3, The inactive state internal power generator for the peripheral device First and second PMOS transistors having a source terminal coupled to an external power source, gate terminals coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor having a drain terminal coupled to a drain terminal of the first PMOS transistor and having the inactive state reference voltage as a gate input; A third NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor and having the inactive state reference voltage as a gate input; A fourth NMOS transistor having a drain terminal coupled to a source terminal of the third NMOS transistor, a source terminal coupled to a ground power supply, and having an internal power supply level setting signal as a gate input when in an inactive state; A third PMOS transistor having a source terminal coupled to the external power supply and a gate terminal coupled to a drain terminal of the first PMOS transistor; A first resistor having one end coupled to a drain terminal of the third PMOS transistor and a second resistor having one end coupled to the other end of the first resistor; A fifth NMOS transistor having a drain terminal coupled to the other end of the second resistor, a source terminal coupled to the ground power supply, and a gate input for using an internal power level setting signal as a switch of a current path in the inactive state; And A drain terminal is coupled to the drain terminal of the second PMOS transistor, a source terminal is coupled to the source terminal of the first NMOS transistor, and is connected to one end of the second resistor to divide the voltage divided by the first and second resistors. Second NMOS transistor fed back to gate input Wherein, the drain terminal of the third PMOS transistor as an output terminal and the internal power supply voltage level of a predetermined magnitude of the output terminal voltage is less than the ground potential level or the external power supply corresponding to the internal power supply level setting signal in the inactive state And a semiconductor device having an internal power generation circuit. The method of claim 3, The active state internal power generation unit for the clock synchronization circuit First and second PMOS transistors having a source terminal coupled to an external power source, gate terminals coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; First and second NMOS transistors having a drain terminal coupled to a drain terminal of the first PMOS transistor and connected in parallel with each other, the activation state reference voltage being a gate input; A fourth NMOS transistor having a drain terminal coupled to the source terminals of the first and second NMOS transistors and forming a current path to ground potential as a gate input for using a power down activation signal as a switch of a current path; A third PMOS transistor having a source terminal coupled to the external power supply and having a power down activation signal as a gate input; A source terminal is coupled with the external power supply, a gate terminal is coupled with a drain terminal of the third and first PMOS transistors, and the drain terminal is used as an output terminal for outputting an internal power supply of an active state internal power generation unit for the clock synchronization circuit. A fourth PMOS transistor; And A drain terminal is coupled to the drain terminal of the second PMOS transistor, a source terminal is coupled to the source terminal of the first and second NMOS transistors, and a gate terminal is coupled to the drain terminal of the fourth PMOS transistor and used for the clock synchronization circuit. The third NMOS transistor which feeds back the internal power of the output of the active state internal power generator to serve as a gate input. A semiconductor device having an internal power generation circuit comprising a. The method of claim 3, The inactive state internal power generator for the clock synchronizing circuit First and second PMOS transistors having a source terminal coupled to an external power source, gate terminals coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor having a drain terminal coupled to a drain terminal of the first PMOS transistor and having the inactive state reference voltage as a gate input; A third NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor and having the inactive state reference voltage as a gate input; A fourth NMOS transistor having a drain terminal coupled to a source terminal of the third NMOS transistor and forming a current path to a ground potential using a gate input to use the internal power level setting signal as a switch of a current path; A third PMOS transistor having a source terminal coupled to the external power supply and a gate terminal coupled to a drain terminal of the first PMOS transistor; A first resistor having one end coupled to a drain terminal of the third PMOS transistor and a second resistor having one end coupled to the other end of the first resistor; A fifth NMOS transistor having a drain terminal coupled to the other end of the second resistor, a source terminal coupled to the ground power supply, and having the internal power level setting signal as a gate input; And A drain terminal is coupled to the drain terminal of the second PMOS transistor and a source terminal is coupled to the source terminal of the first NMOS transistor and coupled to one end of the second resistor to divide the voltage divided by the first and second resistors. Second NMOS transistor fed back to gate input Including a drain terminal of the third PMOS transistor as an output terminal, the output terminal voltage corresponding to the internal power supply level setting signal has a power supply level of a predetermined magnitude less than the ground potential level or the external power supply; A semiconductor device having an internal power generation circuit. The method of claim 3, An inactive state internal power generator for the clock synchronizing circuit and an inactive state internal power generator for the peripheral device First and second PMOS transistors having a source terminal coupled to an external power source, gate terminals coupled to each other, and the gate terminal coupled to a drain terminal of a second PMOS transistor; A first NMOS transistor having a drain terminal coupled to a drain terminal of the first PMOS transistor and having a gate voltage as a reference voltage in the inactive state; A third NMOS transistor having a drain terminal coupled to a source terminal of the first NMOS transistor and having a gate voltage as a reference voltage in the inactive state; A fourth NMOS transistor having a drain terminal coupled to a source terminal of the third NMOS transistor and forming a current path to a ground potential using a gate input to use the internal power level setting signal as a switch of a current path; A third PMOS transistor having a source terminal coupled to the external power supply and a gate terminal coupled to a drain terminal of the first PMOS transistor; A fifth NMOS transistor having a drain terminal coupled to a drain terminal of the third PMOS transistor and having the internal power level setting signal as a gate input; And A fifth NMOS transistor having a drain terminal coupled to the drain terminal of the second PMOS transistor, a source terminal coupled to the source terminal of the first NMOS transistor, and a gate terminal coupled to the drain terminal of the third PMOS transistor Wherein, the drain terminal of the third PMOS transistor as an output terminal and the output terminal voltage corresponding to the internal power level setting signal level has a power supply level of a predetermined magnitude less than the ground potential level or the external power supply; A semiconductor device having an internal power generation circuit, characterized in that. The method of claim 2, The activation reference voltage generator and the deactivation reference voltage generator It is connected between the external power supply and the ground potential to generate an output voltage according to a predetermined resistance ratio or resistance ratio of a transistor, respectively, wherein the output voltage of the activation reference voltage generator is greater than twice the output voltage of the deactivation reference voltage generator. A semiconductor device having an internal power supply circuit. An input processor configured to receive at least one of an external clock, data, a power down mode setting signal, and an internal power level setting signal; A reference voltage generator configured to receive an external power and provide a reference voltage obtained by depressing the external power to a predetermined magnitude; An internal power generator coupled to an output terminal of the input processor and an output terminal of the reference voltage generator, and configured to receive the reference voltage in response to the power down mode setting signal and generate internal power to be supplied to an internal circuit of the semiconductor device; A clock synchronizing circuit including a voltage control oscillator coupled to an output terminal of the internal power generator to generate a predetermined number of clock synchronizing signals having different phases synchronized with an external clock; A data mapping unit coupled to an output terminal of the internal power generation unit to convert the serially input data into a plurality of channels by coding the clock synchronizing signal and converting the data into parallel data; An error correction unit coupled to an output terminal of the internal power generation unit to receive output data of the data mapping unit to correct timing errors between respective parallel data; And An output buffer unit which is supplied with the external power and coupled with an output terminal of the error correction unit to transmit the output data of the error correction unit at high speed Data paralleling device having an internal power generation circuit including a The method of claim 14, The reference voltage generator An activation reference voltage generator providing an activation state reference voltage; And Deactivation reference voltage generator providing an inactive state reference voltage A semiconductor device having an internal power generation circuit comprising a. The method of claim 15, The internal power generation unit An activation state internal power generation unit for a peripheral device which receives the activation state reference voltage and supplies an activation state internal power to an internal component circuit except the clock synchronizing circuit among the component circuits of the semiconductor device in an activation state; An activation state internal power generation unit for a clock synchronization circuit which receives the activation state reference voltage and supplies an activation state internal power to the clock synchronization circuit among the circuits of the semiconductor device in an activation state; In an inactive state, an inactive state internal power source for a peripheral device which receives the inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to an internal component circuit except the clock synchronizing circuit among the component circuits of the semiconductor device part; And In an inactive state, an inactive state internal power generator for a clock synchronizing circuit which receives an inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to the clock synchronizing circuit among the circuits of the semiconductor device. A semiconductor device having an internal power generation circuit comprising a. The method of claim 15, The internal power generation unit An activation state internal power generation unit for a peripheral device that receives the activation state reference voltage and supplies an activation state internal power to an internal component circuit of the semiconductor device except the voltage control oscillator; An activation state internal power generation unit for a clock synchronization circuit which receives the activation state reference voltage and supplies an activation state internal power to the voltage control oscillator among the circuits of the semiconductor device in an activation state; In an inactive state, an inactive state internal power source for a peripheral device that receives the inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to an internal component circuit except the voltage control oscillator among the circuits of the semiconductor device part; And In an inactive state, an inactive state internal power generator for a clock synchronizing circuit which receives an inactive state reference voltage and an internal power level setting signal and supplies an inactive state internal power to the voltage control oscillator among the circuits of the semiconductor device. A semiconductor device having an internal power generation circuit comprising a. The method according to claim 16 or 17, Wherein the internal power level output from the internal power generation unit for the clock synchronizing circuit is higher than the internal power level output from the internal power generation unit for the peripheral device in an activated state or inactive state. Device. The method of claim 14, The predetermined number of clock synchronizing signals A semiconductor device having an internal power generation circuit, characterized by seven clock synchronizing signals. The method of claim 19, The data mapping circuit The output voltage of the internal power generation unit is used as a power source, and a predetermined number of data inputted in series using an inverter latch of two stages by receiving first to third clock synchronization signals is set in parallel with respect to an external clock. A first data mapping unit which latches for a period and converts the data into parallel data; And The output voltage of the internal power generation unit is used as a power source, and a predetermined number of data inputted in series using the inverter latches of three stages by receiving the fourth to sixth clock synchronization signals is set in parallel with respect to the external clock. Second data mapping unit for latching during period and converting into parallel data A semiconductor device having an internal power generation circuit comprising a. The method of claim 20, The first data mapping circuit is A first transfer transistor configured to receive serially input data and pass the serially input data using the first clock synchronizing signal as a control input; A first inverter latch coupled to an output terminal of the first transfer transistor to latch an output of the first transfer transistor; A second transfer transistor configured to pass the output of the first inverter latch using the second and third clock synchronization signals as a control input; And A second inverter latch coupled to an output terminal of the second transfer transistor to latch an output of the second transfer transistor A semiconductor device having an internal power generation circuit comprising a. The method of claim 20, The second data mapping circuit is A third transfer transistor configured to receive serially input data and pass the serially input data by using the fourth clock synchronizing signal as a control input; A third inverter latch coupled to an output terminal of the third transfer transistor to latch an output of the third transfer transistor; A fourth transfer transistor configured to pass an output of the third transfer transistor using an output terminal of the third inverter latch as an input and a fifth and sixth clock synchronizing signal as a control input; A fourth inverter latch coupled to an output terminal of the fourth transfer transistor to latch an output of the fourth transfer transistor; A fifth transfer transistor configured to pass an output of the fourth inverter latch as an input of the output of the fourth inverter latch and a control input of the fourth clock synchronization signal; A fourth inverter latch coupled to an output terminal of the fifth transfer transistor to latch an output voltage of the fifth transfer transistor; And Inverter outputting by inverting output of fourth inverter latch A semiconductor device having an internal power generation circuit comprising a. Receiving at least one of an external clock, data, a power down mode setting signal, and an internal power level setting signal; Generating a reference voltage obtained by depressing an external power supply to a predetermined magnitude; Generating internal power to be supplied to an internal circuit of the semiconductor device in response to the power down mode setting signal using the generated reference voltage; Generating a predetermined number of clock synchronization signals of different phases synchronized with an external clock using the generated internal power supply voltage as a power source; And Latching a predetermined number of serially input data into a parallel state by converting the predetermined number of data into parallel data by using the clock synchronizing signal for one period; Data parallelization method using an internal power supply comprising a. The method of claim 23, wherein Receiving the converted parallel data and correcting a timing error between the parallel data; And Outputting the converted parallel data using an output buffer Data parallelization method using an internal power supply further comprising.