KR20020095166A - Bistable chiral nematic liquid crystal display and method of driving the same - Google Patents

Abstract

The bistable chiral nematic liquid crystal display has a pixel address circuit, which first switch switches the supply voltage to the rest of the pixel address circuit and is controlled by the row address line 10. Device 14 and a second switching device 16 which permits or inhibits the supply voltage from being provided to each part of the liquid crystal material 18 and is controlled by the column select line 20. This pixel layout allows transitions to the H state to be avoided when the material maintains the P or FC states so that black addressing bar artifacts can be avoided.

Description

Bistable chiral nematic liquid crystal display and driving method of such display {BISTABLE CHIRAL NEMATIC LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME}

Cholesteric liquid crystal materials are reflective materials that provide strongly colored binary images. This material is bistable, has a very wide viewing angle and does not require polarisers, color filters or rubbing required by super twisted nematic (STN) type displays. Therefore, this material can provide a low power and low cost display with a high resolution and good quality single color image. This type of display is proposed for hand-held portable devices as well as electronic document viewers such as e-book or newspaper devices.

The cholesteric material has three stable states. The Planar (P) state is the reflective state of the material and is stabilized with a zero applied field. Focal Conic (FC) state is the transmissive scattering state of the material and is also stabilized with a zero applied field. The Homeotropic (H) state is only stabilized above the high threshold voltage, which is approximately 30V, and is also transparent. The black absorbent layer located behind this material means that the H and FC states appear black.

There is also a fourth unstable state that may occur when the material is relaxed from the H state. This state is called the transient planner (P ^* ) state. This state occurs when the high voltage on the substance in the H state decreases sharply, for example for less than 2 ms. The transient planner state relaxes to planner state P in the absence of an applied voltage.

Using this material, a drive structure has been invented for switching the material between the P and FC states which are stabilized at zero applied voltage. The first problem arises because any transition between the P and FC states needs to pass through the H state, which is a high voltage material. Therefore, known passive matrix switching structures require rapid high voltage switching. Conventional drive structures are arranged such that whenever a pixel is addressed, a transition in the material will provoke into the H state. This means that a pixel in the reflective P state will pass through the transparent H state even though the pixel is driven to the reflective P state in the next field period. This causes a visual artifact known as a black addressing bar.

Additional problems with these materials arise from slow response times. For example, to transition the material to the H state, a voltage needs to be applied for at least 20 ms. The material also has a strong temperature dependency.

The bistable nature of a material at zero applied voltage means that the display using this material does not require continuous updating or refreshing. If the display information does not change, the display can be written once and kept in a configuration that carries this information for an extended period of time without any power consumption. This eventually led to the use of cholesteric liquid crystal displays for images that could be slowly updated over a relatively long period of time. However, the problem outlined above, in particular the slow addressing response, has limited the further development of this display technology into wider applications.

US 5 748 277 discloses a passive matrix addressing structure for cholesteric displays which seeks to reduce addressing time. This structure relies on the rapid transition from the H state to the P ^* state. If there is a rapid voltage turn-off, a transition to P ^* (and also a transition to the P state) is achieved, while if there is a slow voltage turn-off, a transition to the FC state occurs. This drive structure provides an address voltage profile with three phases. One of these phases is the “selection phase”, which is a period of only 1 ms, which indicates whether it is a rapid voltage turn-off or a slow voltage turn-off. The other two steps can be performed simultaneously on adjacent rows, so for a significant number of rows, the average row address period will be close to 1 ms. While this address structure improves addressing time, it does not address temperature dependence, rapid high voltage switching or other problems that black addressing desires.

The present invention relates to displays using chiral nematic reflective bistable liquid crystal materials and methods of driving such displays. Such materials are also described as cholesteric. In particular, the present invention relates to an active matrix pixel arrangement and drive structure.

1 shows the optoelectronic response of a bistable reflective cholesteric liquid crystal.

2 shows an active matrix pixel circuit for a cholesteric display in accordance with the present invention.

3 is a timing diagram for the FIG. 2 circuit.

4 shows a second active matrix pixel circuit for a cholesteric display in accordance with the invention allowing an alternating supply voltage.

5 is a timing diagram for the circuit of FIG.

FIG. 6 shows a third active matrix pixel circuit for cholesteric display according to the invention allowing an alternating supply voltage; FIG.

7 is a timing diagram for the circuit of FIG.

8 shows another display in accordance with the present invention;

According to the invention,

A bistable chiral nematic liquid crystal material layer,

An active matrix substrate defining rows and columns of pixel address circuits, each pixel address circuit having an output for applying a signal to each portion of the liquid crystal material;

A display device is provided, wherein each pixel address circuit includes:

A first switching device for switching a supply voltage to the rest of the pixel address circuit, the first switching device being controlled by a row address line;

And a second switching device which permits or inhibits the supply voltage from being provided to each part of the liquid crystal material and is controlled by a column select line.

The switching device of the pixel allows the transition to the H state to be avoided when the material remains in the P or FC state. In particular, if the transition from the P state to the H state is avoided, the black addressing bar artifacts can be avoided. Using a row address line to control the first switching device and a column select line to control the second switching device, the supply voltage can be provided independently to individual pixels. The supply voltage is the voltage required to transfer the cholesteric material to the H state.

The device may further comprise a current discharge path for each portion of the liquid crystal material, thereby allowing the magnitude of the voltage on each portion of the liquid crystal material to be reduced from the supply voltage magnitude. This causes a state transition from the H state to the FC or P state.

Preferably, the discharge path comprises an isolation switch and a current sink, wherein the current flowing through the current sink is controllable to control the rate at which the voltage magnitude is reduced. At this time, the control of the ratio allows the user to select whether to transition to the P ^* state or the FC state. For example, a current sink may include a transistor whose gate is connected to a capacitor, where the voltage across the capacitor is determined by a current mirror circuit, which circuit samples the input current, and the input current measures the desired rate of voltage magnitude reduction. Is selected to provide. The input current may take one of two values, where one value eventually causes a transition to the FC state and the other value eventually causes a transition to the P ^* state.

The second column select line is preferably provided to supply an input current to the pixel. Therefore, sampling of the input current is performed in rows. However, once the input current for one row has been sampled, the liquid crystal material can be discharged while the input current is being sampled by the other row. This means that for a significant number of rows, the row address period will be close to the duration of the control pulse on the row address line or the sampling time required to sample the input current. These are unique pixel drive signals that are not performed simultaneously for different rows. Thus, a high speed drive structure can be implemented.

The apparatus preferably includes a frame store for determining which pixels are supplied with a supply voltage based on the pixel outputs in the previous and current frames.

The present invention also provides a method of addressing a bistable chiral nematic liquid crystal display device, the device comprising an active matrix substrate defining rows and columns of pixel address circuits, each pixel address circuit being provided in each portion of the liquid crystal material. There is provided an addressing method having an output for applying a signal, the method comprising:

Selecting a pixel row to provide each pixel with a sufficient supply voltage to cause the liquid crystal material to reach a homertropic state;

Determining which pixels need to be applied to each part of the liquid crystal material, wherein the pixels were in the reflective planner state in the previous frame and those pixels in the current frame that remained in the reflective planner state needed the supply voltage. Determining, not determined;

Providing a supply voltage to such pixels determined to require a supply voltage;

Providing an input current having one of two values to each pixel on the row;

Sampling the input current;

Causing the magnitude of the voltage on each portion of the liquid crystal material to change at a rate that depends on the sampled input current,

Wherein, for such a pixel supplied with a supply voltage, the first value of the input current eventually causes the liquid crystal material to adopt the reflective planner state P, and the second value of the input current eventually results in the transmissive focal conic (FC) Let the state be adopted.

The method allows the black addressing bar artifacts to be eliminated and avoids high voltage rapid switching. Preferably, the first value of the input current is higher than the second value of the input current, which in turn results in a more rapid rate of voltage change on the liquid crystal material, thereby eventually leading to a transient planner state (P ^* ) from the homertropic state (H). Causes transition to.

Examples of the present invention will now be described in detail with reference to the accompanying drawings.

Definitions of "row" and "column" are somewhat arbitrary in the following detailed description and claims. These terms are only intended to refer to a two-dimensional element arrangement in which groups of elements are aligned in two orthogonal axes. Thus, "row" or "column" may be from side to side of the display, or from top to bottom.

1 shows the optoelectronic response of a bistable reflective cholesteric liquid crystal. The curve shows the reflectivity after applying a given voltage, which is a square wave pulse, starting in either a stable low voltage planar state or a focal conic state. Voltages below V ₁ do not change the state of the material. Voltage pulses between V ₂ and V _{3 cause the} material to switch to the focal conic state, and voltages above V ₄ eventually lead to planar states. To use the material in liquid crystal displays, the material is led to a stable planner or focal conic state through a low applied voltage (<V ₁ ). However, in order to switch between the planar state and the focal conic state, the material must be led to a high voltage state (not shown in FIG. 1) through which the material is permeable. At this time, the condition that causes the high voltage to be removed from the material indicates the manner in which the material is relaxed to a stable low voltage state. If the voltage is abruptly removed, the material passes through the transient planner state before relaxing to a stable planar state. If the high voltage is removed more slowly, the material relaxes to a focal conic low voltage stable state.

Conventional drive structures for cholesteric displays use passive matrix addressing structures, which are possible as a result of the memory effect of liquid crystals. During each field period of the addressing structure, the material passes in a permeable homertropic state. This causes the black addressing bar artifacts described above.

The present invention provides an active matrix addressing structure in which the high voltage supplied to a pixel row can be selectively switched to the liquid crystal material of each pixel on the row. Thus, it is possible to indicate for each pixel whether each pixel passes in the homertropic state. For pixels that are in the reflective planner state and will remain in the reflective planner state, preventing the homertropic state eliminates the problem of the black addressing bar.

2 illustrates a first active matrix pixel design for the present invention. Each pixel is addressed by a first row conductor 10 (“sub-row 0”), which first row conductor 10 addresses a row of pixels, and a high supply voltage V _prep is applied to the liquid crystal material. Used to ensure supply. This voltage V _prep is provided on the supply voltage line 12. The row conductor 10 is connected to the gate of the first transistor 14, which permits or inhibits the supply voltage from being provided to the rest of the pixel. When a pixel row is addressed by the row conductor 10, all of these transistors 14 on the row are turned on so that the supply voltage reaches the rest of the pixel for each pixel on this row. The second transistor 16 permits or prohibits the supply voltage from being provided to the cholesteric liquid crystal cell 18, the gate of which is connected to the column select line 20 (“sub-column 0”). Is provided by The row address line 10 and the column select line 20 together allow the supply voltage to be provided to or isolated from the individual pixels in each row. This allows these pixels to be isolated from the supply voltage so that certain pixels do not enter the homertropic state. In particular, if the pixel is induced from the reflective state in one field period to the reflective state in the next field period, the second transistor 16 is turned off by the signal on the column select line 20. Of course, this requires field storage so that the current state of the pixels can be stored.

As described above, for these pixels where the cholesteric material is induced in the homertropic state, the discharge condition from the homertropic state determines whether the pixel returns to the transmissive focal conic state or the reflective planner state. Indicates. In order for the discharge condition to be controlled, a current mirror circuit 22 is provided that samples the input current on the second column select line 24 (“sub-column 1”). To perform this sampling operation, the second row conductor 26 (“sub-row 1”) is provided with a signal that causes the current mirror 22 to perform the sampling operation. The signal on the second row conductor 26 is conducted by the two transistors 28, 30 in the current mirror circuit 22 so that a current flowing along the second column select line 24 causes these two transistors 28, 30. Let it pass In this step, the elements of the current mirror circuit 22 are insulated from the rest of the pixel, and the current being sampled flows through the sampling transistor 32 to ground 34 through this. When the steady state condition is reached, the appropriate gate voltage of the sampling transistor 32 is stored on the capacitor 36. Furthermore, in this steady state no current will flow through the capacitor 36. If the gate current of the sampling transistor 32 is ignored, all current provided along the second column select line 24 will pass through the sampling transistor 32.

At the end of the sampling operation, transistors 28 and 30 are turned off because the pulse on second row conductor 26 is terminated. At this time, the sampling transistor 32 is insulated, but corresponds to a drain-source current, such as a current sample from the second column select line 24, and has a gate-source voltage determined by the capacitor 36.

In order to initiate the discharge of the supply voltage from the liquid crystal material 18, a pulse is generated in the third row conductor 38 ("sub-row 2") to switch on the discharge transistor 40, and this discharge transistor ( 40 causes current to flow through the sampling transistor 32 to ground 34, thereby discharging the liquid crystal material 18. The rate at which current flows out of the liquid crystal material is determined by the current flowing through the sampling transistor 32 and, therefore, by the current provided along the second column select line 24. Thus, the column select line 24 represents the rate at which the voltage across the liquid crystal material decreases, thereby determining the final state of the pixel.

The timing diagram of FIG. 3 illustrates this process. As described above, the pulse 50 on the row conductor 10 causes the supply voltage to be supplied to the rest of the pixel. The level on the first column select line 20 ("sub-column 0") at this time indicates whether the supply voltage passes through the liquid crystal material 18. Thus, the signal on the first column select line 20 fluctuates between two values, where one value is maintained for at least a time interval corresponding to the duration of the pulse 50. At the end of pulse 50, transistor 16 is turned off to insulate liquid crystal material 18. In this manner, the voltage, is maintained between the material for a period of time (t _1), a discharge transistor (40) during this time period (t ₁₎ is in a closed state. This time t ₁ is the time when the third row conductor 38 (“sub-row 2”) is low. This is the preparation time for the material to reach the homertropic state, which will typically be between 20 ms and 60 ms. Towards the end of the preparation time t ₁ , the current mirror 22 will sample the input current on the second column select line 24. This is achieved by the pulse 52 applied to the second row conductor 26 (“sub-row 1”). During this time the level on the second column select line 24 is sampled by the current mirror 22. The signal on the second column select line 24 varies between the two values and maintains one of these two values for a time interval corresponding to the timing of the pulses 52.

3 shows a timing diagram for two consecutive rows of an arrangement. Assuming that the pulses 50 and 52 have the same width, the timing for adjacent rows is only replaced by the width of these pulses (plus an additional guard band that allows switching of the signal), as in the illustrated example. This is because the preparation time t ₁ may overlap between adjacent pixels. Furthermore, row pulse 50 is applied to one row of pixels, while at the same time the current signal on the second column select line can be sampled by pulses 52 in another row of pixels.

If the pulses 50 and 52 have different widths, the time shift between adjacent rows will generally correspond to the longest duration of these two pulses. This means that a rapid addressing structure can be implemented.

The duration of the pulse 50 is represented by how quickly the liquid crystal can discharge to the supply voltage V _prep . The duration of the pulse 52 is represented by the time required to set the current mirror to the equilibrium state of the current mirror operation.

The amount of high voltage switching required on a row is significantly reduced when compared to passive matrix structures. Transistor 14 requires the highest voltage switching performance controlled by first row conductor 10.

The pixel design of the present invention allows temperature variations to be compensated very easily. For example, the supply voltage V _prep can be modified as a function of temperature if this is necessary to ensure a reliable transition to the homertropic state. Similarly, the current provided on the second column select line 24 may vary as a function of temperature to ensure that the two current levels to be sampled can control the relaxation of the material in the desired manner.

The circuit of FIG. 2 shows the supply voltage V _prep as a constant voltage supplied to all pixels of the display. However, most liquid crystal materials require that the electric field between them be inverted at regular intervals, resulting in a time averaged voltage of zero. This prevents degradation of the liquid crystal material and is necessary to prevent image retention. 4 shows a second pixel circuit that causes the supply voltage to be alternating. These components in the pixel layout of FIG. 4 that correspond to the components of FIG. 2 and have the same function are given the same reference numerals, and descriptions of these components will not be repeated.

In the pixel layout of FIG. 4, transistors 14 and 16 again determine whether a supply voltage is provided to liquid crystal material 18. However, in this circuit, the supply voltage can have a positive value or a negative value. As a result, the current mirror circuit 22 should be able to draw current from the liquid crystal material 18 or supply current to the liquid crystal material depending on the polarity of the supply voltage. For this purpose, two discharge switches 40a and 40b are provided.

In the sampling circuit 22, the current flowing through the two sampling switches 28, 30 has two possible paths to ground 34. One of these paths is through transistors 60 and 62 and the other is through switch 64.

If the supply voltage is positive, the second discharge switch 40b should be off, transistor 64 is off and transistor 62 is turned on. At this time, although an additional transistor 62 is connected between the sampling circuit 22 and the ground line 34, the circuit is the same as that of FIG. Again, the voltage stored between the capacitors 36 corresponds to the gate-source voltage of the transistor 60 when a source-drain current such as the sampled current from the second column select line 24 flows. The discharge path for the liquid crystal material is through the first discharge transistor 40a and through both transistors 60 and 62 to ground 34.

If the supply voltage is negative, the first discharge transistor 40a is turned off, the transistor 62 is turned off, and the transistor 64 is turned on. The sampling operation of the current mirror circuit 22 is the same, so that the voltage corresponding to a given source-drain current of the transistor 60 corresponding to the sampled current is again stored on the capacitor 36. However, the current flowing through the transistor 60 is not discharged from the liquid crystal material 18 but is the current supplied to the liquid crystal 18. Thus, during the discharge period, the current path is from the ground 34 to the liquid crystal material through the switch 64, the switch 60, the second discharge switch 40b. Thus, the circuit operates in the same manner as the circuit of Fig. 2, but operates at a negative voltage.

FIG. 5 shows a timing diagram similar to the timing diagram shown in FIG. 3, wherein the supply voltage changes every field period.

When the voltage supply is positive, the timing diagram corresponds to FIG. 3, where the second discharge transistor 40b is turned off by the sub-row 1 and the transistor 62 is turned by the sub-row 3. On, transistor 64 is turned off by sub-row 4.

When the voltage supply is negative, the waveform of the row is the same during the preparation period t ₁ . Thus, current sampling using pulses 52 occurs again, in which transistor 64 is turned off, transistor 62 is turned on, and discharge switches 40a and 40b are both turned off. Once current sampling occurs, at the end of pulse 52, second discharge switch 40b is turned on by sub-row 1, in which case transistor 64 is turned on by sub-row 4, Transistor 62 is turned off by sub-row 3.

As shown above, the number of row conductors is increased from three to six to enable switching of the sampling current from the liquid crystal material to ground or otherwise from ground to liquid crystal material. However, it is possible to reduce the number of row conductors required to implement this function, and FIG. 6 shows a pixel circuit in which the number of row conductors is reduced.

From the timing diagram of FIG. 5, it is clear that sub-rows 1 and 4 carry the same signal in both positive and negative supply voltage states. Single row conductors can therefore provide such a signal. Thus, in the circuit of FIG. 6, the second discharge transistor 40b and the transistor 64 are supplied by a single row line, sub-row 1. Additional savings for one row conductor are achieved by connecting transistor 62 and first discharge switch 40a to a common control line, sub-row 2. This ensures that the transistor 62 is turned on if necessary during the discharge state through the first discharge switch 40a. However, during the sampling state, transistor 62 will no longer provide the necessary connection to ground. Thus, an additional transistor 70 is inserted, which provides the necessary path to ground 34 during the sampling phase. This additional transistor 70 is controlled by a row conductor (sub-row 3) that provides a current sampling pulse 52.

FIG. 7 shows a timing diagram for two states of the circuit of FIG. 6.

8 shows a liquid crystal display device according to the invention. The device is provided with two glass substrates 80, 82, which face each other to hold a liquid crystal material (not shown) therebetween. The lower substrate 82 is an active plate that defines the pixel layout described above. Each pixel defines a contact pad 84 for the liquid crystal material. Each pixel is addressed by a number of row conductors 86 (only one of them is shown in FIG. 8) and a number of column conductors 88 (only one of them is shown in FIG. 8). The upper substrate 80 includes a common ground potential layer 90 such that individual regions of the liquid crystal material have a defined potential over that region, which is indicated by the potential on the contact pad 84.

The active plate may be manufactured using known techniques, such as using the same process used to form the active plate of a conventional active matrix liquid crystal display, for example. Thus, the necessary transistors and capacitors are formed using thin film technology, and the transistors may be limited to amorphous silicon devices or polycrystalline silicon devices.

The addressing structure of the present invention allows very fast addressing to be achieved because a short sampling period is required to sample the current which subsequently indicates the rate at which the liquid crystal is discharged. Black bar addressing artifacts are eliminated by allowing pixels that do not require updating to be isolated. The need for high voltage rapid switching is reduced, and the addressing structure enables improved temperature stability or easy compensation for temperature variations.

Many modifications will be apparent to those skilled in the art.

As described above, the present invention is used in displays using chiral nematic reflective bistable liquid crystal materials and methods of driving such displays.

Claims (12)

As a display device, A bistable chiral nematic liquid crystal material layer; An active matrix substrate defining rows and columns of pixel address circuits, each pixel address circuit comprising an active matrix substrate having an output for applying a signal to each portion of the liquid crystal material, Here, each pixel address circuit is A first switching device for switching a supply voltage to the remaining portion of said pixel address circuit and controlled by a row address line; And a second switching device which allows or prohibits the supply voltage to be provided to the respective portions of the liquid crystal material and is controlled by a column select line. The display device of claim 1, further comprising a current discharge path for each portion of the liquid crystal material to allow the magnitude of the voltage on each portion of the liquid crystal material to be reduced from the supply voltage magnitude. The display device of claim 2, wherein the discharge path includes an isolation switch and a current sink, wherein the current flowing through the current sink is controllable to control a rate at which the voltage magnitude decreases. 4. The current sink circuit of claim 3, wherein the current sink comprises a transistor having a gate connected to a capacitor, wherein the voltage across the capacitor is determined by a current mirror circuit, the current mirror circuit having a desired rate of reduction of the voltage magnitude. A display device for sampling the input current selected to provide. A display device as claimed in claim 4, wherein a second column select line is provided to supply the input current to the pixel. The display device according to claim 4 or 5, wherein the current mirror circuit samples the input current while the isolation switch insulates the respective portions of the liquid crystal material from the current mirror circuit. 7. The method according to any one of claims 4 to 6, wherein the supply voltage varies between a positive value and a negative value, and the current mirror circuit depends on whether the supply voltage is positive or negative. A display device, which can be configured to provide a voltage across a capacitor. The display apparatus according to claim 1, wherein each switching device comprises a transistor. 9. The apparatus according to any one of claims 1 to 8, comprising a frame store for determining which pixel the supply voltage is to be provided to based on pixel output in previous and current frames. , Display device. A method of addressing a bistable chiral nematic liquid crystal display device comprising an active matrix substrate defining rows and columns of a pixel address circuit, each pixel address circuit having an output for applying a signal to each portion of the liquid crystal material, Selecting a row of pixels to provide each pixel with a supply voltage sufficient to cause the liquid crystal material to reach a homeotropic state; Determining which pixels need to be applied with the supply voltage to each of the portions of the liquid crystal material, which were in a reflecting planar state in the previous frame and maintaining a reflecting planner state in the current frame Determining that a pixel does not require the supply voltage; Providing the supply voltage to such pixels determined to require the supply voltage; Providing an input current having one of two values to each pixel on the row; Sampling the input current; Causing the magnitude of the voltage on each portion of the liquid crystal material to change at a rate that depends on the sampled input current, wherein for such a pixel to which the supply voltage is supplied, the first value of the input current ultimately results in the liquid crystal Causing the material to adopt a reflective planner state, the second value of the input current eventually causing the liquid crystal material to adopt a transmissive focal conic state, Addressing method. 11. The method of claim 10, wherein the first value of the input current is higher than the second value of the input current, which in turn causes a voltage change on the liquid crystal material to occur at a more rapid rate, thereby eventually causing the homertropic state. Addressing method that causes a transition from a transient planar state to a transient planar state. The addressing method according to claim 10 or 11, wherein the supply voltage is a positive value for one frame and a negative value for another frame.