KR20020092404A - Semiconductor device and method of manufacturing thereof - Google Patents

Abstract

In the method for manufacturing a semiconductor device, an etching stop insulating film 18 is formed in the first region 2 to cover at least the side surface of the wiring 16 and in the second region 3 to cover the first conductive plug 15b. Subsequently, insulating films 20 and 28 are formed on the etch stop insulating film 18 and the wiring 16, and a part of the insulating films 20 and 28 are etched until the etch stop insulating film 18 is exposed, and the first conductive plug is etched. A hole 28b is formed over the 15b, and the etching stop insulating film 18 is selectively etched through the hole 28b to expose the top surface of the first plug 15b, and then into the hole 28b. A process of forming the conductive plug 31a of the second stage is included.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF}

Recently, in the trend that DRAM miniaturization is progressing, there is a tendency that the capacitor area is narrowed and the capacitor capacity becomes small. Therefore, in order to increase the capacitor capacity, raising the height of the capacitor is performed.

However, when a capacitor is formed three-dimensionally on a silicon substrate like a stack cell, a contact formed in an interlayer insulating film is formed by connecting upper wiring to a gate electrode and a source / drain region formed in a peripheral circuit portion. The height of the hall rises significantly.

And as contact hole becomes high, it becomes difficult to make fine processing by dry etching, or the coverage of the conductive film formed in a contact hole becomes bad, and there exists a possibility that a contact resistance may rise.

Therefore, in recent years, the solution has been aimed at adopting a laminated structure of two-stage contacts, which are formed as upper contacts and lower contacts, without forming one contact with upper and lower conductive patterns.

Next, a contact structure in a conventional DRAM will be described based on FIGS. 1A, 1B, and 2.

FIG. 1A shows the state after the bit line is formed on the interlayer insulating film covering the MOS transistor of the memory cell portion.

In FIG. 1A, a plurality of gate electrodes 106 and 107 are respectively formed in the active region surrounded by the element isolation insulating film 104 among the memory cell portion 102 and the peripheral circuit portion 103 of the silicon substrate 101. It is formed on the silicon substrate 101 through the gate oxide films 105a and 105b. On the gate electrodes 106 and 107, a protective insulating film 108 made of a silicon nitride film is formed.

Impurity diffusion layers 106a and 106b are formed in the silicon substrate 101 on both sides of the gate electrode 106 of the memory cell unit 102. Then, the MOSFET is constituted by the impurity diffusion layers 106a and 106b, the gate electrode 106 and the like.

In the memory cell unit 102, as shown in the plan view of FIG. 3, a plurality of gate electrodes 106 are formed on one active region 110 surrounded by the device isolation insulating film 104, and a plurality of gate electrodes is formed. The impurity diffusion layers 106a and 106b are formed between the 106th portions. In addition, the gate electrode 106 constitutes a part of the word line.

3 shows a bit line contact position and a storage contact position in one memory cell unit 102. 1 (a) has shown the cross section seen from the I-I line | wire of FIG.

On the other hand, in the peripheral circuit section 103, sidewalls 107s made of, for example, silicon nitride are formed on the side surface of the gate electrode 107, and in the silicon substrate 101 on both sides of the gate electrode 107, Impurity diffusion layers 107a and 107b having an LDD structure are formed. MOSFETs are formed by the gate electrode 107, impurity diffusion layers 107a, 107b, and the like.

In addition, sidewalls 106s made of, for example, silicon nitride are formed on the side surfaces of the gate electrodes 106 of the memory cell unit 102.

The MOSFET and silicon substrate 101 having the above configuration are covered with the first interlayer insulating film 109 made of BPSG. In the memory cell unit 102, lower contact holes 109a and 109b are formed at positions sandwiched by the gate electrode 106 of the first interlayer insulating layer 109.

Their lower contact holes 109a and 109b are self-aligned contacts which are self-alignedly positioned between the gate electrodes 106.

In the lower contact holes 109a and 109b, lower plugs 110a and 110b made of doped silicon are formed.

On the lower plugs 110a and 110b and the first interlayer insulating film 109, a second interlayer insulating film 111 made of BPSG is formed.

An upper contact hole 111a is formed on the lower plug 110a for bit line contact in the second interlayer insulating layer 111 of the memory cell unit 102. In the first and second interlayer insulating films 109 and 111 of the peripheral circuit portion 103, lower contact holes 111b and 111c having depths reaching the impurity diffusion layers 107a and 107b are formed.

In the upper contact hole 111a for the bit line of the memory cell unit 102, an upper plug 112a made of a metal film of a multi-layer structure is formed. In the lower contact holes 111b and 111c of the peripheral circuit portion 103, lower plugs 112b and 112c made of a metal film of a multilayer structure are formed.

In the memory cell portion 102, a bit line 113 connected to the upper plug 112a is formed on the second interlayer insulating film 111. The upper surface of the bit line 113 is covered with the silicon nitride film 115, and a side wall 116 made of silicon nitride is formed on the side thereof.

Subsequently, as shown in FIG. 1B, the memory cell unit 102 forms a process for forming an upper plug for storage contact.

In FIG. 1B, a third interlayer insulating film 117 made of BPSG or the like is formed on the bit line 113 and the second interlayer insulating film 111. In the third interlayer insulating layer 117 of the memory cell unit 102, an upper contact hole 117b connected to the lower plug 110b for storage contact is formed, and the upper contact hole 117b is formed of doped silicon. An upper plug 118 is formed.

In addition, the cross section seen from the III-III line | wire of (b) of FIG. 1, and the II-II line | wire of FIG. 3 becomes as shown in FIG.

After that, as shown in FIG. 2, a capacitor 120 is formed on the third interlayer insulating film 117 in the memory cell unit 102, and a fourth interlayer insulating film 121 covering the capacitor 120 is subsequently formed. It is formed on the interlayer insulating film 117. In the third and fourth interlayer insulating films 117 and 121 in the peripheral circuit section 103, upper plugs 122b and 122c connected to the lower plugs 112b and 112c are formed.

In the peripheral circuit section 103, the lower plugs 112b and 112c and the upper plugs 122b and 122c are each composed of a metal film having a three-layer structure made of titanium (Ti), titanium nitride (TiN) and tungsten (W). . Titanium is formed to lower the contact resistance of the metal film. In addition, titanium nitride is formed as a barrier metal for preventing the increase in resistance caused by the reaction of tungsten and titanium.

The capacitor is formed by the following process.

First, a silicon nitride film 119 is formed on the third interlayer insulating film 117, and a thick BPSG film (not shown) is formed on the silicon nitride film 119, and then the BPSG film and nitride of the memory cell portion 102 are nitrided. The silicon film 119 is patterned, and a capacitor-shaped opening is formed over the upper plug 118 of the memory cell portion 102 and the periphery thereof. Then, after the silicon film is formed along the upper surface of the BPSG film and the inner surface of the opening, the silicon film on the BPSG film is removed by chemical mechanical polishing (CMP). When the BPSG film is removed by hydrofluoric acid, a cylindrical silicon film remains on the third interlayer insulating film 117, and the silicon film is used as the storage electrode 120a of the capacitor 120. In addition, when removing the BPSG film, the silicon nitride film 119 functions as an etching stopper.

The dielectric film 120b is formed on the surface of the storage electrode 120a, and the cell plate electrode 120c is formed on the dielectric film 120b.

The cell plate electrode 120c, the dielectric film 120b, and the silicon nitride film 119 are patterned and removed from the peripheral circuit portion 103.

After the capacitor 120 is formed, the fourth interlayer insulating layer 121 is formed.

In the peripheral circuit portion 103, the third and fourth interlayer insulating films 117 and 121 are patterned, and upper contact holes 121b and 121c are formed on the lower plugs 112b and 112c. Subsequently, upper plugs 122b and 122c made of a metal film having a multilayer structure such as lower plugs 112b and 112c are formed in the upper contact holes 121b and 121c.

Upper wirings 123b and 123c formed on the fourth interlayer insulating film 121 of the peripheral circuit portion 103 are connected to the impurity diffusion layers 107a and 107b through the upper plugs 122b and 122c and the lower plugs 112b and 112c. do.

However, as described above, in the peripheral circuit portion 103 of the semiconductor device, the upper wirings 123b and 123c and the impurity diffusion layers 107a, through the upper plugs 122b and 122c and the lower plugs 112b and 112c stacked in two stages. 107b is electrically connected, but if position shift occurs in the upper contact holes 121b and 121c, the upper plugs 122b and 122c are the lower plugs 112b and 112c, as shown in FIG. There is a risk of falling below the top of the.

The reason why the upper contact holes 121b and 121c are formed deeper than the upper surfaces of the lower plugs 112b and 112c is that when the upper contact holes 121b and 121c are formed, the third and fourth interlayer insulating films 117, This is because over etching is performed to ensure that the film thickness of 121) is opened without problems.

A portion A in FIG. 5 shows a state where a part of the upper contact hole 121c protrudes from the lower plug 112c and reaches the vicinity of the gate electrode 107. In such a state, the breakdown voltage between the lower plug 112c and the gate electrode 107 may be lowered. In addition, when the gate electrode 107 has a salicide structure and the protective insulating film 108 does not exist thereon, the lower plug 112c and the gate electrode 107 may be shorted.

A portion B in FIG. 5 shows a case where a part of the upper contact hole 121b protrudes from the lower plug 112b to reach the element isolation insulating film 104. The edge of the device isolation insulating film 104 is etched at the time of forming the upper contact hole 121b, so that the silicon substrate 101 may be exposed around the impurity diffusion layer 107a. When the upper plug 122b is connected to the impurity diffusion layer 107a and the surrounding silicon substrate 101, the junction leak is increased.

In addition, the part C of FIG. 5 has shown the upper surface of the lower plug 112b, and its peripheral part when a part of upper contact hole 121b protrudes from the lower plug 112b. The upper contact hole 121b on the side of the lower plug 112b has a high aspect ratio, and the coverage of the metal film formed therein becomes poor. As a result, there is a possibility that the titanium nitride originally formed thinner becomes locally thinner, and tungsten and titanium react at the place, thereby increasing the contact resistance.

On the other hand, as shown in FIG. 2, the upper contact hole 117b under the capacitor 120 has the fourth interlayer insulating film 121 and the second interlayer insulating film 111 with respect to the contact holes 121b and 121c of the peripheral circuit portion 103. As shallow as the difference in film thickness. In general, the fourth interlayer insulating layer 121 is formed to be considerably thicker than the second interlayer insulating layer 111. Therefore, the over etching amount for ensuring the difference in film thickness when forming the upper contact hole 117b under the capacitor 120 is over when forming the upper contact holes 121b and 121c of the peripheral circuit portion 103. Since it is smaller than the etching amount, even if the upper contact hole 117b is displaced from the upper surface of the lower plug 110b due to its position shift, it is unlikely to be a fatal problem.

Disclosure of the Invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a structure capable of forming a hole in an upper side where a plug is embedded, to a desired depth without increasing the process, and a manufacturing method thereof.

According to the present invention, in the first region, at least the side surface of the wiring on the first insulating film is covered with the second insulating film, and in the second region, the upper surface of the first conductive plug formed in the first insulating film and its periphery are covered with the second insulating film. Next, after forming a third insulating film made of a material different from the second insulating film on the second insulating film, the first insulating film is selectively etched by selectively etching a part of the third insulating film in the second region using the second insulating film as an etching stopper. A hole is formed on the conductive plug, and the second insulating film is selectively etched through the hole to expose the top surface of the first conductive plug, and then the second conductive plug is formed in the hole.

Thereby, even if overetching is carried out when forming a hole in a 3rd insulating film, the lower 1st insulating film is not etched. Therefore, the conductive plug of the second stage does not fall much lower than the conductive plug of the first stage. In addition, since the insulating film formed on the side of the wiring in the first region is used as the etching stop film in the second region, the increase in the number of steps can be minimized without adversely affecting the characteristics of the transistor formed in the semiconductor substrate. Can be.

The first region is, for example, a region where memory cells are formed, and the second region, for example, is a region where peripheral circuits are formed.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a structure in which an upper conductive layer and a lower conductive layer are connected through a plurality of stage contact plugs.

1A and 1B are cross-sectional views 1 illustrating an example of a manufacturing process of a conventional semiconductor device;

2 is a cross-sectional view 2 illustrating an example of a manufacturing process of a conventional semiconductor device;

3 is a plan view showing the arrangement of contact holes in the memory cell portion of the semiconductor device;

4 is a sectional view seen from line III-III of FIG. 1 (b) and line II-II of FIG. 3;

5 is a cross-sectional view showing a problem of a manufacturing process of a conventional semiconductor device;

6 (a) to 6 (c) are cross-sectional views 1 illustrating a process for manufacturing a semiconductor device according to the first embodiment of the present invention;

7 (a) and 7 (b) are cross-sectional views (2) showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

8A and 8B are cross-sectional views 3 illustrating a process for manufacturing a semiconductor device according to the first embodiment of the present invention;

9 is a cross-sectional view 4 showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention;

10 is a cross-sectional view 5 illustrating the process of manufacturing the semiconductor device according to the first embodiment of the present invention;

11 is a sectional view 6 showing a process for manufacturing a semiconductor device according to the first embodiment of the present invention;

12 is a cross-sectional view 7 showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 13A is a cross-sectional view taken along line V-V shown in FIG. 8B;

FIG. 13B is a sectional view taken along the line VI-VI shown in FIG. 12;

Fig. 14 is a plan view showing the arrangement relationship between the gate electrode, the contact portion, and the bit line of the memory cell portion of the semiconductor device of the first embodiment of the present invention;

15 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

16 is a sectional view taken along line VII-VII of the semiconductor device shown in FIG. 15;

17 is a sectional view of a semiconductor device according to Embodiment 3 of the present invention;

18 is a cross sectional view of a semiconductor device according to the fourth embodiment of the present invention;

19 is a cross-sectional view of another semiconductor device in accordance with the fifth embodiment of the present invention;

20 is a cross sectional view of a semiconductor device according to the sixth embodiment of the present invention; And

21 (a) to 21 (c) are cross-sectional views illustrating the process of manufacturing the semiconductor device according to the seventh embodiment of the present invention.

EMBODIMENT OF THE INVENTION Below, the Example of this invention is described based on drawing.

(First embodiment)

6-12 is sectional drawing which shows the manufacturing process of the semiconductor device which shows 1st Example of this invention.

First, the process until it becomes the structure shown to Fig.6 (a) is demonstrated.

In the n-type silicon (semiconductor) substrate 1, at least a memory cell portion 2 and a peripheral circuit portion 3 exist, and in the silicon substrate 1, a device isolation insulating film 4 having a hollow trench isolation (STI) structure ) Is formed. Instead of STI, a LOCOS or other device isolation structure may be employed.

After the device isolation insulating film 4 is formed, p-type impurity ions are implanted into predetermined active regions in the memory cell portion 2 and the peripheral circuit portion 3 to form the p wells 1a and 1b. Although the structure in which the p well 1b is formed in the peripheral circuit part 3 of FIG. 6A is shown, the n type active region (not shown) which does not inject the p type impurity also exists.

In the peripheral circuit section 3, a CMOS is formed. In other words, an n-channel MOSFET is formed in the p well 1b of the peripheral circuit section 3 according to a process described later, and a p-channel MOSFET (not shown) is formed in the n-type active region (not shown). do.

Subsequently, thermal oxidation of the surface of the silicon substrate 1 of the memory cell portion 2 and the peripheral circuit portion 3 forms the gate oxide films 5a and 5b, respectively.

Further, after forming a conductive film, for example, a two-layered conductive film of doped silicon and silicide on the gate oxide films 5a and 5b, the first protective insulating film 8 made of silicon nitride is formed on the conductive film, for example. It is formed to a thickness of 150nm.

Thereafter, the first protective insulating film 8 and the conductive film are patterned into a gate electrode shape by a photolithography method using a resist.

As a result, in the memory cell portion 2, a plurality of gate electrodes 6 constituted by a conductive film also serve as word lines, and in the peripheral circuit portion 3, a plurality of gate electrodes 7 constituted by a conductive film are formed. In the memory cell portion 2, a plurality of gate electrodes 6 are arranged in parallel on one p well 1a surrounded by the element isolation insulating film 4 through the gate insulating film 5a.

Next, by using a resist mask (not shown) in which the memory cell portion 2 is opened, n-type impurities are selectively implanted into the memory cell portion 2 of the silicon substrate 1 so that both sides of the gate electrode 6 are formed. N-type impurity diffusion layers 6a and 6b are formed in the film. In the memory cell portion 2, a MOSFET is formed by the gate electrode 6, the n-type impurity diffusion layers 6a and 6b, and the like. Subsequently, by using a resist mask (not shown) in which the peripheral circuit portion 3 is opened, the impurity ions are selectively implanted into the peripheral circuit portion 3 of the silicon substrate 1 to impurity on both sides of the gate electrode 7. Low concentration portions of the diffusion layers 7a and 7b are formed.

After removing the resist mask, the surface of the impurity diffusion layers 6a, 6b, 7a, and 7b is oxidized in a dry oxidation atmosphere at 800 ° C., for example, by thermal oxidation to form an oxide film (not shown) to a thickness of several nm. .

Subsequently, a silicon nitride film is formed to a thickness of 20 to 100 nm on the gate electrodes 6 and 7 and on the side surfaces and the silicon substrate 1 by chemical vapor deposition (CVD) using silane and ammonia. Thereafter, the silicon nitride film is anisotropically etched and left as sidewalls 6s and 7s on the side surfaces of the gate electrodes 6 and 7.

Next, while covering the memory cell portion 2 with a photoresist (not shown), using the gate electrode 7 and the sidewall 7s of the peripheral circuit portion 3 as a mask, the silicon substrate of the peripheral circuit portion 3 ( Impurities are ion implanted into 1). As a result, in the peripheral circuit portion 3, high concentration portions of the impurity diffusion layers 7a and 7b on both sides of the gate electrode 7 are formed, and these impurity diffusion layers 7a and 7b have an LDD structure. In the peripheral circuit portion 3, the MOSFET is constituted by the impurity diffusion layers 7a and 7b, the gate electrode 7 and the like.

Next, on the gate electrodes 6, 7, sidewalls 6s, 7s, impurity diffusion layers 6a, 6b, 7a, 7b, and element isolation insulating film 4, as the first interlayer insulating film 9, BPSG (boro -phospho silicate glass) film is formed to a thickness of, for example, 1000 nm by CVD. The first interlayer insulating film 9 is heated and reflowed and polished by a chemical mechanical polishing (CMP) method to planarize its upper surface. Polishing is performed until the thickness of the first interlayer insulating film 9 is about 500 nm from the surface of the silicon substrate 1.

Here, an oxide film (HDP or the like) is formed as the first interlayer insulating film 9 by the plasma CVD method for the purpose of avoiding deterioration of the MOSFET characteristics due to the heating reflow, and then the upper surface thereof by the CMP method. You may grind and planarize.

Subsequently, in the memory cell portion 2, lower contact holes 10a and 10b are formed by the photolithography method at positions sandwiched by the gate electrode 6 in the first interlayer insulating film 9. Their lower contact holes 10a and 10b are self-aligned contacts which are self-alignedly positioned by side walls 6s between the gate electrodes 6.

Subsequently, an amorphous silicon film doped with phosphorus is formed in the lower contact holes 10a and 10b and on the first interlayer insulating film 9, and then the amorphous silicon film is formed on the top surface of the first interlayer insulating film 9 by the CMP method. Remove from As a result, the amorphous silicon film remaining in the lower contact holes 10a and 10b is used as the lower contact plugs 11a and 11b.

In addition, of the three lower contact plugs 11a and 11b formed on one active region surrounded by the element isolation insulating film 4, the center lower contact plug 11a is used as a bit line contact, and the remaining lower contact plugs ( 11b) is used as a storage contact.

Next, the process until it will be in the state as shown to Fig.6 (b) is demonstrated.

First, on the lower contact plugs 11a and 11b and the first interlayer insulating film 9, a second interlayer insulating film 12 made of BPSG, plasma oxide film or the like is formed to a thickness of 200 nm. Subsequently, by patterning the second interlayer insulating film 12 of the memory cell portion 2 by the photolithography method, an upper contact hole 13a is formed on the lower contact plug 11a for bit line contact. In addition, the first and second interlayer insulating films 9 and 12 of the peripheral circuit portion 3 are patterned by photolithography to form lower contact holes 13b and 13c on the impurity diffusion layers 7a and 7b.

Here, the upper contact hole 13a of the memory cell portion 2 and the lower contact holes 13b and 13c of the peripheral circuit portion 3 may be formed at the same time, but the upper contact hole 13a for the bit line contact is relatively shallow. Therefore, it is necessary to pay close attention to the position shift with the lower contact plug 11a below it.

Next, the process until it becomes a structure as shown in FIG.6 (c) is demonstrated.

First, a titanium (Ti) film 14a having a film thickness of 50 nm and a film thickness of 50 nm by the CVD method on the inside of the upper contact hole 13a, the lower contact holes 13b and 13c, and the second interlayer insulating film 12. A titanium nitride (TiN) film 14b and a tungsten (W) film 14c having a film thickness of 300 nm are sequentially formed.

Then, the Ti film 14a, the TiN film 14b, and the W film 14c are polished by the CMP method to remove these films from the upper surface of the second interlayer insulating film 12. As a result, the metal films 14a to 14c remaining in the upper contact hole 13a in the memory cell unit 2 become the upper contact plug 15a for bit line contact, and the lower contact hole (in the peripheral circuit section 3). The metal films 14a to 14c remaining in the 13b and 13c are the lower contact plugs 15b and 15c.

Here, the titanium film 14a is provided to obtain good electrical contact with the lower contact plug 11a and the impurity diffusion layers 7a and 7b formed thereunder, and the titanium nitride film 14b is a tungsten film 14c. ) And a titanium film 14a are provided as a barrier layer for suppressing the reaction.

Next, the process until it becomes a structure as shown to Fig.7 (a) is demonstrated.

First, a titanium film 16a having a thickness of 50 nm, a titanium nitride film 16b having a thickness of 50 nm, and a tungsten film 16c having a thickness of 100 nm are placed on the contact plugs 15a to 15c and the second interlayer insulating film 12. The second protective insulating films 17 each formed by CVD and made of silicon nitride having a thickness of 100 nm on the tungsten film 16c are formed by the CVD method. Here, although the titanium film 16a, the titanium nitride film 16b, and the tungsten film 16c are formed by CVD method, since the base is flat, it can also be formed using a sputtering method.

Subsequently, the Ti film 16a, the TiN film 16b, the W film 16c, and the second protective insulating film 17 are patterned by the photolithography method to form a bit line in the memory cell portion 2. As a result, the bit line 16 composed of the titanium film 16a, the titanium nitride film 16b, and the tungsten film 16c is impurity through the upper contact plug 15a and the lower contact plug 11a thereunder. It is electrically connected to the diffusion layer 6a.

The second protective insulating film 17 is used to prevent a short between the contact plug for storage contact and the bit line 16 formed later.

In the peripheral circuit section 3, the titanium film 16a, the titanium nitride film 16b, and the tungsten film 16c may be patterned and left as wiring.

Next, the process until it turns to the state shown in FIG.7 (b) is demonstrated.

First, a silicon nitride (etch stop) film 18 having a film thickness of 20 to 100 nm is formed on the entire surface by a reduced pressure (LP) CVD method. As the growth conditions of the silicon nitride film 18, a mixed gas of any one of SiH ₂ Cl ₂ and SiH ₄ and NH ₃ was used, and the growth temperature was set to 600 ° C to 800 ° C, preferably 750 ° C. The pressure of the growth atmosphere is set to 0.1 to 1.0 Torr.

Thereafter, the photoresist 19 is applied onto the silicon nitride film 18, and the photoresist 19 is exposed and developed to remain only in the peripheral circuit portion 3.

Then, the silicon nitride film 18 present in the memory cell portion 2 is anisotropically etched in a substantially vertical direction and left on the side of the bit line 16 as shown in FIG. 18s). At the time of etching, since the silicon nitride film 18 of the peripheral circuit portion 3 is covered by the photoresist 19, the state in which the lower contact plugs 15b and 15c and the second interlayer insulating film 12 are covered is shown. Keeping up.

The silicon nitride film 18 may be left in the entire peripheral circuit portion 3, but in general, since the silicon nitride film causes deterioration of device characteristics such as MOSFETs, the silicon nitride film 18 may be disposed at a location where the upper contact hole formed in a later step comes down. For example, the position side may leave a margin in the minimum range from the expected size. For example, the silicon nitride film 18 may be left over and around the lower contact plugs 15b and 15c.

The photoresist 19 of the peripheral circuit portion 3 is removed after the silicon nitride film 18 is patterned.

Next, the process until forming the structure shown to FIG. 8 (b) is demonstrated.

First, as the third interlayer insulating film 20, a silicon oxide film having a film thickness of 800 nm, for example, is formed on the entire surface by the plasma CVD method. The third interlayer insulating film 20 is made of a material which can be selectively etched with respect to the silicon nitride film 18.

Subsequently, the third interlayer insulating film 20 is polished by the CMP method to smooth the surface thereof. Polishing of the third interlayer insulating film 20 is performed until the thickness remains about 150 nm from the top surface of the second protective insulating film 17 that protects the bit line 16.

Thereafter, in the memory cell portion 2, the second and third interlayer insulating films 12 and 20 are patterned by the photolithography method, thereby forming the upper contact hole 20b on the lower contact plug 11b for storage contact. do.

In this case, the etching rate of the silicon nitride film is set to be slow with respect to the BPSG and silicon oxide films constituting the second and third interlayer insulating films 12 and 20. As a result, the upper contact hole 20b is not formed in the second protective insulating film 17 and the side wall 18s covering the bit line 16 and is not connected to the bit line 16. Accordingly, as shown in FIG. 13A, the upper contact hole 20b for the storage contact is self-aligned. 13A is a cross sectional view taken along the line VV of FIG. 8B.

Thereafter, an amorphous silicon film doped with phosphorus is formed over the third interlayer insulating film 20 and in the upper contact hole 20b. This amorphous silicon film is grown to a film thickness of 300 nm on the third interlayer insulating film 20 by the CVD method. Subsequently, the amorphous silicon film on the third interlayer insulating film 20 is removed by the CMP method. The amorphous silicon remaining in the upper contact hole 20b for the storage contact is left as the upper contact plug 21 for the storage contact.

The upper contact plug 21 is electrically connected to one impurity diffusion layer 6b of the MOSFET through the lower contact plug 11b.

Next, the process until forming the structure shown in FIG. 9 is demonstrated.

First, a silicon nitride film 22 having a film thickness of 50 nm is formed on the third insulating film 20 and the upper contact plug 21 at a growth temperature of 750 ° C. by, for example, a reduced pressure CVD method. The silicon nitride film 22 having a film thickness of 50 nm was formed as one of a film species and a film thickness that do not transmit hydrofluoric acid used in the subsequent steps.

On the silicon nitride film 22, a BPSG film 23 having a film thickness of 1000 nm is formed by the CVD method.

Thereafter, the openings 23a and 23b in the shape of storage (accumulation) electrodes are formed in the BPSG film 23 and the silicon nitride film 22 by patterning using a photolithography method.

An amorphous silicon film doped with phosphorus is formed by CVD along the upper surface of the BPSG film 23 and the inner circumferential surfaces of the openings 23a and 23b. In this case, the film thickness of the amorphous silicon film on the BPSG film 23 is set to 50 nm.

Subsequently, the amorphous silicon film on the BPSG film 23 is selectively removed by the CMP method, and the amorphous silicon film remaining only in the openings 23a and 23b is left as the storage electrode 24. The storage electrode 24 has a cylindrical shape and is connected to the upper contact plug 21 below it.

In addition, in order to prevent the slurry used when polishing the amorphous silicon film from entering the openings 23a and 23b, after forming the amorphous silicon film, the CMP method after embedding the photoresist R into the openings 23a and 23b. You may grind by. In this case, the photoresist R is removed by a normal resist stripping process after polishing the amorphous silicon film.

Next, the process until forming the structure shown in FIG. 10 is demonstrated.

First, the BPSG film 23 is selectively removed by hydrofluoric acid. At this time, the silicon nitride film 22 under the BPSG film 23 has a property and a film thickness that serve to protect the third interlayer insulating film 20 from prolonged hydrofluoric acid treatment. By removing this BPSG film 23, the outer circumferential surface of the storage electrode 24 is exposed.

Subsequently, a silicon nitride film having a thickness of 5 nm is formed on the surface of the storage electrode 24 and the upper surface of the silicon nitride film 22 by the CVD method, and then the surface of the silicon nitride film is oxidized, and the capacitor dielectric film 25 It is used as).

Thereafter, an amorphous silicon film having a thickness of 50 nm phosphorus-doped is formed on the capacitor dielectric film 25 by CVD. Subsequently, the amorphous silicon film is patterned and left on the storage electrode 24 by the lithography process, and this is used as the cell plate electrode 26. In this case, the silicon nitride film 22 is also patterned in the same shape, and the cell plate electrode 26, the dielectric film 25, and the silicon nitride film 22 are removed from the peripheral circuit portion 3.

The capacitors 27a and 27b of the DRAM cell are constituted by the storage electrode 24, the capacitor insulating film 25, and the cell plate electrode 26.

Next, the process until it becomes the structure shown in FIG. 11 is demonstrated.

First, a fourth interlayer insulating film 28 covering the capacitors 27a and 27b is formed on the third interlayer insulating film 20. As the fourth interlayer insulating film 28, a silicon oxide film having a film thickness of 2000 nm formed by plasma CVD is used.

Subsequently, the surface of the fourth interlayer insulating film 28 is polished and flattened by the CMP method. Polishing is performed until the fourth interlayer insulating film 28 has a thickness of about 2.0 to 2.5 mu m from the silicon substrate.

In addition, a photoresist 29 is coated on the fourth interlayer insulating film 28, and the photoresist 29 is exposed and developed to form windows 29b and 29c above the lower contact plugs 15b and 15c of the peripheral circuit portion 3. . Thereafter, the fourth interlayer insulating film 28 and the third interlayer insulating film 20 thereunder are anisotropically etched through the windows 29b and 29c to form the upper contact holes 28b and 28c.

In this case, a C ₄ F ₈ system is used as the etching gas. This slows down the etching rate of the silicon nitride film 18 below when the third and fourth interlayer insulating films 20 and 28 are etched.

Therefore, since the silicon nitride film 18 functions as an etching stopper film, the upper contact holes 28b and 28c are not formed in the second interlayer insulating film 12.

In FIG. 11, for the purpose of comparison with FIG. 5, the contact holes 28b and 28c are formed at positions protruding from the lower contact plugs 15b and 15c. It is formed aiming at a matching position.

Thereafter, the silicon nitride film 18 is etched through the contact holes 28b and 28c to expose the contact plugs 15b and 15c. In this case, the CHF ₃ system is used as the etching gas under the condition that the second interlayer insulating film 12 is hardly etched. As a result, the end portions of the contact holes 28b and 28c are present in the vicinity of the upper surfaces of the contact plugs 15b and 15c.

Thereafter, the photoresist 29 is peeled off. The photoresist 29 may be peeled off after the etching of the third and fourth interlayer insulating films 20 and 28.

In addition, when the upper contact holes 28b and 28c are formed by protruding from the lower contact plugs 15b and 15c, a part of the upper surface of the lower contact plugs 15b and 15c is covered by the silicon nitride film 18. .

Next, the process until forming the structure shown in FIG. 12 is demonstrated.

First, a Ti film 30a having a film thickness of 20 nm, a TiN film 30b having a film thickness of 20 nm, and a W film 30c having a film thickness of 300 nm are formed on the upper contact holes 28b and 28c and on the fourth interlayer insulating film 28. Are sequentially formed by the CVD method. Subsequently, the Ti film 30a, the TiN film 30b, and the W film 30c on the fourth interlayer insulating film 28 are selectively removed by the CMP method. The Ti film 30a, the TiN film 30b, and the W film 30c remaining in the contact holes 28a and 28b are used as the upper contact plugs 31a and 31b.

Thereafter, in the peripheral circuit portion 3, the wirings 32a and 32b are formed on the fourth interlayer insulating film 28, and the wirings 32a and 32b are formed of the upper contact plugs 31a and 31b and the lower contact plugs 15b, respectively. It is connected to the impurity diffusion layers 7a and 7b through 15c.

In addition, when the cross section seen from the VI-VI line in the memory cell part 2 of FIG. 12 is shown, it becomes like FIG.13 (b).

According to the above embodiment, since the sidewall 18s made of silicon nitride formed on the side of the bit line 16 of the memory cell portion 2 and the etching stopper film 18 of the peripheral circuit portion 3 are simultaneously formed, Thereafter, even if the upper contact holes 28b, 28c formed in the third and fourth interlayer insulating films 20, 28 of the peripheral circuit portion 3 protrude from the lower contact plugs 15b, 15c, the upper contact holes 28b, 28c) is prevented from falling down greatly from the top of the bottom contact plugs 15b and 15c.

In addition, since a certain heat treatment is usually required for the formation of the silicon nitride film, it is possible to adversely affect the characteristics of the MOSFET if two sidewalls and an etching stop film are formed, but by simultaneously forming them, the increase in heat treatment is minimized. You can do it.

Here, the upper limit of the film thickness of the silicon nitride film 18 is determined from the request that the space between the bit lines 16 is not narrowed more than necessary as shown in Fig. 13A, and the lower limit is It should be determined from the request as a stopper film for the formation of the upper contact holes 28a and 28b of the peripheral circuit portion 3. The film thickness of the stopper film also depends on the film thickness of the upper interlayer insulating film, but a film thickness of at least 20 to 30 nm is required.

The positional relationship seen from the plane of the bit line 16, the gate electrode 6, and the contact portion of the memory cell portion 2 is as shown in FIG. In FIG. 14, the cross section seen from the line VII-VII is (a) of FIG. 7, and the cross section seen from the VIII-VIII line is (a) of FIG.

In addition, instead of the silicon nitride film 18 formed on the second interlayer insulating film 12 of the peripheral circuit portion 3, another material film serving as an etching stopper at the time of etching the third interlayer insulating film 20, for example, For example, an oxynitride silicon film (SiON) or an alumina (Al ₂ O ₃ ) film may be formed.

By the way, as a countermeasure for solving the problem of the conventional example shown in Fig. 5, an etching stop film serving as a conductive layer may be formed between the upper plugs 122b and 122c and the lower plugs 112b and 112c. For example, when the bit line 115 is processed, the patterning of the conductive layer having a size predicting the positional deviation of the upper contact holes 121b and 121c and the deviation of the diameter is performed by the upper plugs 122b and 122c and the lower plug 112b. And 112c). This makes it possible to avoid the upper plugs 122b and 122c from falling from the lower plugs 112b and 112c. However, in this case, the patterning of the conductive layer needs to be the size predicted by the deviation of the positional deviation and the diameter deviation, so that, for example, the size of the conductive layer becomes larger than the lower contact holes 111b and 111c by about 0.2 µm, for example.

In the case where the plurality of lower plugs 112b and 112c to which different potentials are applied are adjacent to each other, the lower plug 112b is provided because a restriction is placed so that the patterning of the conductive layers formed on the lower plugs 112b and 112c is not shorted. , The gap between the lower contact holes 111b and 111c into which 112c is embedded is increased, and further, the chip size is increased.

Since high integration and miniaturization are required in the peripheral circuit portion of the mixed DRAM, there is little room for arranging the pattern of the conductive layer.

(Second embodiment)

15 is a sectional view showing a second embodiment of the present invention. 16 is a VIII-VIII cross-sectional view of FIG. In addition, in FIG.15, 16, the code | symbol same as FIG.12 has shown the same element.

In this embodiment, the silicon nitride film 18 shown in Fig. 7B of the first embodiment is left on the entire surface without patterning, and the upper portion of the bit line 16 and the storage contact in the memory cell portion 2 is left. It is used as a short circuit prevention film of the contact plug 21 and used as an etching stopper film in the peripheral circuit part 3.

In this case, the etching for forming the upper contact hole 20b for the storage contact is performed in three steps in which the silicon nitride film 18 is added to the etching of the third interlayer insulating film 20 and the second interlayer insulating film 12. It is necessary.

By the way, even when the position shift occurs between the bit lines 16 when forming the holes 20b for the storage contacts as shown in FIG. 16, the silicon nitride film 18 is subjected to the bit lines 16 after the etching. Since it remains on the side of the bit line 16, the bit line 16 is not exposed.

In the case of this embodiment, compared with the first embodiment, the formation of the photoresist 19 serving as a mask can be omitted in one step, which is advantageous in terms of cost.

(Third embodiment)

In FIG. 10 of the first embodiment, after the cell plate electrode 26 is patterned, the silicon nitride film 22 below it is also patterned continuously.

However, as shown in FIG. 17, the silicon nitride film 22 may be left over without patterning.

In this case, when the dielectric film 25 of the capacitor is made of silicon nitride, the dielectric film 25 may also be left.

In such a case, when the silicon nitride film 22 serving as the base of the capacitors 27a and 27b is not etched, the process of forming the upper contact holes 28b and 28c in the peripheral circuit portion 3 is as follows. .

That is, when etching the fourth interlayer insulating film 28, the silicon nitride film 22 below is temporarily made an etching stopper, after which the silicon nitride film 22 is etched, and the third interlayer insulating film 20 ) And the silicon nitride film 18 is subsequently etched to form upper contact holes 28b and 28c.

According to such a process, the silicon nitride film 22 can cancel the dispersion | variation in the film thickness in the wafer surface and the chip | tip of the 4th interlayer insulation film 28 after grinding | polishing the surface once. Manufacturing margins are improved. In addition, since the silicon nitride film 22 is left when the cell plate electrode 26 is patterned, the etching process is not increased in comparison with the first embodiment.

In this embodiment, the silicon nitride film 18 may be removed from the peripheral circuit portion 3 without forming the photoresist 19 shown in FIG. 7B in the peripheral circuit portion 3.

In addition, in FIG. 17, the same code | symbol as FIG. 12 has shown the same element.

(Example 4)

18 is a cross-sectional view showing a semiconductor device of a fourth embodiment of the present invention. In addition, in FIG. 18, the same code | symbol as FIG. 12 has shown the same element.

In the present embodiment, the lower contact plugs 15d and 15e connected to the impurity diffusion layers 7a and 7b in the peripheral circuit portion 3 are formed below the third interlayer insulating film 20 and the upper contact plugs 31c and 31d. ) Is formed on the fourth interlayer insulating film 28 and the silicon nitride film 22.

That is, as shown in FIG. 6B of the first embodiment, the upper contact hole 13a is formed in the second interlayer insulating film 12 of the memory cell portion, and at the same time, the contact hole 13b below the peripheral circuit portion 3 is formed. The first, second and third interlayer insulating films 9, 12, and 20 in the peripheral circuit portion 3 before or after forming the upper contact plug 21 for the storage contact without forming the first, second, and 13c. It has a structure in which contact holes 13d and 13e are formed.

In addition, the contact plugs 15d and 15e formed in the contact holes 13d and 13e have a three-layer structure of a Ti film, a TiN film, and a W film as in the first embodiment. That is, after the Ti film, the TiN film, and the W film are formed in the contact holes 13d and 13e and over the third interlayer insulating film 20, the metal film on the third interlayer insulating film 20 is removed by the CMP method. As a result, the metal film remaining in the lower contact holes 13d and 13e is used as the contact plugs 15d and 15e.

In this embodiment, the silicon nitride film 18 may be removed from the peripheral circuit portion 3 in the peripheral circuit portion 3 without forming the photoresist 19 shown in FIG.

Instead, the silicon nitride film 22 formed under the capacitors 27a and 27b is left without being removed from the peripheral circuit portion 3. According to this, when the fourth interlayer insulating film 28 is patterned in the peripheral circuit section 3 to form the upper contact holes 28d and 28e, the silicon nitride film 22 below the film becomes an etching stopper film. The deviation of the thick fourth interlayer insulating film 28 can be offset.

As described above, the contact holes 13d and 13e are formed in the first, second and third interlayer insulating films 9, 12 and 20, and the upper contact holes 28d and 28e are formed in the third interlayer insulating film 28. The upper contact holes 28d and 28e are shallower than those of the first embodiment in the case of forming the upper surface, so that processing is easy.

(Example 5)

In the fourth embodiment, the lower contact holes 13d and 13e formed in the peripheral circuit portion 3 are formed before or after the upper contact hole 20b for the storage contact of the memory cell portion 2, but they are formed. You may form simultaneously.

In this case, as shown in FIG. 19, the Ti film, the TiN film, and the W film which are sequentially formed in the contact holes 13d and 13e are also formed in the hole 20b for storage contact.

Therefore, when forming the contact holes 13d and 13e and the hole 20b for a storage contact simultaneously, doped silicon is not formed in the hole 20b for a storage contact, and the metal film of a three-layer structure is formed, This will be used as the upper contact plug 21a.

In this case, the storage electrode 24a connected to the upper contact plug 21a does not need to be made of silicon, but can be made of platinum, ruthenium, ruthenium oxide, strontium ruthenate, or other metals. When ruthenium oxide is used as the storage electrode 24a, an oxide dielectric film such as barium strontium titanate (BST), strontium titanate (STO), tantalum oxide, or PZT is used as the capacitor dielectric film 25a. As the plate electrode 26a, the same material as that of the storage electrode 24a may be used.

In addition, in FIG. 19, the same code | symbol as FIG. 18 has shown the same element.

(Example 6)

As shown in FIG. 20, the semiconductor device of this embodiment has three stages of contact plugs connected to the impurity diffusion layers 7a and 7b of the peripheral circuit section 30. As shown in FIG.

In this embodiment, in FIG. 8B of the first embodiment, the second and third interlayer insulating films 12 and 20 of the memory cell portion 2 are patterned to form the upper contact hole 20b for storage contact. At the same time, at the same time, the second interlayer insulating film 20 of the peripheral circuit portion 3 is patterned to form an intermediate contact hole 20c above the lower contact plugs 15b and 15c.

In this case, etching of the second interlayer insulating film 20 is stopped under the silicon nitride film 18 below, whereby the intermediate contact hole 20c is made larger from the lower contact plugs 15b and 15c. Will not fall. Thereafter, the silicon nitride film 18 is selectively etched through the intermediate contact hole 20c, thereby connecting the intermediate contact hole 20c to the contact plugs 15b and 15c.

Thereafter, in the upper contact hole 20b for the storage contact of the memory cell unit 2 and the contact hole 20c in the middle of the peripheral circuit region 3, a three-layer structure of titanium, titanium nitride, and tungsten, respectively, A metal film is formed. As a result, an upper contact plug 21b made of a metal film is formed in the upper contact hole 20b, and intermediate contact plugs 33b, 33c made of a metal film are formed in the intermediate contact hole 20c. do.

The metal film formed on the third interlayer insulating film 20 is removed by the CMP method.

As described above, when the contact plug 21b in the upper contact hole 20c for the storage contact of the memory cell portion 2 is made of metal, the capacitors 27a and 27b are similar to those shown in the fifth embodiment. It is good also as a structure.

Upper contact plugs 31c and 31d formed by the same process as in the fifth embodiment are connected to the intermediate contact plugs 33b and 33c formed in the peripheral circuit portion 3.

The upper contact holes 28d and 28e into which the upper contact plugs 31c and 31d are embedded are formed by using the silicon nitride film 22 formed under the fourth interlayer insulating film 28 as an etching stopper. same.

As described above, when the number of stages of the contact plugs formed in the interlayer insulating film is increased in the peripheral circuit section 3, the holes for embedding the contact plugs become shallow, so that the processing becomes easy. In this case, at the time of etching for forming the intermediate and upper contact holes 20c, 28d, and 28e, the silicon nitride films 18 and 22 serve as etching stoppers.

In addition, since the depths of the contact holes 20c, 28d, and 28e are shallow, either or both of the silicon nitride films 18 and 22 may be removed from the peripheral circuit portion 3.

In addition, in FIG. 20, the same code | symbol as FIG. 19 has shown the same element.

(Example 7)

In the first embodiment, as shown in Figs. 6B and 7A, an upper contact hole 13a is formed in the second interlayer insulating film 12, and the upper contact plug 15a is formed therein. After forming the metal film, the metal film constituting the bit line 16 is formed on the second interlayer insulating film 12.

However, it is also possible to form the bit line 16 and the contact plug 15a below it at once, and the process is demonstrated below based on FIG. In addition, in FIG. 21, the same code | symbol as FIG.6 (b) has shown the same element.

First, from the state shown in Fig. 6B, the upper contact hole 13a for the bit line contact of the memory cell unit 2 and the contact holes 13b and 13c of the peripheral circuit unit 3 and the second layer are interposed. On the insulating film 12, a titanium film 41a having a film thickness of 50 nm, a titanium nitride film 41b having a film thickness of 50 nm, and a tungsten film 41c having a film thickness of 150 nm are sequentially formed by the CVD method, followed by tungsten. On the film 41c, a protective insulating film 42 made of titanium nitride having a film thickness of 100 nm is formed by the CVD method.

Next, as shown in Fig. 21B, the titanium film 41a, the titanium nitride film 41b, and the tungsten film 41c are patterned by the normal photolithography method, so that the bits of the memory cell portion 2 are patterned. At the same time as forming the line 43, the lower contact plugs 44b and 44c of the peripheral circuit portion 3 are formed. In this case, the bit line 43 is directly connected to the lower contact plug 11a.

By the way, the film thickness of the tungsten film 41c is preferably set to a sufficient thickness so that the protective insulating film 42 does not enter the lower contact plugs 44b and 44c of the peripheral circuit portion 3, and the bit line 43 It is preferable to be thin to the extent that processing is easy.

In the present embodiment, the metal film on the second interlayer insulating film 12 is removed by the CMP method and left in the contact holes 13b and 13c. As a result, the number of process steps is greatly reduced. Further, since the metal film constituting the contact plugs 44b and 44c and the metal film constituting the bit line 43 are performed in the same film forming process, the film formation of titanium, titanium nitride and tungsten can be omitted once. Here, the protective insulating film 42 made of silicon nitride is used to prevent a short circuit between the upper contact plug 21 for the storage contact and the bit line 43, similarly to the protective insulating film 17 of the first embodiment. .

Next, as shown in Fig. 21C, on the bit lines 43, the plugs 44b and 44c and the second interlayer insulating film 12, a silicon nitride film 18 having a film thickness of 50 nm is subjected to the reduced pressure CVD method. And the photoresist 19 covering the peripheral circuit portion 3 is subsequently formed. The subsequent process is the same as in the first embodiment.

Claims (21)

A first impurity diffusion layer formed in the first region of the semiconductor substrate, A second impurity diffusion layer formed in a second region of the semiconductor substrate, A first insulating film formed on the semiconductor substrate; A first hole in the first region and formed on the first impurity diffusion layer; A first conductive plug formed in the first hole, A wiring formed on the first insulating film in the first region, A second insulating film formed on the wiring and the first insulating film in the first and second regions; A second hole formed in said second insulating film in said first region and away from said wiring and connected to said first hole, An electrode formed on said second insulating film in said first region and electrically connected to said first conductive plug through a second hole; A third hole formed over the second impurity diffusion layer in the first insulating film of the second region, A fourth hole formed on the third hole in the second insulating film of the second region, A second conductive plug formed in the third hole, A third conductive plug formed in the fourth hole; And a third insulating film formed of a material different from the second insulating film, formed on the side surface of the wiring, and formed around the connecting portion of the second conductive plug and the third conductive plug. The method of claim 1, And the third insulating film is in contact with a portion of or above the upper surface of the second conductive plug. The method of claim 1, And the third insulating film is between the first insulating film and the second insulating film, and extends into the first region and the second region. The method of claim 1, A third impurity diffusion layer formed on the semiconductor substrate in the first region, A fifth hole formed on the third impurity diffusion layer in the first insulating film, And a fourth conductive plug formed in said fifth hole and electrically connected to said wiring. The method of claim 1, A fourth insulating film formed on the second insulating film and the electrode; And a sixth hole formed in the fourth insulating film in the second region and connected to the fourth hole. The method of claim 5, And the fourth hole is an extension of the sixth hole, and the third conductive plug is formed in the fourth hole and the sixth hole. The method of claim 1, A fifth insulating film formed between the electrode in the first region and the second insulating film and formed on the second insulating film in the second region; A fourth insulating film made of a material different from the fifth insulating film and formed on the fifth insulating film; And a seventh hole formed in the fourth insulating film and the fifth insulating film and connected to the fourth hole. The method of claim 7, wherein And the fourth hole is on an extension of the seventh hole, and the third conductive plug is also formed in the seventh hole. The method of claim 1, And the first region is a region where a memory cell is formed, and the second region is a region where a peripheral circuit is formed. A first impurity diffusion layer and a second impurity diffusion layer formed in the first region of the semiconductor substrate, A third impurity diffusion layer formed in a second region of the semiconductor substrate, A first insulating film covering the first, second and third impurity diffusion layers; A first hole formed in the first insulating layer in the first region, A first conductive plug formed in the first hole, A second insulating film formed on the first conductive plug and the first insulating film; A second hole formed in the second insulating film in the first region and exposing the first conductive plug; A third hole formed in said first region and said second insulating film and having a depth reaching said third impurity diffusion layer; A second conductive plug formed in the third hole, A wiring formed on the second insulating film and electrically connected to the first conductive plug through the second hole; A third insulating film formed on the second conductive plug, the wiring side surface, and the second insulating film; A fourth insulating film formed over the third insulating film and made of a material different from the third insulating film; And a fourth hole formed in said third and said fourth insulating films in said second region, wherein at least a portion of said second conductive plug overlaps with said second conductive plug. Forming a first impurity diffusion layer and a second impurity diffusion layer in a first region of the semiconductor substrate, Forming a third impurity diffusion layer in a second region of the semiconductor substrate; Forming a first insulating film on the semiconductor substrate, the first insulating film covering the first, second and third impurity diffusion layers; Patterning the first insulating film in the first region to form first holes and second holes on the first impurity diffusion layer and the second impurity diffusion layer, respectively; Forming a first conductive plug and a second conductive plug in the first and second holes, respectively; Forming a wiring electrically connected to the first conductive plug on the first insulating film; Patterning the first insulating film in the second region to form a third hole having a depth reaching the third impurity diffusion layer; Forming a third conductive plug in the third hole; Forming a second insulating film on the third conductive plug, the wiring, and the first insulating film; Forming a third insulating film formed of a material different from the second insulating film on the second insulating film; In the second region, using the second insulating film as an etch stop layer, and patterning the third insulating film to form a fourth hole at least partially overlapping the third conductive plug; Selectively etching the second insulating film through the fourth hole to expose an upper surface of the third conductive plug; And forming a fourth conductive plug connected to the upper surface of the third conductive plug in the fourth hole. The method of claim 11, Forming a fourth insulating film covering the first conductive plug, the second conductive plug, and the first insulating film between the wiring and the first insulating film; Patterning the fourth insulating film in the first region to form a fifth hole between the first conductive plug and the wiring; And further comprising forming an upper portion of the third hole in the fourth insulating film. The method of claim 12, And a fifth step of forming a fifth plug in said fifth hole. The method of claim 11, And etching the second insulating film in the first area while covering at least a portion of the second insulating film with the mask in the second area, thereby leaving the second insulating film on the side of the wiring in the first area. The manufacturing method of the semiconductor device characterized by the above-mentioned. The method according to claim 11 or 14, A protective insulating film made of the same material as that of the second insulating film is formed on the wiring. The method according to claim 11 or 12, Patterning at least the second and third insulating films in the first region to form a sixth hole exposing an upper surface of the second conductive plug; Forming a sixth conductive plug in the sixth hole; Forming an electrode connected to the sixth conductive plug on the third insulating film; Forming a fifth insulating film on the electrode and the third insulating film; And forming a seventh hole connected to said fourth hole in said fifth region in said second region. The method of claim 16, And the seventh hole and the fourth hole are continuously formed. The method of claim 17, And after forming the seventh hole, simultaneously forming the fourth conductive plug in the seventh hole and the fourth hole. The method of claim 16, The electrode is formed as a lower electrode of the capacitor, And after forming the lower electrode, forming a dielectric film on the electrode, and forming an upper electrode on the dielectric film. The method of claim 16, And forming a sixth insulating film, which is an etching stopper film of the fifth insulating film, on the third insulating film. The method of claim 20, And the sixth insulating film is etched through the seventh hole after forming the seventh hole in the fifth insulating film.