KR20020091468A - Wafer-level packaging process - Google Patents

Abstract

PURPOSE: A wafer level packaging method is provided to simplify a wafer level packaging process by forming a stress buffer layer, bumps and scribe lines on a wafer, and to simply dice the wafer without misalignment after a packaging process by making the scribe lines confined by patterned photoresist formed on the wafer. CONSTITUTION: The patterned photoresist is formed on the wafer(100) covering a plurality of scribe lines(112) and bump formation positions. The stress buffer layer(109) is formed on a region not covered with the patterned photoresist. After the patterned photoresist is eliminated, a plurality of the first openings are confined in the scribe line or the exposed stress buffer layer. The second patterned photoresist having the plurality of the second openings are aligned with the upper surface of the wafer to cover a stencil, the stress buffer layer and the scribe lines so that the second openings expose the first openings. A solder material is filled in the openings. A reflow process is performed according to the use of the stencil or the second photoresist before or after the stencil or the second photoresist is eliminated.

Description

Wafer-level packaging process

The present invention relates to a wafer-level packaging method. More particularly, the present invention relates to a wafer-level packaging method using a stress buffer layer on the wafer instead of underfill.

As electronic technology advances, a special emphasis is placed on miniaturization of electronic products. This miniaturization ultimately results in more complex and dense electronics. In the electronics industry, package structures having small dimensions and high density are required for the packaging of electronic devices. Ball Grid Array (BGA) Package, Chip-Scale Package (CSP), Flip-Chip (F / C) Package, and Multi-Chip Module (MCM) Many types of packages have been developed, such as packages.

Among the packages of the type described above, flip chip packages offer many advantages, such as small surface area of the package, high pin count, short signal path, low induction and easy control of noise signal. Thus, flip chip structures are increasingly used in the packaging of electronic devices.

In a typical flip chip package, an underfill must be formed between the chip and the carrier or a printed circuit board to which the chip is connected. The underfill shares the thermal stresses generated by the difference in coefficient of thermal expansion between the carrier and the chip, thereby substantially protecting the bumps that electrically connect the chip to the carrier from weakening due to thermal cycles.

With increasing integration of packaging, the pitch between bumps formed on a chip is constantly decreasing. For flip chip packages, effectively filling the underfill without empty space becomes a problem and increases manufacturing costs. Therefore, there is a need for a solution that can overcome the above problems to enable a reliable flip chip.

One object of the present invention is to provide a wafer-level packaging method in which a stress buffer layer is appropriately formed on the wafer to replace the underfill of the conventional packaging method so that wafer-level packaging can be easily obtained.

1-4 are schematic cross-sectional views of various steps of a wafer-level packaging method according to a first preferred embodiment of the present invention.

5-8 are cross-sectional views schematically illustrating the various steps of a wafer-level packaging method according to a second preferred embodiment of the present invention.

In order to achieve the above and other objects, the present invention provides a method comprising: providing a wafer having a plurality of chips having a plurality of bonding pads, each chip exposed through a passivation layer formed on the surface of the wafer; Respectively forming an under ball metallurgy (UBM) on each bonding pad; Forming a patterned photoresist on the wafer to define a plurality of scribe lines and a plurality of bump formation positions; Forming a stress buffer layer over the wafer in a region not covered by the patterned photoresist; Removing the patterned photoresist; Applying a stencil having a plurality of openings to the stress buffer layer and scribe lines such that the openings expose the bump forming positions; Filling solder material into the openings; Removing the stencil; And performing a reflow process to form the bumps at the bump formation positions.

Moreover, the present invention also provides a method of producing a wafer comprising a plurality of chips having a plurality of bonding pads, each chip having a plurality of bonding pads exposed through a passivation layer formed on a surface of the wafer; Forming a first patterned photoresist on the wafer to define a plurality of scribe lines and a plurality of bump formation positions; Forming a stress buffer layer over the wafer in a region not covered by the first patterned photoresist; Removing a first patterned photoresist defining a plurality of first openings in the stress buffer layer corresponding to the position of the bonding pads; Forming a UMB on each bonding pad exposed through each first opening, wherein the UMB covers the sidewall of the bonding pad and the first opening and overlaps the stress buffer layer; Forming a second patterned photoresist having a plurality of second openings on the stress buffer layer and scribe lines, such that the second openings expose the first openings; Filling solder material into the first and second openings; Performing a reflow process to form the bumps; And removing the second patterned photoresist.

After the packaging process described above, the wafer is diced and connected on a carrier by Flip-chip interconnection technology. With stress buffer layers replacing conventional underfills, flip-chip packages are simply obtained with substantially reduced manufacturing costs.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to further explain the invention as claimed.

Detailed description of the embodiments and test examples of the present invention with reference to the accompanying drawings is only illustrative and not limiting.

1-4, several cross-sectional views schematically illustrate various steps of a wafer-level packaging method according to a preferred embodiment of the present invention.

1, the wafer 100 is provided with a plurality of bonding pads 102 thereon. A passivation layer 104 is formed on the surface of the wafer 100 and exposes the bonding pads 102 thereon. An under ball metallurgy portion (UBM) 106 is formed on the exposed bonding pads 102. The UMB can be made of multiple layers of chromium / chromium-copper / copper, for example. A patterned photoresist 108 is formed over the wafer 100 to cover the UMBs 106 and scribe lines. The patterned photoresist 108 may be, for example, a liquid photoresist or a dry film.

Referring to FIG. 2, a stress buffer layer 109 is next formed in an area not covered by the patterned photoresist 108. The stress buffer layer 109 may be made of epoxy, for example, to provide an effective stress buffer. Next, the patterned photoresist 108 is removed so that the plurality of first openings 110 expose the UBI 106 and the plurality of scribe lines 112 to the stress buffer layer 109. It is limited within. The first openings 110 are positions where bumps will be formed later.

Referring to FIG. 3, a stencil 114 is next applied on the stress buffer layer 109 to cover the scribe lines 112. When the stencil 114 is aligned on the stress buffer layer 109, the stencil 114 has a plurality of second openings 115 therein aligned with the first openings. Next, solder material 116 is filled in the first openings 110 and the second openings 115. For example, in this embodiment of the invention, the size of the openings 115 is larger than the size of the first openings 110. The solder material 116 is, for example, a tin-lead paste that may have various ratios, Sn _x Pb _y of x + y = 100. However, the solder material 116 may also be comprised of other solder components not mentioned in the detailed description of the present invention.

Referring to FIG. 4, the stencil 114 is then removed to expose the scribe lines 112 for subsequent dicing of the wafer 200. The solder material 116 is then reflowed to form a plurality of bumps 118. The bumps 118 formed by the generation of surface tension during reflow of the solder material partially overlap over the stress buffer layer 109.

5-8, several cross-sectional views schematically illustrate a wafer-level packaging method according to a second preferred embodiment of the present invention.

Referring to FIG. 5, a wafer 200 is provided with a plurality of chips formed thereon, each chip having a plurality of bonding pads 202 exposed through a passivation layer 204 formed on the wafer 200. have. A patterned photoresist 208 is then formed on the wafer 200 to cover the bump formation positions and scribe lines. The patterned photoresist 208 may be, for example, a liquid photoresist or a dry film.

Referring to FIG. 6, a stress buffer layer 209 is next formed over the wafer in an area not covered by the patterned photoresist 208. The stress buffer layer 209 may be made of epoxy, for example, to provide effective stress buffer characteristics. Next, the patterned photoresist 208 opens a plurality of first openings 210 exposing the bonding pads 202 on which the scribe lines 212 and the UMBs 206 are formed. Removed to form. The first openings 210 are then positions where bumps are to be formed.

Referring to FIG. 7, an isolation layer is formed to cover the bonding pads 202, the scribe lines 212, and the stress buffer layer 209 at the bottom of the first openings 210. do. A UMB 206 is then formed over each bonding pad 202, and the UMB 206 covers the sidewalls of the bonding pads 202 and the first openings 210. In this embodiment, the UMB 206 is formed to overlap with the stress buffer layer 209. In the first embodiment of the present invention, the UMBs 206 only cover the bonding pads 202. In contrast, in the second embodiment, the isolation layer 207 is formed on the passivation layer 204 and the stress buffer layer 209.

Next, another patterned photoresist 214 is formed to cover the stress buffer layer 209 and the scribe lines 212. The patterned photoresist 214 has a plurality of second openings 215 aligned with the first openings 210. Then, the solder material 216 is filled in the first openings 210 and the second openings 215. For example, in this embodiment of the present invention, the size of the second openings 215 is larger than the size of the first openings 210. The solder material 216 is, for example, a tin-lead paste, which may have various ratios, Sn _x Pb _y of x + y = 100. However, the solder material 216 may also be composed of other solder components not mentioned herein.

Referring to FIG. 8, a plurality of bumps 218 are formed after reflow of the solder material 216. The bumps 218 formed as above have a portion overlapping the stress buffer layer 209. Next, the patterned photoresist 214 and the separation layer 207 that are not covered by the bumps are removed. The isolation layer 207 is intended to ensure effective and complete removal of the patterned photoresist 214 after reflow.

In the method of the present invention, the stress buffer layer, the bumps and the scribe lines are all formed on the wafer, resulting in simplified wafer level packaging.

Furthermore, since the scribe lines are defined by the patterned photoresist formed on the wafer, the wafer after being packaged can simply be diced without the problem of misalignment. Warping of the wafer, which may occur in subsequent thermal processes, can be avoided due to the scribe lines.

These individualized chips can be flipped after the wafer is diced, can be directly connected to the printed circuit board or carrier, and the stress buffer layer advantageously excludes conventional underfill methods. By replacing the conventional underfill by the stress buffer layer of the present invention, packaging is easily obtained at low cost.

According to the method described above, even in the case where the pitch of bumps decreases, the limitations of the conventional underfill method can still be overcome advantageously, while the wiper-level packaging method is also simplified.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

Claims (9)

Is performed on the wafer with a plurality of chips having a plurality of bonding pads exposed through a passivation layer covering the wafer, Forming each UMB on each bonding pad; Forming a first patterned photoresist on the substrate to define a plurality of scribe lines and a plurality of bump formation positions where a plurality of bumps should be subsequently formed corresponding to the position of the UMB. ; Forming a stress buffer layer to cover areas not covered by the first patterned photoresist; Removing the first photoresist such that the stress buffer layer has a plurality of first openings exposing the bump forming positions; Applying a stencil having a plurality of second openings on the wafer to cover the stress buffer layer and the scribe lines such that the second openings expose the first openings; Filling solder material into the first and second openings; And Wafer-level packaging method comprising performing a reflow process, and then removing the stencil. The packaging method of claim 1, wherein the stress buffer layer is formed by screen printing. The method of claim 1 wherein the stress buffer layer is formed by dispensing. 2. The method of claim 1, wherein said stress buffer layer is made of epoxy. Is performed on the wafer with a plurality of chips having a plurality of bonding pads exposed through a passivation layer covering the wafer, Forming a first patterned photoresist to define a plurality of scribe lines and a plurality of bump formation positions where a plurality of bumps respectively must be formed corresponding to the bonding pads; Forming a stress buffer layer covering areas not covered by the first patterned photoresist; Removing the first photoresist such that the stress buffer layer has a plurality of first openings exposing the bump forming positions; Forming each of the UMBs on the bonding pads so that each UMB covers the sidewalls of the bonding pads and the first openings and overlaps the stress buffer layer; Forming a second patterned photoresist having a plurality of second openings to cover the stress buffer layer and scribe lines, the first openings being exposed through the second openings; Filling solder material into the first and second openings; And Performing a reflow process and then removing the second patterned photoresist. The packaging method according to claim 5, wherein the stress buffer layer is formed by screen printing. 6. The method of claim 5, wherein said stress buffer layer is formed by dispensing. 6. The method of claim 5, wherein said stress buffer layer is made of epoxy. 6. The method of claim 5, wherein a buffer layer is formed on the wafer before the UMBs are formed to ensure complete removal of the second patterned photoresist after the reflow process.