KR20020088652A - Sram using dram cell capable of controlling refresh operation of the dram - Google Patents

Abstract

PURPOSE: An SRAM compatible memory device using a DRAM cell for controlling a refresh operation is provided to perform a normal operation by minimizing a delay time in a process for generating a normal operating signal. CONSTITUTION: An oscillation circuit(110) can be formed by a ring oscillator. The oscillation circuit(110) generates an oscillation signal(VOSC) to a refresh relay circuit(140). A pulse generator(120) receives an external address signal(ADDR) and generates a normal operating control signal(PPZ) to a normal operating signal activation circuit(130). The normal operating signal activation circuit(130) receives the normal operating control signal(PPZ), activates a normal operating signal(CEN), and provides the normal operating signal(CEN) to the refresh relay circuit(140). The refresh relay circuit(140) is used for masking the oscillation signal(VOSC) by using the normal operating signal(CEN).

Description

SRAM compatible memory device using DRAM cell that can control refresh operation {SRAM USING DRAM CELL CAPABLE OF CONTROLLING REFRESH OPERATION OF THE DRAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory (SRAM) compatible memory device using a dynamic random access memory (DRAM) cell.

In general, random access memory (RAM) of the semiconductor memory device may be classified into SRAM and DRAM. Here, the unit memory cell (SRAM cell) of the SRAM is typically implemented with four transistors forming a latch structure and two transistors serving as transfer gates. That is, since the SRAM stores a data signal in a unit memory cell having a latch structure, a refresh operation for preserving the data signal is not required. In addition, compared to DRAM, SRAM has the advantages of fast operating speed and low power consumption.

However, since the unit memory cell of the SRAM is implemented by six transistors, the layout area of the SRAM is larger than that of the DRAM unit memory cell (DRAM cell), which is implemented by one transistor and one capacitor. In other words, when the RAM of the same capacity is manufactured, since the layout area of the SRAM is 6 to 10 times larger than the layout area of the DRAM, the SRAM is not suitable for large data accumulation.

In order to overcome the drawbacks of DRAM and SRAM as described above, studies have recently been actively conducted to implement an SRAM compatible memory device having a structure of a DRAM cell and performing an interface as an SRAM. Since the SRAM compatible memory device has DRAM cells, it is required to perform a refresh operation for preserving stored data within a predetermined refresh period.

In order to perform the refresh operation as described above, the SRAM compatible memory device includes a timer for generating a refresh request command every predetermined time. However, in the SRAM compatible memory device incorporating the timer, timing overlap between a normal operation and a refresh operation for inputting / outputting data to / from the DRAM cell may occur. In other words, the normal operation signal may be generated during the refresh operation, or the refresh request signal may be generated during the normal operation.

In this case, when the timing overlaps, the existing SRAM compatible memory device executes a first generated command and then a later generated command. That is, if a normal operation signal is generated during the refresh operation, the conventional SRAM compatible memory device performs the normal operation after completing the refresh operation, and when the refresh request signal is generated during the normal operation, After completing the normal operation, perform the retry operation.

However, in the conventional SRAM compatible memory device as described above, when a normal operation signal is generated while performing a refresh operation, the start time of the normal operation is delayed after the completion of the refresh operation, and thus the processing speed of data decreases. I have a problem.

The present invention has been made in an effort to provide an SRAM compatible memory device which performs a normal operation by minimizing a delay when a normal operation signal is generated in order to effectively solve the above-described problems of the related art.

In order to better understand the drawings used in the detailed description of the drawings, a brief description of each drawing is provided.

1 is a block diagram conceptually illustrating an SRAM compatible memory device using a DRAM cell capable of controlling a refresh operation according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the refresh arbitration circuit of FIG. 1 in detail.

3 is a timing diagram illustrating a case in which a normal operation is performed in an SRAM compatible memory device of the present invention.

4 is a block diagram conceptually illustrating an SRAM compatible memory device using DRAM cells capable of controlling a refresh operation according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating the refresh arbitration circuit of FIG. 4 in detail.

FIG. 6 is a circuit diagram illustrating the refresh forced execution circuit of FIG. 4 in detail.

FIG. 7 is a circuit diagram illustrating the logic sum circuit of FIG. 4 in detail.

<Description of the symbols for the main parts of the drawings>

110: oscillation circuit 120: pulse generator

130: normal operation signal activation circuit 140: refresh arbitration circuit

150: refresh driving circuit

One aspect of the present invention for achieving the above technical problem relates to an SRAM compatible memory device that can control the refresh operation. The RAM device of the present invention has a DRAM cell in which a refresh operation for preserving stored data is required within a predetermined refresh period, performs an SRAM interface, and performs a refresh operation of the DRAM cell at every refresh period. The refresh operation is stopped while performing a normal operation of inputting / outputting data to / from the outside.

Preferably, the oscillating circuit for generating the oscillation signal oscillation signal is oscillated in a predetermined oscillation period; A normal operation signal activation circuit for receiving a predetermined control signal input from the outside and activating a normal operation display signal representing the normal operation; And a refresh arbitration circuit for activating a refresh request signal for performing the refresh operation in response to the oscillation signal, and stopping the activation of the refresh request signal for a predetermined period when the normal operation display signal is activated.

Another aspect of the present invention for achieving the above technical problem relates to an SRAM compatible memory device capable of controlling the refresh operation to be performed immediately after the normal operation is finished. An SRAM compatible memory device of the present invention includes an oscillation circuit for generating an oscillation signal oscillated at a predetermined oscillation period; A normal operation signal activation circuit for activating a normal operation display signal indicating a normal operation of receiving a predetermined control signal input from the outside and inputting / outputting data to / from the outside; A refresh arbitration circuit activating a refresh request signal for performing the refresh operation in response to the oscillation signal, and stopping the activation of the refresh request signal for a predetermined period when the normal operation display signal is activated; A refresh forced execution circuit for controlling the refresh request signal to respond to the oscillation signal despite the activation of the normal operation display signal; And a logic sum circuit for logic-suming the output signals of the refresh arbitration circuit and the refresh forced execution circuit to output the refresh request signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, an SRAM compatible memory device capable of controlling a refresh operation according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7.

FIG. 1 is a block diagram conceptually illustrating an SRAM compatible memory device capable of controlling a refresh operation using a DRAM cell according to a first embodiment of the present invention. Referring to FIG. 1, an SRAM compatible memory device according to a first embodiment of the present invention may include an oscillation circuit 110, a pulse generator 120, a normal operation signal activation circuit 130, a refresh arbitration circuit 140, and a refresh. The driving circuit 150 is provided.

In the present embodiment, the oscillation circuit 110 may be implemented as a ring oscillator, and after the SRAM compatible memory device according to the present invention is initially driven, that is, powered up, An oscillation signal (VOSC) in the form of a pulse oscillated at an oscillation period (about 10 ms) is generated and provided to the refresh arbitration circuit 140.

The pulse generator 120 receives a command for performing a normal operation from the outside, that is, an external address signal ADDR, an external chip select signal / CS and a write enable signal for selecting an SRAM compatible memory device. When / WE) is activated, a pulse type normal operation control signal PPZ is generated and provided to the normal operation signal activation circuit 130. In this embodiment, the normal operation control signal PPZ is generated in the form of a pulse having a width of 5 kHz.

The normal operation signal activation circuit 130 receives a normal operation control signal PPZ from the pulse generator 120 to perform a normal operation and a normal operation signal CEN to perform a normal operation. Activates the normal operation indication signal CEN1 indicating the fact. In this case, the normal operation indication signal CEN1 is provided to the refresh arbitration circuit 140 to be used for masking the oscillation signal VOSC. The normal operation signal CEN is provided to circuits for normal operation to drive normal operation of the SRAM compatible memory device of this embodiment. Each of the normal operation signal CEN and the normal operation display signal CEN1 is output in the form of a pulse having a width of about 20 ms and about 30 ms. That is, the pulse width of the normal operation display signal CEN1 is larger than the normal operation signal CEN by about 5 m before and after, thereby implementing masking stably.

The refresh arbitration circuit 140 includes a latch unit 210 and an output unit 250 as shown in FIG. The refresh arbitration circuit 140 generates a refresh request signal QINIT for performing a refresh operation. The refresh request signal QINIT is activated in response to the oscillation signal VOSC, and the normal operation indication signal CEN1 is "high", while the normal operation is performed, in response to the oscillation signal VOSC. I never do that. In other words, when the normal operation indication signal CEN1 is inactive in the low state, the refresh arbitration circuit 140 activates the refresh request signal QINIT in response to the oscillation signal VOSC. On the other hand, when the normal operation indication signal CEN1 is activated "high", the refresh arbitration circuit 140 stops responding to the oscillation signal VOSC.

Here, the latch unit 210 may include a first inverter 212, first and second NOR gates 214 and 216 cross-coupled with each other, a second inverter 218, A third inverter 220 and a precharge part 222 are provided.

The first inverter 212 inverts and outputs a logic state of the normal operation display signal CEN1 input from the normal operation signal activation circuit 130. The first NOR gate 214 receives the output signal of the first inverter 212 as one input signal, and the second NOR gate 216 receives the oscillation signal VOSC as one input signal. . The output signal of each of the first and second Noah gates 214 and 216 becomes the other input signal of each of the second and first Noah gates 216 and 214. The second inverter 218 inverts the logic state of the output signal of the first NOR gate 214 and outputs the first output signal VLA1 of the latch unit 210. The third inverter 220 inverts the logic state of the output signal of the second NOR gate 216 and outputs the second output signal VLA2 of the latch unit 210. The precharge unit 222 precharges the output signal of the first NOR gate 214 to a "high" state when the SRAM compatible memory device is initially driven. In the present embodiment, the precharge unit 222 is implemented as a PMOS transistor whose source is connected to the power supply voltage VDD.

Referring to the operation state of the latch unit 210 configured as described above in detail as follows. When the normal operation display signal CEN1 is in a low state, the first inverter 212 inverts the logic state of the normal operation display signal CEN1 to "high" so that the first NOR gate 214 is inverted. Will output Accordingly, the output signal of the first NOR gate 214 is "low" and is input to the second NOR gate 216 and the second inverter 218. Therefore, the first output signal VLA1 of the latch unit 210 output through the second inverter 218 is "high".

In this case, the second NOR gate 216 alternately outputs signals of the "low" and "high" states in response to the oscillation signal VOSC that periodically oscillates. That is, when the oscillation signal VOSC is in the "high" state, the output signal of the second NOR gate 216 is "low" and is input to the first NOR gate 214 and the third inverter 218. do. At this time, the second output signal VLA2 of the latch unit 210 output through the third inverter 220 is "high".

Subsequently, when the oscillation signal VOSC transitions to the "low" state, the output signal of the second NOR gate 216 transitions to the "high" state, and the first NOR gate 214 and the third inverter ( 220). At this time, the second output signal VLA2 of the latch unit 210 output through the third inverter 220 is "low".

As described above, when the normal operation display signal CEN1 is "low" and inactive, the first output signal VLA1 of the latch unit 210 remains in the "high" state, but the second output signal ( The logic state of VLA2 is varied in response to the oscillation signal VOSC.

On the other hand, when the normal operation activation circuit 130 activates the normal operation display signal CEN1 to "high", the first inverter 212 sets the logic state of the normal operation display signal CEN1 to "low". The inversion is input to the first noah gate 214. In this case, the logic states of the output signals of the first and second NOR gates 214 and 216 are latched "high" and "low", respectively.

In other words, a signal of a "high" state is inputted to an input terminal of the second noah gate 216 cross-coupled to the output side of the first noble gate 214, and the oscillation signal VOSC is "low". Assume that "state. Then, the output signal of the second NOR gate 216 is "low" and is input to the first NOR gate 214 and the third inverter 220. At this time, the second output signal VLA2 of the latch unit 210 output through the third inverter 220 is "high". The first NOR gate 214 outputs a signal of a "high" state. Therefore, the logic state of the first output signal VLA1 of the latch unit 210 output through the second inverter 218 is " low &quot; opposite to the logic state of the second output signal VLA2.

That is, the output signal of the second NOR gate 216 is " low " regardless of the logic state of the oscillation signal VOSC. Therefore, the second output signal VLA2 of the latch unit 210 output through the third inverter 220 becomes "high". In addition, the logic state of the output signal of the first NOR gate 214 to which the output signal of the second NOR gate 216 is input is "high". Therefore, the first output signal VLA1 of the latch unit 210 output through the second inverter 218 becomes "low".

When the normal operation display signal CEN1 is activated as described above, the first and second output signals VLA1 and VLA2 of the latch unit 210 are opposite to each other regardless of the oscillation signal VOSC. Latches to a logical state. In addition, the first and second output signals VLA1 and VLA2 of the latch unit 210 latched as described above are released when the normal operation display signal CEN1 transitions to the “low” state. Thereafter, the second output signal VLA2 responds to the oscillation signal VOSC as described above.

The output unit 250 includes a NAND gate 252 and a fourth inverter 254.

The NAND gate 252 receives the first and second output signals VLA1 and VLA2 of the latch unit 210, and logically multiplies the first and second output signals VLA1 and VLA2 by the logical AND. Invert the result and print it out. The fourth inverter 254 inverts the logic state of the signal output from the NAND gate 252 and outputs it as the refresh request signal QINIT.

Accordingly, when the normal operation display signal CEN1 is inactive in the low state, the first output signal VLA1 of the latch unit 210 maintains the high state and the second output signal VLA2. Since the variable varies in response to the oscillation signal VOSC, the output unit 250 outputs the refresh request signal QINIT according to the logic state of the second output signal VLA2. In other words, when the normal operation indication signal CEN1 is inactive in the low state, the refresh arbitration circuit 140 outputs the refresh request signal QINIT in response to the oscillation signal VOSC.

On the other hand, when the normal operation display signal CEN1 is activated as "high", the first and second output signals VLA1 and VLA2 of the latch unit 210 are in the logic state of the oscillation signal VOSC. The output unit 210 outputs only a signal of a "low" state because it maintains a constant logic state regardless. In other words, when the normal operation indication signal CEN1 is activated "high", the refresh arbitration circuit 140 may not respond to the oscillation signal VOSC.

The refresh driving circuit 150 generates a refresh driving signal SRFP while the refresh request signal QINIT output from the refresh arbitration circuit 140 is activated "high" to provide circuits for driving a refresh operation. do. Circuits for driving the refresh operation are well known techniques, and thus detailed description thereof will be omitted.

An operation state of the SRAM compatible memory device according to the present invention configured as described above will be described with reference to FIG. 3.

First, when the normal operation display signal CEN1 is in an inactive state "low", the refresh request signal QINIT is periodically transitioned in response to the oscillation signal VOSC.

In this case, when the external address select signal ADRS is input to the pulse generator 120 while the external chip select signal / CS and the write enable signal / WE are activated, the pulse generator 120 The normal operation control signal PPZ is generated as a pulse and provided to the normal operation activation circuit 130.

Then, the normal operation activation circuit 130 activates the normal operation signal CEN and the normal operation display signal CEN1 to "high". In this case, the refresh arbitration circuit 140 outputs the refresh request signal QINIT in the "low" state regardless of the oscillation signal VOSC. That is, the refresh arbitration circuit 140 does not respond to the oscillation signal VOSC, and thus does not generate the refresh request signal QINIT.

Accordingly, since the SRAM compatible memory device of the present invention blocks activation of the refresh request signal QINIT as soon as the normal operation control signal PPZ is generated, the normal operation can be performed immediately.

Meanwhile, the SRAM compatible memory device capable of controlling the refresh operation according to the present invention is not limited to the above-described first embodiment, and various modifications and substitutions may be made in connection with the control of the refresh operation as described below. .

Next, an SRAM compatible memory device capable of controlling the refresh operation according to the second embodiment of the present invention will be described in detail with reference to FIGS. 4 to 7.

4 is a block diagram conceptually illustrating an SRAM compatible memory device using DRAM cells according to a second embodiment of the present invention. Referring to FIG. 4, an SRAM compatible memory device according to a second embodiment of the present invention may include an oscillation circuit 410, a pulse generator 420, a normal operation signal activation circuit 430, a refresh arbitration circuit 440, and a refresh. A forced execution signal 450, a logic sum circuit 460 and a refresh driving circuit 470 are provided.

Since the oscillation circuit 410, the pulse generator 420, the normal operation signal activation circuit 430, and the refresh driving circuit 470 are almost identical in configuration and operation to the above-described first embodiment, a detailed description thereof will be provided. Omit. However, in the present embodiment, the oscillation signal VOSC and the normal operation indication signal CEN1 generated by the oscillation circuit 410 and the normal operation signal activation circuit 430, respectively, are not only refresh arbitration circuit 440, but also refresh force execution. Also provided as circuit 450.

In addition, the refresh arbitration circuit 440 is also substantially the same as the first embodiment described above, a detailed description thereof will be omitted. That is, the refresh arbitration circuit 440 according to the present embodiment includes a first inverter 512, first and second Noah gates 514 and 516 cross-coupled with each other, and a second inverter as shown in FIG. 518, a latch unit 510 having a third inverter 520 and a first precharge unit 522, and an output unit 550 having a first NAND gate 552 and a fourth inverter 554. Is implemented. However, in the present embodiment, the refresh arbitration circuit 440 generates the pre-refresh request signal PRE-QINIT instead of the refresh request signal QINIT and provides it to the logic sum circuit 470.

When the refresh forced execution circuit 450 activates the refresh forced execution request signal QI, the refresh request signal QINIT is applied to the oscillation signal VOSC, despite the activation of the normal operation display signal CEN1. Generates a refresh forced signal QIRFP that controls to respond to the &lt; RTI ID = 0.0 &gt; The refresh forced execution request signal QI is a signal that is activated during a normal operation that continues for a predetermined time and is inactivated when the refresh operation is started, and any one or two or more of the internal signals of the SRAM compatible memory device of the present invention. It can be generated by a combination of signals. Preferably, the refresh forced execution request signal QI is an inversion signal of the refresh driving signal SRFP. The refresh forced execution circuit 450 is implemented similarly to the refresh arbitration circuit 440.

In other words, as shown in FIG. 6, the refresh forced execution circuit 450 may specifically include third and fourth quinoa gates 610 and 620 cross-coupled with each other, and fifth and sixth inverters 630. 640, a second precharge unit 650, a second NAND gate 660, and a seventh inverter 670. Here, the third NOR gate 610 receives the normal operation display signal CEN1 output from the normal operation activation circuit 430 as one input signal, and the fourth NOR gate 620 is the oscillation circuit 410. The oscillation signal (VOSC) outputted from) is received as one input signal. The output signal of each of the third and fourth NOR gates 610 and 620 is the other input signal of each of the fourth and third NOR gates 620 and 610. The fifth inverter 630 inverts and outputs the logic state of the output signal of the third NOR gate 610, and the sixth inverter 640 inverts the logic state of the output signal of the fourth NOR gate 620. And print it out. The second precharge unit 650 precharges the output signal of the third NOR gate 610 to a "high" state during power-up of the SRAM compatible memory device according to the present invention.

The second NAND gate 660 receives and outputs the signals output from the fifth and sixth inverters 630 and 640 and the refresh force execution request signal QI, and inverts the result of the AND. . The seventh inverter 670 inverts the logic state of the signal output from the second NAND gate 660 and outputs it as the refresh forced execution signal QIRFP.

The operation state of the refresh forced execution circuit 450 configured as described above will be described in detail as follows.

First, when the refresh forced execution request signal QI is deactivated to "low", the refresh forced execution signal QIRFP is fixed to "low". Accordingly, the refresh forced execution circuit 450 may not drive the refresh operation. However, when the refresh forced execution request signal QI is activated to " high ", even when the normal operation indication signal CEN1 is activated to " high ", the refresh forced execution signal QIRFP is an oscillation signal. Answer (VOSC).

When the normal operation display signal CEN1 is activated as “high”, the signal output through the fifth inverter 630 remains “high”, but the signal output through the sixth inverter 640. The logic state of is varied in response to the oscillation signal VOSC. Therefore, when the oscillation signal VOSC is "high", the second NAND gate 660 outputs a signal of the "low" state, and thus the refresh forced execution signal output through the seventh inverter 670. The logic state of QIRFP is " high. &Quot; When the oscillation signal VOSC is in the "low" state, the refresh forced execution signal QIRFP in the "low" state is output.

As illustrated in FIG. 7, the logic sum circuit 460 includes a fifth Noah gate 710 and an eighth inverter 720. The fifth NOR gate 710 logically sums the pre-refresh request signal PRE-QINIT outputted from the refresh arbitration circuit 440 and the refresh forced execution signal QIRFP outputted from the refresh forced execution circuit 450. The OR result is inverted and output. The eighth inverter 720 inverts the signal output from the fifth NOR gate 710 and outputs it as a refresh request signal QINIT. That is, the refresh request signal QINIT responds to the pre-refresh request signal PRE-QINIT or the refresh force execution request signal QIRFP.

Therefore, according to the second embodiment of the present invention, the refresh request signal QINIT drives the refresh operation in response as follows.

1) Respond to the pre-refresh request signal PRE-QINIT during a predetermined time period during which the normal operation display signal CEN1 is activated.

2) Respond to the refresh forced execution signal QIRFP during a predetermined time period during which the normal operation display signal CEN1 is deactivated.

Although the present invention has been described with reference to the first and second embodiments shown in the drawings, this is merely exemplary, and various modifications and equivalent other embodiments may be made by those skilled in the art. Will understand. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the above-described SRAM compatible memory device of the present invention, even during the refresh operation, the normal operation is immediately performed in response to a normal operation command input from the outside, and thus the data processing speed is higher than that of the conventional SRAM compatible memory device. Can greatly improve.

In addition, when the normal operation is long, the SRAM compatible memory device of the present invention may activate the refresh force execution signal so that the refresh operation may be performed immediately after the normal operation is terminated.

Claims (7)

An SRAM compatible memory device having a DRAM cell for which a refresh operation for preserving stored data is required within a predetermined refresh period, and performing an SRAM interface, comprising: The refresh operation of the DRAM cell at each refresh cycle, the refresh operation is suspended while performing a normal operation for input and output data to / from outside. The memory device of claim 1, wherein the SRAM compatible memory device comprises: An oscillation circuit for generating an oscillation signal oscillated at a predetermined oscillation period; A normal operation signal activation circuit for receiving a predetermined control signal input from the outside and activating a normal operation display signal representing the normal operation; And A refresh arbitration circuit for activating a refresh request signal for performing the refresh operation in response to the oscillation signal, and stopping the activation of the refresh request signal for a predetermined period when the normal operation display signal is activated; SRAM compatible memory device comprising a. The method of claim 2, wherein the refresh arbitration circuit The first output signal latched in an inactive state by the normal operation display signal and the oscillation signal during the normal operation, and during the normal operation, the response to the oscillation signal is changed by the normal operation display signal. A latch unit generating a second output signal to be stopped; And And an output unit enabled by activation of the first output signal of the latch unit and ultimately outputting the refresh request signal in response to the second output signal. The method of claim 3, wherein the latch unit A first inverter for inverting a logic state of the normal operation display signal; First and second NOR gates each receiving an output signal of the first inverter and the oscillation signal as input signals and cross-coupled with each other; A second inverter inverting a logic state of an output signal of the first NOR gate and providing the inverted logic state to the output unit; And A third inverter for inverting a logic state of an output signal of the second NOR gate to the output unit SRAM compatible memory device comprising a. The method of claim 4, wherein the latch unit And a precharge unit configured to precharge the output signal of the first NOR gate when the SRAM compatible memory device is initially driven. The memory device of claim 2, wherein the SRAM compatible memory device comprises: And a refresh driving circuit configured to generate a refresh driving signal activated in the refresh period in response to a refresh request signal activated by the refresh arbitration circuit. An SRAM compatible memory device having a DRAM cell for which a refresh operation for preserving stored data is required within a predetermined refresh period, and performing an SRAM interface, comprising: An oscillation circuit for generating an oscillation signal oscillated at a predetermined oscillation period; A normal operation signal activation circuit for activating a normal operation display signal indicating a normal operation of receiving a predetermined control signal input from the outside and inputting / outputting data to / from the outside; A refresh arbitration circuit activating a refresh request signal for performing the refresh operation in response to the oscillation signal, and stopping the activation of the refresh request signal for a predetermined period when the normal operation display signal is activated; A refresh forced execution circuit for controlling the refresh request signal to respond to the oscillation signal despite the activation of the normal operation display signal; And A logic sum circuit for outputting the refresh request signal by ORing the output signals of the refresh arbitration circuit and the refresh forced execution circuit; SRAM compatible memory device comprising a.