KR20020087904A - Joystick use video games - Google Patents

Abstract

PURPOSE: A joystick device for a video game is provided to input data as well as the video game and to replace a keyboard through the simple program change by converting a key signal of the joystick into the same signal as the keyboard. CONSTITUTION: A key input part(100) includes a joystick(1000) performing a movement key, a plurality of buttons for inputting a specific signal, and a control key for operating the plural buttons as a dualized key. A display part(200) includes a plurality of LEDs visually displaying an operation of the control key and a power supply state. A signal converter(300) converts the signal outputted from the key input part into a code recognizable to a computer(3000) and outputs the code. A signal selector(400) transmits the code data outputted from the signal converting part and the keyboard(2000) to the computer by selecting the code data according to a priority.

Description

Joystick device for video games {Joystick use video games}

The present invention relates to a joystick (joystick) device for video games, in particular can be combined with a general computer keyboard to transmit the keyboard signal to the computer main body, and converts the key signal provided in the joystick device to the same signal as the keyboard to the computer main body The present invention relates to a video game joystick device that allows data input as well as video games, and can be used as a keyboard substitute by a simple program change.

Conventional joystick devices have been provided with a joystick and a few buttons, connected to a computer main body to move a character in the game with the joystick, and have pressed a previously reserved button to perform a specific operation.

Recently, however, due to the rapid development of computer technology, game programs that can be implemented in home game consoles have also made great progress. In particular, the strategy simulation game has been developed to provide an environment in which a large number of people can be connected by a network and play a game. While the existing game is a confrontation structure between a person and a computer, the recent game has been a confrontation structure between a person and a user, and users are more interested in the game. However, such a strategy simulation game is difficult to operate with only a few preset buttons. In many situations, the use of shortcut keys has become necessary, and in particular, reservation keys that users can specify arbitrarily during the game have become essential.

In addition, the existing joystick has a disadvantage in that it does not adequately control a strategy simulation game that requires selection and positioning of each character in the game.

In addition, even if a keyboard and a mouse for a computer is installed in the existing joystick device, because the input device standard and the joystick device specifications are different from each other, the computer main body does not recognize the signals of the keyboard and mouse provided in the joystick device.

Accordingly, the present invention has been proposed to solve various problems occurring in the conventional joystick device as described above,

An object of the present invention is to combine the general computer keyboard and transmit the keyboard signal to the computer main body, by converting the key signal provided in the joystick device to the same signal as the keyboard to be transmitted to the computer main body to input data as well as video games It is possible to provide a joystick device for a video game that can be used as a substitute for a keyboard.

"Video game joystick device" according to the present invention for achieving the above object,

Before and after. A key input unit including a joystick serving as a left and right moving key, a plurality of buttons for inputting a specific signal, and a control key for operating the plurality of buttons as a dual key;

A display unit including a plurality of light emitting diodes for visually displaying whether the control key is operated and a power supply state;

A signal converter converting the signal output from the key input unit into a code that can be recognized by a computer and outputting the converted code;

And a signal selector configured to select the code data output from the signal converter and the code data output from the keyboard according to priority and transmit the selected code data to the computer main body.

In the above, the signal selection unit,

A first buffer for buffering serial data output from the keyboard;

Second to fifth buffers each buffering signals generated when a plurality of buttons are operated in the key input unit;

A sixth buffer which buffers the input data selection signal and outputs the selection signal for selecting one of the signals output from the keyboard and the signal converter;

A seventh and eighth buffers for buffering a signal corresponding to the control key of the key input unit;

A first and gate for ANDing the output signals of the seventh and eighth buffers;

First to eighth multiplexers for selecting and outputting one of output data of the first buffer, output data of the second to fifth buffers, and output data of the first and gates according to the output signal of the sixth buffer; ,

A first inverter for phase inverting output data of the first to eighth multiplexers,

A ninth buffer buffering the output data of the first inverter and transmitting the buffered data to the computer main body;

A tenth buffer for buffering the input clock signal CK,

The first to fourth data processing units are configured to process an input signal in synchronization with a clock output from the tenth buffer.

The first data processing unit,

A buffer to buffer the incoming data,

An inverter for phase reversing the operation control signal output from the third data processor;

A first flip-flop whose operation is controlled according to an output signal of the inverter and which latches data of the buffer in synchronization with a clock output from the tenth buffer;

A second flip-flop for latching output data of the first flip-flop in synchronization with the clock;

A first and gate for ANDing the output data of the second flip flop and the output data of the first flip flop;

A second and gate for performing an AND operation on the phase inverted signal of the first and gate output signals, the signal output from the third data processor, and the signal inverted phase of the signal output from the seventh buffer;

And a tri-state buffer configured to receive the output signal of the second and gate as an enable signal and output a ground signal GND.

The second data processing unit,

A buffer to buffer the incoming data,

An inverter for phase reversing the operation control signal output from the fourth data processor;

A first flip-flop whose operation is controlled according to an output signal of the inverter and which latches data of the buffer in synchronization with a clock output from the tenth buffer;

A second flip-flop for latching output data of the first flip-flop in synchronization with the clock;

A first and gate for ANDing the output data of the second flip flop and the output data of the first flip flop;

A second and gate for ANDing the phase inversion signal of the output signal of the first and gate and the signal output from the fourth data processor;

An orifice for ORing the signal output from the seventh buffer and the output signal of the second and gate;

The output signal of the OA gate is applied as an enable signal and is characterized by consisting of a three-state buffer for outputting a ground signal (GND).

The third data processing unit,

A buffer to buffer the incoming data,

An inverter for phase reversing the operation control signal output from the first data processor;

A first flip-flop whose operation is controlled according to an output signal of the inverter and which latches data of the buffer in synchronization with a clock output from the tenth buffer;

A second flip-flop for latching output data of the first flip-flop in synchronization with the clock;

A first and gate for ANDing the output data of the second flip flop and the output data of the first flip flop;

A second AND gate for performing an AND operation on the phase inverted signal of the first and gate output signals, the signal output from the first data processor, and the signal inverted phase of the signal output from the seventh buffer;

And a tri-state buffer configured to receive the output signal of the second and gate as an enable signal and output a ground signal GND.

The fourth data processing unit,

A first buffer for buffering the input data,

An inverter for phase reversing the operation control signal output from the second data processor;

A first flip-flop whose operation is controlled according to an output signal of the inverter and which latches data of the first buffer in synchronization with a clock output from the tenth buffer;

A second flip-flop for latching output data of the first flip-flop in synchronization with the clock;

A first and gate for ANDing the output data of the second flip flop and the output data of the first flip flop;

A second AND gate for performing an AND operation on the phase inverted signal of the first and gate output signals, the signal output from the second data processor, and the signal inverted phase of the signal output from the seventh buffer;

A tri-state buffer receiving the output signal of the second and gate as an enable signal and outputting a ground signal GND;

And a second buffer configured to buffer and output the output data of the first buffer.

1 is an external view showing a key configuration of a joystick device for a video game according to the present invention;

2 is a block diagram showing the configuration of a joystick device for a video game according to the present invention;

3A and 3B are circuit diagrams illustrating an exemplary embodiment of the signal selector of FIG. 2;

4 is a view showing a corresponding key of the keyboard corresponding to the key of the joystick device for video games in the present invention.

<Explanation of symbols for the main parts of the drawings>

100 ..... key input

200 ..... Display

300 ..... Signal converter

400 ..... signal selector

1000 ..... joystick device

2000 ..... keyboard

3000 ..... computer body

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

1 is an external view showing a key configuration of a joystick device for a video game according to the present invention.

Reference numeral 1000 denotes a joystick device, and reference numeral 101 denotes before and after. Joysticks serve as left and right navigation keys, reference numerals 102 to 111 denote a plurality of buttons for inputting a specific signal, and reference numerals 112 to 119 denote control keys for operating the plurality of buttons as double keys. Reference numerals 201 to 209 denote a plurality of light emitting diodes that visually display whether power is supplied and whether the control key is operated.

2 is a block diagram showing the configuration of a joystick device for a video game according to the present invention.

Where reference numeral 100 is before and after. Joystick 101 serving as left and right movement keys, a plurality of buttons 102 to 111 for inputting a specific signal, and a control key 112 to 119 for operating the plurality of buttons 102 to 111 as dual keys Reference numeral 200 denotes a display unit including a plurality of light emitting diodes 201 to 209 for visually displaying whether the control keys 112 to 119 are operated and a power supply state. Reference numeral 300 denotes a signal converter for converting a signal output from the key input unit 100 into a code that can be recognized by a computer, and reference numeral 400 denotes a code data and a keyboard (outputted from the signal converter 300). A signal selection unit for selecting the code data output from 2000 according to the priority and transmitting the code data to the computer main body 3000 is shown.

The operation of the video game joystick apparatus according to the present invention configured as described above will be described in detail with reference to FIGS. 3A / B and FIG. 4.

First, the user connects the computer keyboard 2000 to the connector implemented in the joystick device 1000, and connects the joystick device 1000 to a predetermined position of the computer main body 3000 with a cable.

Here, the keyboard 2000 and the joystick device 1000 use the PS2 interface method, and the joystick device 1000 and the computer main body 3000 also use the PS2 interface method. In addition, the joystick apparatus 1000 receives driving power from the computer main body 3000.

When power is supplied, the joystick device 1000 is initialized, and when a user operates the joystick 101 provided in the key input unit 100 or manipulates a plurality of buttons 102 to 111, a signal corresponding thereto is converted into a signal converter. Entered at 300. In this case, the plurality of buttons 102 to 111 generate two signals corresponding to whether the control keys 201 to 209 are operated. When the control keys 201 to 209 are operated, the specific light emitting diodes 201 to 209 in the display unit 200 emit light to allow the user to easily recognize the operation of the dual key.

On the other hand, when the control keys 201 to 209 are not operated (off state), the signals initially set of the plurality of buttons 102 to 111 are generated and transmitted to the signal conversion unit 300. When the control keys 201 to 209 are operated (on), a set signal is generated and transmitted to the signal converter 300 unlike the initial setting state of the plurality of buttons 102 to 111.

Then, the signal transmission unit 300 converts the input signal into corresponding code data used in the computer and transmits the converted signal to the signal selection unit 400.

4 is a diagram illustrating a correlation between various keys provided in the joystick device and a computer keyboard.

Although the correlation between the joystick device and the computer keyboard implemented in the present invention is shown in FIG. 4, such correlation may have many changes by simple program change. For example, the button 102 of the joystick device 1000 is initially set to A (which is converted to a Ctrl signal when the control key is operated), but can be changed to a code value of N for the convenience and efficiency of the game. .

Next, the signal selector 400 selects one of the code data transmitted from the signal converter 300 and the code data transmitted from the keyboard 2000 and transmits the selected signal to the computer main body 3000. In this case, the priority of the output data of the signal converter 300 is high. That is, when the keys of the joystick device and the buttons of the keyboard are pressed at the same time, the signal of the joystick device is transmitted to the computer main body. However, when only the keyboard is operated without the joystick device being operated, the signal of the keyboard is transmitted to the computer body as it is.

3A and 3B are circuit diagrams illustrating an exemplary embodiment of the signal selector.

As shown in the figure, a signal is generated when the first buffer 401 buffers the serial data K [7: 0] output from the keyboard 2000 and a plurality of buttons in the key input unit 100. Among the signals output from the keyboard 2000 and the signal converter 300 after buffering the second to fifth buffers 402 to 405 that buffer each of the KXY0 to KXY3 and the input data selection signal DEC2. Sixth buffer 406 outputting the selection signal S0 for selecting one, and seventh and eighth buffers 407 buffering signals DEC0 to DEC1 corresponding to the control keys of the key input unit 100. 408, the first and fourth gates 409 for ANDing the output signals of the seventh and eighth buffers 407 to 408, and the first buffer 401 according to the output signals of the sixth buffer 406. ) And select one of the output data of the second to fifth buffers (402 to 405) and the output data of the first and gate 409 First to eighth multiplexers 410 to 417, an inverter 418 for phase inverting output data of the first to eighth multiplexers 410 to 417, and output data D [7] of the inverter 418. : 0]) buffers the ninth buffer 419 for transmitting to the computer main body 3000, the tenth buffer 420 for buffering the input clock signal CK, and the tenth buffer 420. The first to fourth data processing units 430, 440, 450, and 460 process the input signal IOPAD in synchronization with the output clock.

The first data processor 430 may include a buffer 431 for buffering input data KD, an inverter 432 for phase reversing an operation control signal output from the third data processor 450, and The operation is controlled according to the output signal of the inverter 432, and the first flip-flop 433 latches the data KDI of the buffer 431 in synchronization with the clock CK output from the tenth buffer 420. ), A second flip flop 434 for latching output data of the first flip flop 433 in synchronization with the clock CK, output data of the second flip flop 434, and the first flip. A first inverted gate 435 for multiplying the output data of the flop 433, a phase inverted signal for output from the first and gate 435, and a signal output from the third data processor 450; A second and gate 436 for performing a logical AND on a signal obtained by phase-inverting the signal output from the seventh buffer 407, and the second Being applied to the output signal of the de-gate 436 to the enable signal (E) consists of a tri-state buffer 437 which outputs a signal ground (GND).

The second data processor 440 may include a buffer 441 for buffering input data K0, an inverter 442 for inverting a phase of an operation control signal output from the fourth data processor 460, and A first flip-flop 443 which operates according to an output signal of the inverter 442 and latches data KCI of the buffer 441 in synchronization with a clock output from the tenth buffer 409; A second flip-flop 444 for latching output data of the first flip-flop 443 in synchronization with the clock, an output data of the second flip-flop 444 and an output of the first flip-flop 443 The first and gate 445 for ANDing the data, and the second and gate 446 for ANDing the output signal of the first and gate 445 and the phase inversion signal of the signal output from the fourth data processing unit 460. ) And a signal output from the seventh buffer 407 and an output signal of the second and gate 446. The sum of the orifice 447 and the three-state buffer 448 is applied to the output signal of the oragate 447 as the enable signal (E) and outputs a ground signal (GND).

In addition, the third data processor 450 may include a buffer 451 for buffering input data, an inverter 452 for inverting a phase of an operation control signal output from the first data processor 430, and the inverter ( An operation is controlled according to the output signal of 452, and the first flip-flop 453 latches the data MDI of the buffer 451 in synchronization with the clock CK output from the tenth buffer 420. A second flip-flop 454 for latching output data of the first flip-flop 453 in synchronization with the clock CK, the output data of the second flip-flop 454, and the first flip-flop ( A first inverted gate 455 for multiplying the output data of the 453, a phase inverted signal of the output signal of the first and gate 455, and a signal output from the first data processor 430; A second and gate 456 for performing an AND operation on the signal in which the signal output from the buffer 407 is inverted in phase; 2 being applied to the enable signal (E) an output signal of the AND gate 456, consists of a tri-state buffer 457 which outputs a signal ground (GND).

In addition, the fourth data processor 460 may include a first buffer 461 for buffering input data MC, and an inverter 462 for inverting phase of an operation control signal output from the first data processor 430. And a first flip-flop whose operation is controlled according to the output signal of the inverter 462, and latching data of the first buffer 461 in synchronization with the clock CK output from the tenth buffer 420. 463, a second flip-flop 464 that latches output data of the first flip-flop 463 in synchronization with the clock CK, output data of the second flip-flop 464, and the second data; The first and second gates 464 logically multiplying the output data of the first flip-flop 463, and the signals in which the output signals of the first and gates 464 and the signals output from the second data processing unit 463 are inverted in phase. And a second AND gate 466 for performing AND on the signal obtained by phase-inverting the signal output from the seventh buffer 407, The tri-state buffer 467 for receiving the output signal of the second and gate 466 as the enable signal E and outputting the ground signal GND, and buffers the output data of the first buffer 461. The second buffer 468 is configured to output MINT.

The operation of the signal selector 400 configured as described above will be described in more detail as follows.

First, the first buffer 401 inputs the first to eighth multiplexers 410 to 417 which buffer 8-bit serial data K [7: 0] output from the keyboard 2000.

Next, the second to fifth buffers 402 to 405 buffer the signals KXY0 to KXY3 generated when the plurality of buttons 102 to 111 in the key input unit 100 are manipulated, respectively. Transfer to multiplexer (410 ~ 413).

In addition, the sixth buffer 406 buffers the input data selection signal DEC2 and then selects the first signal as the selection signal S0 for selecting one of the signals output from the keyboard 2000 and the signal converter 300. To the eighth multiplexers 410 to 417.

The seventh and eighth buffers 407 to 408 buffer the signals DEC0 to DEC1 corresponding to the control keys of the key input unit 100, and the first and gate 409 stores the seventh and eighth buffers. The output signal of the buffers 407 to 408 is multiplied by the result, and the resultant signal is input to the fifth to eighth multiplexers 414 to 417.

Then, the first to eighth multiplexers 410 to 417 use the output signal of the sixth buffer 406 as a selection signal and output data D0 of the first buffer 401 and the second to fifth buffers ( One of the output data D1 of 402 to 405 and the output data D1 of the first and gate 409 is selected and output (DI0 to DI7).

Accordingly, the inverter 418 phase-inverts the output data of the first to eighth multiplexers 410 to 417, and the ninth buffer 419 outputs the output data D [7: of the first inverter 418. 0]) is buffered and transmitted to the computer main body 3000.

Next, the tenth buffer 420 buffers the input clock signal CK and inputs the synchronous clock to each flip-flop in the first to fourth data processing units 430, 440, 450, and 460. Accordingly, the first to fourth data processing units 430, 440, 450, and 460 process the input signal IOPAD in synchronization with the clock CK output from the tenth buffer 420.

First, the operation of the first data processing unit 430 will be described. The buffer 431 buffers the input data KD and inputs the data to the data terminal D of the first flip-flop 433. The operation control signal output from the third data processor 450 is inverted in phase and input to the control terminal PRE of the first flip-flop 433.

Accordingly, the first flip-flop 433 is controlled according to the output signal of the inverter 432, and the data of the buffer 431 is synchronized with the clock CK output from the tenth buffer 420. KDI is latched and input to the second flip-flop 4340 data terminal.

The second flip-flop 434 latches and outputs the output data of the first flip-flop 433 in synchronization with the clock CK.

In addition, the first and gate 435 is an AND of the output data of the second flip-flop 434 and the output data of the first flip-flop 433, the second and gate 436 is the first end Phase-invert the output signal of the gate 435, the signal output from the third data processing unit 450, and the phase-inverted signal output from the seventh buffer 407 to calculate the result signal. The control signal is output from the status buffer 437.

Accordingly, the tri-state buffer 437 receives the output signal of the second and gate 436 as the enable signal E and outputs a low signal (ground signal GND) input to the input terminal.

Meanwhile, the second data processor 440 buffers the data K0 input from the buffer 441 and inputs the data K0 to the data terminal D of the first flip-flop 443. The fourth data is output from the inverter 4420. The phase of the operation control signal output from the processor 460 is inverted and input to the control terminal of the first flip-flop 443.

The first flip-flop 443 is controlled according to an output signal of the inverter 442, and latches data KCI of the buffer 441 in synchronization with a clock output from the tenth buffer 409. To be output to the second flip-flop 444.

The second flip-flop 444 latches and outputs the output data of the first flip-flop 443 in synchronization with an input clock, and the first and gate 445 of the second flip-flop 444 The output data and the output data of the first flip-flop 443 are ANDed to output the result.

In addition, the second and gate 446 logically multiplies the phase inversion signal of the output signal of the first and gate 445 and the signal output from the fourth data processing unit 460, and the oragate 447 is The signal output from the seventh buffer 407 and the output signal of the second and gate 446 are ORed together, and the result is output as the enable signal E. FIG.

Then, the tri-state buffer 448 receives the output signal of the OR gate 447 as the enable signal E and outputs a low signal (ground signal GND) input to the input terminal.

In addition, the third data processing unit 450 buffers the data input from the buffer 451 and inputs the data to the data terminal of the first flip-flop 453. The first data processing unit 430 is input from the inverter 452. The phase of the operation control signal output from the inverted phase is input to the control terminal of the first flip-flop 453.

In addition, the first flip-flop 453 is controlled according to the output signal of the inverter 452, and the data MDI of the buffer 451 in synchronization with the clock CK output from the tenth buffer 420. ) Is input to the data terminal of the second flip-flop 454.

The second flip-flop 454 latches and outputs the output data of the first flip-flop 453 in synchronization with the clock CK, and the first and gate 455 receives the second flip-flop 454. ) And the output data of the first flip-flop 453 and the result signal is input to one input terminal of the second and gate (456).

The second and gate 456 phase inverts the output signal of the first and gate 455 and the signal output from the first data processor 430 and the signal output from the seventh buffer 407. Is multiplied by the phase-inverted signal, and the resultant signal is transmitted to the tri-state buffer 457 as an enable signal (E).

The tri-state buffer 457 receives the output signal of the second and gate 456 as an enable signal E and outputs a low signal (ground signal GND).

In addition, the fourth data processor 460 buffers the data MC input from the first buffer 461 and inputs the data to the data terminal of the first flip-flop 463. The operation control signal output from the data processor 430 is inverted in phase and input to the control terminal of the first flip-flop 463.

The first flip-flop 463 is controlled according to the output signal of the inverter 462, and the data of the first buffer 461 is synchronized with the clock CK output from the tenth buffer 420. Is latched and input to the data terminal of the second flip-flop 464.

The second flip-flop 464 latches and outputs the output data of the first flip-flop 463 in synchronization with the clock CK, and the first and gate 465 receives the second flip-flop 464. ) And the output data of the first flip-flop 463 and the result signal is input to one input terminal of the second and gate (466).

The second and gate 466 phase inverts an output signal of the first and gate 464 and a signal output from the second data processor 463 and a signal output from the seventh buffer 407. Is multiplied by the phase inverted signal, and the resultant signal is input to the tri-state buffer 467 as an enable signal E. The tri-state buffer 467 has a low signal (ground signal GND) according to the enable signal. Will print)).

In addition, the second buffer 468 buffers the output data of the first buffer 461 and outputs the data MINT.

According to the present invention described above, by combining the joystick device with a general computer keyboard, there is an effect that can transmit the keyboard signal to the computer main body.

In addition, by converting the key signal provided in the joystick device into the same signal as the keyboard to be transmitted to the computer main body, there is an effect that can input data as well as video games.

In addition, a simple program change can be used to input data instead of the keyboard.

Claims (6)

In joystick device, Before and after. A key input unit including a joystick serving as left and right navigation keys, at least two buttons for inputting a specific signal, and at least two control keys for operating the at least two buttons as a dual key; A display unit including at least two light emitting diodes for visually displaying whether the at least two control keys are operated and a power supply state; A signal converter converting the signal output from the key input unit into a code that can be recognized by a computer and outputting the converted code; And a signal selector for selecting the code data output from the signal converter and the code data output from the keyboard according to priority and transmitting the selected code data to the computer main body. The method of claim 1, wherein the signal selector, A first buffer 401 for buffering serial data K [7: 0] output from the keyboard and a signal KXY0 to KXY3 generated when a plurality of buttons are operated in the key input unit 100 are respectively buffered. A selection signal S0 for selecting one of the signals output from the keyboard 2000 and the signal converter 300 after buffering the second to fifth buffers 402 to 405 and the input data selection signal DEC2. ) And a seventh and eighth buffers 407 to 408 which buffer the sixth buffer 406 outputted to the signal, the signals DEC0 to DEC1 corresponding to the control keys of the key input unit 100, and the seventh and eighth buffers. Output data of the first buffer 401 and the second to the second and fourth gates according to the first and fourth gates 409 and OR of the output signals of the eighth buffers 407 to 408, and the output signals of the sixth buffer 406. First to eighth multiplexers 410 for selecting and outputting one of the output data of the fifth buffers 402 to 405 and the output data of the first and gate 409. 417, the inverter 418 which phase-inverts the output data of the first to eighth multiplexers 410 to 417, and the output data D [7: 0] of the inverter 418 by buffering the A ninth buffer 419 transmitted to the computer main body 3000, a tenth buffer 420 buffering the input clock signal CK, and a clock output from the tenth buffer 420 Joystick device for a video game, characterized in that the first to fourth data processing unit (430, 440, 450, 460) for processing the signal (IOPAD). The method of claim 2, wherein the first data processing unit 430, A buffer 431 for buffering input data KD, an inverter 432 for phase reversing an operation control signal output from the third data processing unit 450, and an operation according to an output signal of the inverter 432 Is controlled, and the first flip-flop 433 latches the data KDI of the buffer 431 in synchronization with the clock CK output from the tenth buffer 420 and the clock CK. To multiply the second flip-flop 434 by latching the output data of the first flip-flop 433, the output data of the second flip-flop 434, and the output data of the first flip-flop 433. A phase inverted signal of the first and gate 435, the output signal of the first and gate 435, the signal output from the third data processing unit 450, and the signal output from the seventh buffer 407. And the output signal of the second and gate 436 and the output signal of the second and gate 436 Joystick device for a video game, characterized in that consisting of a three-state buffer (437) is applied to the enable signal (E) and outputs a low signal (ground signal (GND)). The method of claim 2, wherein the second data processing unit 440, A buffer 441 for buffering the input data K0, an inverter 442 for phase reversing the operation control signal output from the fourth data processing unit 460, and an operation according to the output signal of the inverter 442 Is controlled, a first flip-flop 443 which latches data KCI of the buffer 441 in synchronization with a clock output from the tenth buffer 409, and the first flip-flop in synchronization with the clock. A second flip-flop 444 for latching the output data of the 444, and a first and gate 445 for ANDing the output data of the second flip-flop 444 and the output data of the first flip-flop 443. ), A second and gate 446 for ANDing the output signal of the first and gate 445 and the phase inversion signal of the signal output from the fourth data processing unit 460, and the seventh buffer 407. An OR gate 447 for ORing the signal outputted from the output signal of the second and gate 446, and Iowa gate 447 being applied to the output signal to the enable signal (E) a video game joystick device, characterized in that consisting of tri-state buffer 448, which outputs a signal ground (GND) of the. The method of claim 2, wherein the third data processing unit 450, An operation is controlled according to a buffer 451 for buffering input data, an inverter 452 for inverting an operation control signal output from the first data processor 430, and an output signal of the inverter 452. A first flip-flop 453 which latches the data MDI of the buffer 451 in synchronization with the clock CK output from the tenth buffer 420, and the first flip-flop 453 in synchronization with the clock CK. A second flip-flop 454 for latching output data of the first flip-flop 453 and a first end for ANDing the output data of the second flip-flop 454 and the output data of the first flip-flop 453. Phase invert the gate 455, the output signal of the first and gate 455, the signal output from the first data processor 430, and the signal output from the seventh buffer 407. The second and gate 456, which is ANDed by the signal, and the output signal of the second and 456 A video game joystick device according to claim being applied to the enable signal (E) that is configured as a tri-state buffer 457, which outputs a low signal (GND). The method of claim 2, wherein the fourth data processing unit 460, A first buffer 461 for buffering input data MC, an inverter 462 for inverting a phase of an operation control signal output from the first data processor 430, and an output signal of the inverter 462. The operation is controlled according to the first flip-flop 463 which latches data of the first buffer 461 in synchronization with the clock CK output from the tenth buffer 420 and the clock CK. The second flip-flop 464 latches the output data of the first flip-flop 463 in synchronization with the output data of the second flip-flop 464 and the output data of the first flip-flop 463. The first and second multiplied by the first and gate 464, the output signal of the first and gate 464 and the signal output from the second data processing unit 463 and the signal output from the seventh buffer (407) A second and gate 466 for ANDing the signal obtained by inverting the phase of the signal, and an output signal of the second and gate 466. A tri-state buffer 467 that is applied as an enable signal E and outputs a ground signal GND, and a second buffer 468 that buffers and outputs the output data of the first buffer 461. Joystick device for video games, characterized in that configured.