KR20020071430A - Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same - Google Patents

Abstract

PURPOSE: An ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same are provided to increase mounting density of the semiconductor package and reduce thickness of the semiconductor package. CONSTITUTION: An upper semiconductor chip(120a) and a lower semiconductor chip(120b) are adhered to both sides of a chip adhering portion(512a) of a die pad(512) by using an adhesive(122). An edge portion(512b) of the die pad(512) is thicker than the chip adhering portion(512a). The edge portion(512b) of the die pad(512) is equal to an inner lead(516a) in thickness. The thickness of the chip adhering portion(512a) corresponds to 30 to 50 percents of the thickness of the edge portion(512b). An upper portion of the package body(526) is different from a lower portion of the package body(526) in thickness. The semiconductor chips(120a,120b) are electrically with an inner lead(516a) by a reverse bonding wire. The reverse bonding wire includes a ball boned on a surface of the inner lead(516a) and a stitch bonded with an electrode pad of the semiconductor chip(120). A bonding wire(530) connected with the upper semiconductor chip(120a) is shorter than a bonding wire(532) connected with the lower semiconductor chip(120b).

Description

Ultra-thin semiconductor package device having different thickness of die pad and leads, and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor assembly technology, and more particularly, to an ultra-thin semiconductor package, a method of manufacturing the same, and an electronic device including an ultra-thin package device, in which the thickness of a die pad and a lead is made thin. will be.

As is well known, semiconductor integrated circuit chips such as memory devices are assembled into packages and used on circuit boards of various electronic devices. Such semiconductor package devices use a medium for electrical connection and physical bonding with a circuit board, and a lead frame is the most common medium.

1 is a cross-sectional view of an IC device in which semiconductor chips are mounted on both surfaces of a lead frame in order to increase chip mounting density of a semiconductor package device. A semiconductor package having such a structure is disclosed, for example, in Japanese Patent Laid-Open No. 62-147360.

Referring to FIG. 1, a conventional semiconductor package 10 of the related art has a lead frame 15 composed of a die pad 13 and a plurality of leads 14. The semiconductor integrated circuit chip 11 is physically bonded to the die pad 13 by an adhesive 12 and electrically connected to the lead 14 by a bonding wire 16. The semiconductor chip 11 and the bonding wire 16 and the like are sealed in a package molded body 17 formed of a molding resin such as epoxy and protected from the outside. The outer lead protruding outward of each lead 14, that is, out of the package molded body 17, is processed into a form suitable for mounting on an external circuit board (not shown).

The conventional semiconductor package 10 having the above structure is increasingly faced with the demand for thinning. This is in accordance with the trend toward miniaturization and thinning of various electronic devices themselves using the semiconductor package 10 mounted thereon. In particular, as illustrated in FIG. 1, two or more semiconductor chips 11 may be embedded to increase memory capacity. In the case of the semiconductor package 10, the need for thinning is further increased. In order to reduce the thickness of the semiconductor package, there is a method of reducing the thickness of the semiconductor chip and thinning the lead frame. The semiconductor chip can reduce the thickness to a range of 100 to 150 mu m by, for example, wafer back-lapping the wafer. If only one semiconductor chip of this thickness is used, the total thickness of the package element can be made 1 mm or less.

However, reducing the thickness of the semiconductor integrated circuit chip makes it difficult to handle the wafer and increases the possibility of wafer breakage or chip breakage. Considering that the main material for forming a wafer, that is, a semiconductor chip, is silicon having a weak hardness, this disadvantage is natural. In particular, considering the technical trend of increasing the diameter of the wafer to 12 inches to increase the yield of semiconductor products, there is a limit to reducing the thickness of the chip.

On the other hand, if the thickness of the lead frame is too thin, the lead frame may be easily broken during the assembly process, and the productivity of the assembly process may be reduced. At present, the thickness of the lead frame is known to be 100 µm in the limit in consideration of the handleability of the lead frame, the formability of the external lead, and the like.

It is also possible to use new assembly techniques, such as chip scale package (CSP) techniques, to reduce the thickness of the package elements, but this entails an increase in costs such as the need to replace plastic package assembly equipment already in use.

Accordingly, it is an object of the present invention to provide an ultra-thin semiconductor package having a thickness of 1.0 mm or less, preferably 0.7 mm or less or 0.5 mm or less, while increasing the mounting density of the semiconductor package and a method of manufacturing the same.

Another object of the present invention is to provide an ultra-thin semiconductor package and a method of manufacturing the same, which can be produced without additional investment by using the equipment used for manufacturing the existing plastic package as it is.

Still another object of the present invention is to provide an ultra-thin semiconductor package having excellent physical reliability and easy process management.

1 is a cross-sectional view showing a lead frame semiconductor package according to the prior art.

2 is a plan view illustrating an ultra-thin semiconductor package according to a first embodiment of the present invention.

3A is a cross-sectional view taken along the line III-III of FIG. 2, and FIG. 3B is a partial detail view of FIG. 3A.

4 is a cross-sectional view taken along the line IV-IV of FIG. 2.

5 is a cross-sectional view illustrating an ultra-thin semiconductor package according to a second embodiment of the present invention.

6 is a cross-sectional view illustrating an ultra-thin semiconductor package according to a third exemplary embodiment of the present invention.

7A and 7B are cross-sectional views illustrating an ultra-thin semiconductor package according to a fourth embodiment of the present invention.

8 is a cross-sectional view illustrating an ultra-thin semiconductor package according to a fifth embodiment of the present invention.

9 is a partial detailed view illustrating the structure of reverse wire bonding in the ultra-thin semiconductor package according to the present invention.

10 is a cross-sectional view illustrating an ultra-thin semiconductor package according to a sixth embodiment of the present invention.

11A and 11B are a plan view and a cross-sectional view illustrating an ultra-thin semiconductor package according to a seventh embodiment of the present invention.

12A to 12F are partial cross-sectional views illustrating a method of partially thinning a die pad of a lead frame in a process of manufacturing an ultra-thin semiconductor package device according to the present invention.

13A to 13I are partial cross-sectional views illustrating a manufacturing process of the ultra-thin semiconductor package device according to the present invention.

14A and 14B are plan views and cross-sectional views of an electronic device to which the ultra-thin semiconductor package device according to the present invention is applied.

15 is a cross-sectional view of a package device to which the thinning technology of the present invention is applied.

16 is a cross-sectional view of another package device to which the thinning technique of the present invention is applied.

<Explanation of symbols for the main parts of the drawings>

100, 200, 300, 400, 500, 550, 600, 650: semiconductor package

110, 210, 310, 410, 510, 610: lead frame

112, 212, 312, 412, 512, 612: die pad

114, 214, 414, 614: tie bar

116, 316, 416, 516, 616: leads

120: semiconductor integrated circuit chip

122: adhesive layer

124: bonding wire

126: package mold body

In order to achieve the above object, the present invention provides an ultra-thin semiconductor package in which the die pad constituting the lead frame is made partially thin. An ultra-thin semiconductor package according to the present invention includes a lead frame, which includes a plurality of leads disposed around the die pad. The die pad has a chip attachment portion to which a semiconductor chip is attached and an edge portion integrally formed with the chip attachment portion around the die attachment portion. The chip attachment portion is smaller in thickness (first thickness) than the thickness of the lead (second thickness). In addition, the ultra-thin semiconductor package of the present invention includes a semiconductor integrated circuit chip attached to a die pad, a bonding wire for electrically connecting respective leads to the semiconductor integrated circuit chip, a die pad, a semiconductor integrated circuit chip, and a bonding wire, respectively. And a package molded body for sealing the inside of the lid.

In particular, the ultra-thin semiconductor package of the present invention has a first thickness of the die pad less than the second thickness of the leads, preferably a thickness of the semiconductor package is 0.7 mm or less, and the first thickness of the die pad is the second thickness of the leads. 50% or less of, for example, 30 to 50% range.

The ultra-thin semiconductor package of the present invention may include two semiconductor integrated circuit chips each attached to both sides of the die pad, and may include at least two tie bars connected to the edge of the die pad and having a third thickness. have. The third thickness of the tie bar may be equal to the first thickness of the die pad chip attachment portion or the second thickness of the lead. The die pad edge is the same thickness as the chip attachment or the thickness of the lead. When the thickness of the die pad edge portion is larger than the die pad chip attachment portion so as to be equal to the thickness of the lead, the die pad is shaped like a 'c' lying on its side with the edge protruding.

When the protruding direction of the die pad edge portion is downward in the package molding thickness direction, it is preferable to bend the tie bar downward so that the die pad is located at the center of the package molding body. On the other hand, when the protrusion direction of the die pad edge part faces upward with respect to the package molded object thickness direction, it is preferable that the lead is arrange | positioned upwardly with respect to the thickness direction of the package molded object.

According to another embodiment of the present invention, the die pad includes a first die pad and a second die pad divided into at least two portions, each of which comprises a tie bar and a chip attachment portion. And an edge portion. In this embodiment, the tie bars, chip attachments and edges are the same thickness and thinner than the leads.

According to a second aspect of the present invention, there is provided a method of manufacturing an ultra-thin semiconductor package device, comprising the steps of: (A) preparing a lead frame in which a die pad, a tie bar, and a plurality of leads are formed; Defining an edge portion around the chip, (C) etching the chip attachment portion to form a predetermined thickness thinner than the lead, and (D) applying the semiconductor chip to the etched chip attachment portion. A die bonding step of attaching, (E) a wire bonding step of electrically connecting the semiconductor chip with a lead, and (F) molding the semiconductor chip, the bonding wire, and a portion of the lead to form a package forming body. . The amount removed in the chip attachment etching step is determined by the pressure and injection or deposition time of the etchant. Package forming body forming step is preferably a low temperature process, for example 170 ~ 175 ℃.

The ultra-thin semiconductor package manufacturing method according to the present invention comprises the steps of preparing a wafer having a plurality of semiconductor chips and having an active surface, attaching an adhesive layer on the bottom surface of the wafer and attaching an ultraviolet tape to the adhesive layer, Irradiating the ultraviolet tape with ultraviolet light to remove the adhesive force between the adhesive layer and the ultraviolet tape, cutting the wafer into a plurality of semiconductor chip units, and completely separating the cut semiconductor chip from the ultraviolet tape in a wafer state. The semiconductor chip may further include separating the semiconductor chip with the adhesive layer attached to the bottom surface of the semiconductor chip.

The die bonding step includes a primary die bonding step of attaching a semiconductor chip to the upper surface of the chip attaching part, and a secondary die bonding step of attaching a semiconductor chip to the bottom surface of the chip attaching part. At the bottom, there is an adhesive layer attached in the wafer preparation step, and die bonding is performed by the adhesive layer.

Meanwhile, the wire bonding step includes a primary wire bonding step for the semiconductor chip attached to the upper surface of the chip attaching portion and a secondary wire bonding step for the semiconductor chip attached to the bottom surface of the chip attaching portion, which is attached to the lead. It is preferable that the reverse wire bonding forms balls and stitches on electrode pads of the semiconductor chip, and includes bonding wires connected to the semiconductor chip attached to the upper surface of the chip attaching portion and bonding wires connected to the semiconductor chip attached to the bottom surface of the chip attaching portion. Make the length different. For example, the length of the bonding wire connected to the semiconductor chip with a small step between the semiconductor chip and the lead is shorter.

By applying the ultra-thin technology of the present invention, it is possible to implement a laminated package having a thickness of 0.6 mm of the package forming body or a package having a thickness of 0.48 mm (if there is only one semiconductor chip), which is a portable device such as a memory card. It can be applied to various electronic devices requiring thin thickness such as electronic devices.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like or corresponding elements throughout. The drawings are briefly shown to help understand the embodiments of the present invention, and do not necessarily reflect actual specifications or dimensions.

The structure of the ultra-thin laminated package device according to the present invention will be described with reference to FIGS. 2 to 11.

First embodiment

2 is a partially exploded plan view illustrating an ultra-thin semiconductor package according to a first exemplary embodiment of the present invention. 3A is a cross-sectional view taken along the line III-III of FIG. 2, FIG. 3B is a partial detail view of FIG. 3A, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 2.

As shown in FIGS. 2 to 4, the ultra-thin semiconductor package 100 according to the first embodiment of the present invention includes a lead frame 110 including a die pad 112, tie bars 114, and leads 116. ). The die pad 112 is located in the center of the package 100 and a number of leads 116 and several tie bars 114 are disposed around the die pad 112. The leads 116 are separated from the die pad 112, but the tie bars 114 are connected to the die pad 112. The die pad 112 includes a chip attaching portion 112a to which the semiconductor chip 120 is attached and an edge portion 112b integrally formed with the chip attaching portion 112a around the die attaching portion 112a.

Upper and lower semiconductor integrated circuit chips 120a and 120b are attached to both surfaces of the lead frame 110, that is, the upper and lower surfaces of the die pad 112 and the chip attaching part 112a. The semiconductor integrated circuit chip 120 is, for example, a DRAM, a flash memory, or a non-memory IC device. The upper semiconductor chip 120a and the lower semiconductor chip 120b may be the same kind of chips, or different types of different chips. For example, if you want to increase the memory capacity, the same memory chip is used to construct the package.

The upper and lower semiconductor integrated circuit chips 120 are attached to the chip attaching portion 112a of the die pad 112 through the adhesive layer 122. An adhesive tape such as silver-epoxy or an adhesive tape in the form of a film is attached to the adhesive layer. Used as 122. It is preferable that the adhesive layer 122 is a film adhesive tape made of epoxy-based resin, and the adhesive layer 122 has been previously attached to the bottom surface of the semiconductor chip in the wafer state. The semiconductor integrated circuit chip 120 is electrically connected to the leads 116 through the bonding wire 124. The bonding wire 124 uses, for example, a conventional Au wire.

The semiconductor integrated circuit chip 120, the die pad 112, the bonding wire 124, and the like are all sealed inside the package molded body 126. The package molded body 126 is molded from a molding resin such as an epoxy compound. In the manufacturing process of the semiconductor package 100, the tie bar 114 supporting the die pad 112 is connected to the die pad edge portion 112b and remains only inside the package molded body 126. The lead 116, which is an electrical and physical medium between the semiconductor package 100 and an external circuit board (not shown), is connected to the semiconductor integrated circuit chip 120 by a bonding wire 124 in the package molded body 126. The portion connected to the circuit board is located outside the package molded body 126. A lead portion located inside the molded body 126 is called an inner lead 116a, and a lead portion placed outside the molded body 126 is called an outer lead 116b. The external lead 116b is bent into a shape suitable for mounting the package element 110 on an external circuit board, for example, a gull-wing shape.

One of the features of the present invention is that the thickness t1 of the die pad 112 chip attaching portion 112a is smaller than the thickness t2 of the lid 116 (see FIG. 3B). As is well known in the art, the lead frame 110 used to manufacture the package 100 is made of a copper or iron-nickel alloy (eg, alloy42) material. As will be described later, the lead frame 110 is made from a thin plate-shaped lead frame disc, and the die frame 112, tie by patterning the lead frame disc by etching or stamping. The bar 114, the lead 116, and the like are formed. In addition, although not shown in the drawings because it is not included in the manufactured package 100, a dam bar, a side rail, and the like, which perform a specific function in the package manufacturing process, manufacture the lead frame 110. Is formed in the process.

The lead frame 110 may vary in thickness depending on the type of the semiconductor package 100. In addition, in accordance with the trend of thinning of the semiconductor package 100, the thickness of the lead frame 110 continues to decrease. As a result, lead frames having a thickness of 300 μm (= 12 mil), 250 μm (= 10 mil), 200 μm (= 8 mil), and 150 μm (= 6 mil) were used in recent years. Lead frames reduced to) levels are also used. In this embodiment, the thin lead frame 110 is used to a thickness of about 100 μm, and the thickness of the die pad 112 (that is, the thickness of the chip attaching portion 112a) is equal to 30 of the total thickness of the lead frame 110. Thin to 50%, eg, about 40%. That is, the thickness of the lid 116 (t2 in FIG. 3B) is about 100 μm, while the thickness of the die pad 112 (t1 in FIG. 3B) is about 40 μm. On the other hand, the tie bar 114 is about 40 mu m in thickness, as is the thickness of the die pad 112 (see Fig. 4). In this embodiment, the chip attaching portion 112a of the die pad 112 has the same thickness as the edge portion 112b.

By making the thickness of the die pad 112 thin, the semiconductor package 100 may be made thin. In the case of this embodiment, the thickness (T of FIG. 3A) of the semiconductor package 110 is about 0.58 mm. Referring to FIG. 3B, the thickness of the adhesive layer 122 is 10 to 20 µm, respectively, and the thickness t3 of the semiconductor integrated circuit chip 120 is 100 to 150 µm, respectively, and an upper surface of the semiconductor integrated circuit chip 120 is provided. The height or loop height t 4 of the bonding wire 124 is from about 80 μm.

Since the loop of the bonding wire 124 also affects the overall thickness of the package element, the wire bonding between the semiconductor integrated circuit chip 120 and the lead 116 uses a so-called reverse bonding method. Reverse bonding is a ball bonding in the chip electrode terminal 128, pulls the wire 124 toward the lead 116, and then stitch bonding in the lead 116 as in a typical wire bonding method. Rather than performing the ball bonding on the lead 116, the wire 124 is pulled toward the semiconductor chip 120, and then the stitch bonding is performed on the chip electrode terminal 128. By doing so, the wire height (about 150 μm) in typical wire bonding is reduced to half level (about 80 μm) in reverse bonding. Meanwhile, a metal bump (not shown) may be formed on the chip electrode terminal 128 to mitigate the impact on the semiconductor chip 120 in the reverse bonding process.

The method of reducing the thickness of the die pad 112 includes a method of partially removing both sides of the die pad 112 and a method of partially removing only one side of the die pad 112 in the manufacturing process of the lead frame 110. Here, partly removing means removing the die pad to a certain depth but not completely. This embodiment is an example in which both surfaces of the die pad 112 are partially removed to reduce the thickness, and the second and third embodiments described later are examples in which only one surface is partially removed. As mentioned above, the die pad 112 is supported by the tie bars 114 in the package manufacturing process. Therefore, even if the die pad 112 is thin, it does not affect the physical strength of the lead frame 110 as a whole. In addition, there is an advantage that can use the existing apparatus and process for manufacturing the lead frame 110 as it is.

On the other hand, if only one side of the die pad 112 is partially removed, the die pad 112 is not located at the middle portion (in the thickness direction) of the lid 116, but rather the top surface or the bottom of the lid 116. Will match the face. In other words, the die pad 112 is slightly biased toward the upper side or the lower side without being located at the center in the thickness direction of the package molded body 126. This means that the thickness of the upper side and the lower side of the package molded body 126 is changed based on the active surface (that is, the surface on which the chip electrode pad is formed) of each of the upper and lower semiconductor integrated circuit chips 120a and 120b. In the molding process of forming the package molded body 126, incomplete molding may be caused.

Second Embodiment and Third Embodiment

Therefore, when only one side of the die pad is partially removed to realize a thin thickness of the die pad, the package body with respect to the die pad may be formed by adjusting the position of the die pad or forming a package molded asymmetrically based on the position of the die pad. A vertical symmetrical structure is realized. The former is the second embodiment and the latter is the third embodiment. 5 and 6 illustrate cross-sectional views of an ultra-thin semiconductor package 200 according to a second embodiment of the present invention, and FIG. 6 illustrates a cross-sectional view of the third embodiment of the present invention. Each of the ultra-thin semiconductor packages 300 according to the present invention is shown. 5 is a cross-sectional view corresponding to FIG. 4, and FIG. 6 is a cross-sectional view corresponding to FIG. 3A.

First, referring to FIG. 5, the die pad 212 is disposed below the tie bar 214 by a predetermined distance d with respect to the package molding thickness direction. That is, the die pad 212 is so-called down set from the horizontal plane formed by the lead frame 210. Therefore, even if only one surface is partially removed to form the die pad 212, the die pad 212 can be positioned at the center in the thickness direction of the package molded body 126. That is, the distance d1 from the active surface of the upper semiconductor chip 120a to the top surface of the package molded body 126 is equal to the distance d2 from the active surface of the lower semiconductor chip 120b to the bottom surface of the package molded body 126. The size of the downset is determined by the thickness of the semiconductor chip, the thickness of the lead, the thickness of the die pad, the package thickness, and the like, and may vary depending on whether the upper and lower chips have the same thickness or different thicknesses.

Next, a third embodiment will be described with reference to FIG. 6. The package molded body 126 is formed based on the position of the die pad 312. In other words, the package molded body 126 is generally formed so that its upper and lower thicknesses are the same with respect to the lid 316, whereas the package molded body 126 of the present embodiment has the upper and lower thicknesses based on the die pad 312. Form the same. That is, the thickness t5 of the upper portion of the lid 316 of the package molded body 126 and the thickness of the lower portion of the lid 316 so that the die pad 312 may be located at the center of the package body 126 in the center of the thickness of the package molded body 126. (t6) forms differently. Therefore, when viewed with respect to the lead 316 of the lead frame 310, so-called unbalanced molding is performed. Such asymmetrical molding can be implemented, for example, by varying the size of the cavity of the upper and lower molds.

Fourth embodiment

On the other hand, the tie bar is the same thickness as the die pad edge. The die pad edge may be the same thickness as the die pad chip attachment or the same thickness as the lead. This is the difference between removing the die pad and the tie bar when partially removing the die pad. In the first embodiment described above, the die pad edge portion 112b has the same thickness as the tie bar 114 and the chip attaching portion 112a (see Fig. 4). And tie bars have the same thickness as the leads. 7A and 7B are cross-sectional views illustrating an ultra-thin semiconductor package 400 according to a fourth embodiment of the present invention. 7A is a cross-sectional view corresponding to FIG. 3, and FIG. 7B is a cross-sectional view corresponding to FIG. 4.

As shown in FIGS. 7A and 7B, the die pad 412 includes a chip attachment portion 412a to which the semiconductor integrated circuit chip 120 is attached and an edge portion 412b connected to the tie bar 414. . At this time, the chip attaching portion 412a of the die pad 412 is partially removed and is thin, but the edge portion 412b and the tie bar 414 of the die pad 412 are not removed. Accordingly, the remaining portions of the lead frame 410 except for the center portion 412a of the die pad 412, that is, the edge 412b and the tie bar 414 and the lead 416 of the die pad 412 are all Have the same thickness. In fact, considering that only the chip attachment portion 412a of the die pad 412 adhered to the semiconductor integrated circuit chip 120 contributes to the thinning of the package 400, the edge portion 412b of the die pad 412 and By maintaining the thickness of the tie bar 414 as it is, it is possible to stably implement the supporting function of the die pad 412 by the tie bar 414.

Fifth Embodiment

The semiconductor package device shown in FIGS. 8 to 10 is an embodiment of a multilayer package device in which the thickness of the die pad and the lead are different from each other by partially removing one side of the die pad.

In the multilayer package device 500 according to the exemplary embodiment illustrated in FIG. 8, the upper semiconductor chip 120a and the lower semiconductor chip 120b respectively apply the adhesive 122 to both sides of the chip attaching part 512a of the die pad 512. Attached through. The edge portion 512b of the die pad 512 is larger in thickness than the chip attachment portion 512a and is equal to the thickness of the lead 516, ie the inner lead 516a. The thickness of the chip attachment portion 512a is, for example, in the range of about 30-50% of the thickness of the edge portion 512b. Accordingly, the die pad 512 is shaped like a 'c' in which the cut surface of the die face 512b protrudes. The protruding direction is upward with respect to the thickness direction of the package molded body 526, that is, the upper semiconductor chip ( Facing 120a).

In the process of forming the package body 526, for example, an injection molding process, it is preferable to realize a vertically symmetrical structure based on the die pad. To this end, the upper and lower thicknesses D1 and D2 of the package body 526 are different based on the inner lead 516a so that the upper chip 120a and the lower chip 120b are formed on the upper and lower sides of the package forming body 526. Can be dropped by the same distance d. For example, the thickness of the package molded body 526 is 580 µm, the thickness of the upper and lower semiconductor chips 120a and 120b is 120 µm, the thickness of the adhesive layer 122 is 20 µm, and the thickness of the inner lead 516a is 100 µm. When the thickness of the die pad chip attaching portion 512a is 40 µm, the thickness D1 is 205 µm, D2 is 275 µm, and the distances d are all 135 µm.

As illustrated in FIG. 9, the semiconductor chips 120a and 120b are both electrically connected by the internal lead 516a and the reverse bonding wire 524. The reverse bonding wire 524 includes a ball 550 bonded to the surface of the inner lead 516a and a stitch 560 bonded to the electrode pad 534 of the semiconductor chip 120. The balls 550 and stitches 560 are formed by capillaries used in conventional wire bonding processes. Since no ball is formed in the electrode pad 534 of the semiconductor chip, a loop is not required on the electrode pad. A loop of wire is needed just above the ball 550 bonded to the inner lead 516a, but the inner lead 516a is from the active surface 540 of the upper and lower semiconductor chips 120a and 120b toward the center of the package molded body 526. Because of their biased arrangement, the wire loop does not affect the overall thickness increase of the package molded body 526.

Meanwhile, the bonding wire 530 connected to the upper semiconductor chip 120a may be shorter in length than the bonding wire 532 connected to the lower semiconductor chip 120b. The bondability of the wires 530 and 532 is proportional to the step difference between the chip electrode pad and the lead (since a margin for the loop height can be secured), and is inversely proportional to the distance between the electrode pad and the lead. Therefore, it is preferable to shorten the length of the bonding wire 530 connected to the upper semiconductor chip 120a having a small step with the lead 516a to ensure bonding property.

Sixth embodiment

The structure 600 shown in FIG. 10 is an embodiment of a laminated package device in which the thickness of the die pad and the lead are different from each other by partially removing one side of the die pad 612a as in the fifth embodiment. The thickness of the die pad chip attachment portion 612a is thinner, for example in the range of 30-50% of the thickness of the die pad edge portion 612b and the inner lead 616a. The edge portion 612b and the inner lead 616a have the same thickness.

The difference from the package element 500 according to the fifth embodiment is that the shape of the cut surface of the die pad 612 protrudes from the chip attaching portion 612a, and the protruding direction of the package molded body 626. ) Is directed downward toward the thickness direction, that is, toward the lower semiconductor chip 120b. In the sixth embodiment, on the other hand, in order to realize a vertically symmetrical structure with respect to the die pad in the package body forming step, it is necessary to downset the tie bar by a predetermined size. Downset processing of the tie bar is, for example, disposing the die pad downward from the tie bar by a predetermined distance dd with respect to the package molding thickness direction.

In this embodiment, for example, the thickness of the package molded body 626 is 580 μm, the thickness of the upper and lower semiconductor chips 120a and 120b is 120 μm, the thickness of the adhesive layer 122 is 20 μm, and the thickness of the inner lead 616a is increased. When the thickness is 100 μm and the die pad attaching portion 612a is 40 μm, the distance d from the upper semiconductor chip 120a to the upper surface of the package molded body 626 is the package molded body 626 from the lower semiconductor chip 120b. ) Is the same as the distance d to the bottom surface and 135㎛. On the other hand, the size dd of downset processing is 25 micrometers, making the package molded object thickness D of upper and lower parts of the inner lead 616a the same, and implement | achieving a vertically symmetrical structure with respect to the die pad 612.

In this embodiment, the bonding wire 632 connected to the upper chip 120a is longer than the bonding wire 630 connected to the lower chip 120b because the primary wire bonding and secondary in the wire bonding process It may be due to the structure supporting the semiconductor chip when the wire bonding is performed, or to improve the bonding property of the wire.

Seventh embodiment

Meanwhile, the die pad applied to the present invention may be divided into at least two parts. The seventh embodiment corresponds to such an example, and FIGS. 11A and 11B show an ultra-thin semiconductor package 700 according to this embodiment. FIG. 11A is a plan view and FIG. 11B is a cross-sectional view taken along the line IXB-IXB of FIG. 11A.

As shown in FIGS. 11A and 11B, the die pad 712 includes a first die pad 720 and a second die pad 730 divided into two parts, which may be divided into two or more if necessary. have. Each of the divided die pads 720 and 730 is connected to each tie bar 740 and 750, and the semiconductor integrated circuit chip 120 is connected to the first die pad 720 and the second through the adhesive layer 122. Attached to die pad 730 simultaneously.

When the die pad is divided into the first die pad 720 and the second die pad 730 as in this embodiment, the original functions of the die pads 720 and 730 for attaching and supporting the semiconductor integrated circuit chip 120 are Without losing, the area occupied by the die pad within the package molded body 726 is reduced. Accordingly, the reliability degradation that may occur due to the difference in thermal expansion coefficient between the die pads 720 and 730 and the remaining components (for example, the package molded body 726, the semiconductor integrated circuit chip 120, and the adhesive layer 122). Problems (e.g., interfacial peeling, cracking of the package molded body) can be largely solved. In this respect, the ultra-thin semiconductor package of the present invention may use a small die pad smaller in size than a semiconductor integrated circuit chip in addition to the divided die pad.

In the package device 700 according to the seventh exemplary embodiment, the first die pad 720 and the second die pad 730 have chip attaching portions 720a and 730a and edge portions 720b and 730b, respectively. The thickness of the attachment portions 720a and 730a is thinner, for example in the range of 30-50% of the thickness of the lead frame lead 716. 11A and 11B, the thickness of the die pad edge portions 720b and 730b is the same as that of the die pad chip attaching portions 720a and 730a. However, the thicknesses of the edge portions of the die pad edge portions 720b and 730b are the same as those of the fourth to sixth embodiments. It is also possible to do the same.

Manufacturing method of ultra thin package device

Next, an ultra-thin package device manufacturing method according to the present invention will be described with reference to FIGS. 12 and 13.

12A to 12F are partial cross-sectional views illustrating a method of partially thinning a die pad of a lead frame in a process of manufacturing an ultra-thin package device according to the present invention. What is described here is, for example, a die pad structure suitable for use in the package structures of the fifth and sixth embodiments described with reference to FIGS. 8 and 10, that is, a die in which a die pad edge portion protrudes from the die pad chip attachment portion. The pad structure will be described. However, it will be understood by those skilled in the art that the die pad structure according to another embodiment may be easily implemented by modifying the process described below.

First, a disc is prepared from a lead frame made of a copper alloy or an iron-nickel alloy. 12A shows the die pad region 802 of the lead frame. The die pad region 802 is, for example, 100 mu m thick.

Referring to FIG. 12B, photo resists 804 and 806 (for example, photo-resistor) are entirely applied on both sides of the die pad region 802, for example, with a thickness of 7.0 ± 1.0 μm. The masks 810 and 812 are aligned and exposed as shown in FIG. 10C above and below the die pad region 802 to which the photoresist 804 and 806 are applied. Predetermined patterns are formed in the masks 810 and 812. For example, the black pattern 811 of the mask 810 reflects the light 813 and the remaining white patterns transmit the light.

When the exposed sample is developed, the register at the position where no light is received is removed. When the remaining portion of the resist is treated with, for example, chromium (Cr), the edge pattern 804a is disposed above the die pad region 802 and the resist pattern 806a remains below the die pad region 802 as shown in FIG. 12D. Get the structure. For example, when the etching solution is sprayed or immersed in the etching solution, the portions exposed to the resist patterns 804a and 806a are partially removed as shown in FIG. 12E. The amount removed when selectively removing the die pad region 802 is determined by the pressure and the deposition or spraying time of the corrosion solution. When the resist pattern is removed, as shown in FIG. 12F, a die pad having a structure in which the chip attaching portion 820 of the die pad is thinner than the edge portion 830 is formed.

Since the rest of the lead frame, that is, the inner lead, the outer lead, the tie bar, the side rails, and the like are not etched, they are the same thickness as the die pad edge portion 830.

13A to 13I are cross-sectional views illustrating a process of mounting and packaging an ultra-thin semiconductor package device according to the present invention, for example, in a lead frame manufactured by FIGS. 12A to 12F.

As shown in FIG. 13A, a wafer 902 is prepared by forming a plurality of desired IC elements through a wafer fabrication process and having an ultraviolet tape 904 attached to an active surface 903. Here, the ultraviolet light tapes 904 and 906 refer to a tape which hardly loses adhesive strength when ultraviolet light is irradiated. The ultraviolet light tape 904 attached to the wafer active surface 903 absorbs shock and vibration, thereby providing a pretreatment process, for example, This is to prevent the wafer from being broken in the wafer backside polishing process and to prevent the adhesive residue from remaining on the wafer surface or impacting the wafer when removing the tape from the wafer. An ultraviolet tape 906 is attached through the adhesive layer 908 to the bottom surface of the wafer 902 that has been back polished (ie, opposite to the active surface). The ultraviolet ray tape 906 also has a property that the adhesive force disappears when the ultraviolet ray is irradiated. The ultraviolet ray tape 906 is attached to the wafer through another adhesive layer 908 without being directly attached to the bottom surface of the wafer.

The adhesive layer 908 is preferably, for example, a film adhesive tape composed of an epoxy resin. The adhesive layer 908 includes a hardener and a coupling agent, wherein the hardener is for example an amine and the binder is for example silane.

As shown in FIG. 13A, when the first ultraviolet irradiation step of irradiating ultraviolet rays to the active surface 903 of the wafer 902 through an ultraviolet lamp or the like proceeds, the ultraviolet tape 904 attached to the wafer active surface 903 is performed. Is easily removed from the wafer active surface 903 without losing adhesion and impacting the wafer 902 or leaving no residue. 13A may be omitted as an optional step in the ultra-thin semiconductor package device manufacturing process according to the present invention.

As shown in FIG. 13B, a second ultraviolet irradiation step of irradiating ultraviolet rays to the bottom surface of the wafer 902 from which the ultraviolet tape 904 is removed is performed. Then, the ultraviolet tape 906 is in a state where the adhesive force with the adhesive layer 908 becomes weak and can be easily removed from the adhesive layer 908.

In this state, as shown in FIG. 13C, the wafer is cut into individual chips by performing a wafer sawing step of cutting the wafer 902 using a cutting means 912, for example, a diamond wheel rotating at a high speed. To 910. Since the adhesive layer 908 is attached to the bottom of the separated individual chip 910, and the adhesive layer 908 is connected by the ultraviolet tape 906, the individual chips 910 maintain the shape of the wafer as a whole. Doing.

Referring to FIG. 13D, the individual chips 910 that are separated while maintaining the wafer shape are adsorbed by, for example, a vacuum pickup means 920 to be completely separated from the wafer (die pick-up step). As previously described, since the ultraviolet tape 906 has lost its adhesion with the adhesive layer 908, the individual chips 910 can be easily separated from the ultraviolet tape 906. On the other hand, the adhesive layer 908 is attached to the bottom surface of each chip 910 that is completely separated.

Referring to FIG. 13E, a primary chip for attaching an individual chip 910 having an adhesive layer 908 attached to a bottom surface thereof, for example, on a die pad 932 of a lead frame 930 manufactured by the process described with reference to FIG. 12. Proceed with the die bonding step. The lead frame 930 includes a die pad 932 and a lead 938, and the die pad 932 includes a chip attachment portion 934 and an edge portion 936. The edge portion 936 protrudes from the chip attachment portion 934 and has the same thickness as the lead 938. The chip attachment portion 934 has a thickness in the range of 30-50% of the thickness of the edge portion 936.

Since the individual chips separated from the wafer are attached to the top surface of the chip attachment portion 934, this is called the upper chip 910a. Here, the upper surface of the chip attaching portion 934 refers to a surface positioned in the same direction as the protruding direction of the edge portion 936. Since the adhesive layer 908 is attached to the bottom of the upper chip 910a, the upper chip 910a may be bonded to the die pad without a separate adhesive coating process for die bonding.

Next, as shown in FIG. 13F, the secondary die bonding step of attaching the lower semiconductor chip 910b to the bottom surface of the die pad chip attaching portion 934 is performed. Since the adhesive layer 908 is also attached to the bottom surface of the lower semiconductor chip 910b, the lower chip 910b may be bonded to the die pad without a separate adhesive coating process for secondary die bonding.

In die bonding, it is not important to bond the top chip first or the bottom chip first.

Referring to FIG. 13G, a primary wire bonding step of aligning and fixing the lead frame 902 on the support 940a and electrically connecting the upper chip 910a and the lead frame lead 938 to the bonding wire 942 is performed. Proceed.

Then, as shown in FIG. 13H, the secondary wire bonding aligns and secures the lead frame 902 to the support 940b and then electrically connects the lower chip 910b and the lead frame lead 938 with a bonding wire 945. Proceed to step.

It is not important which of the upper chip and the lower chip is used first in the wire bonding step. However, in consideration of the bondability of the wires 942 and 945, the length of the bonding wire 942 connected to the semiconductor chip disposed in the protruding direction of the upper chip 910a, that is, the edge 936 is shorter. It is desirable to. This is because the step from the active surface of the upper chip 910a to the edge 936 is smaller than the step relative to the lower chip 910b.

The primary and secondary wire bonding steps are preferably reverse wire bonding steps in which balls are formed in the lead frame leads 938 and the wires are pulled toward the chip with a capillary to stitch bond the wires to the electrode pads of the chip. .

As shown in FIG. 13I, when the secondary wire bonding is completed, the package molding body 950 is formed through an injection molding process, and the lead 938 placed outside the molding body 950 is bent into an appropriate shape. The ultra-thin semiconductor package device according to the present invention is completed.

Since the package according to the invention is very small in thickness, the curing rate of the molded body is very fast. Accordingly, the molding step of FIG. 13I is preferably a low temperature process. For example, the molding process is performed in the temperature range of 170 ~ 175 ℃.

Application example

The ultra-thin semiconductor package device according to the present invention can be widely applied to various portable electronic devices such as digital cameras, MP3 players, handheld personal computers (HPC), personal digital assistants (PDAs), mobile phones, and the like.

14A and 14B show an example of a memory card in which an ultra-thin semiconductor package according to the present invention is integrated. FIG. 14A is a plan view of the memory card, and FIG. 14B is a cross-sectional view taken along the line 14b-14b of FIG. 14A.

The memory card is mainly implemented in the form of a card using flash memory, currently SmartMedia (Toshiba, Japan), Memory Stick (Sony), Sony (Japan), SanDisk (USA) SanDisk's CompactFlash, MultiMedia Card and Secure Digital Card, developed jointly by SanDisk and Siemens, are standardized. Shown in Fig. 14 is a MemoryStick Duo manufactured by Sony Corporation.

The memory card 960 includes a main board 967, a terminal pad 961 formed on the substrate, a controller mounting portion 962, a passive element mounting portion 963, and a memory mounting portion 965. The memory mounting unit 965 is divided by another area and an interposer 965. The standard of the memory stick duo card 960 is 31.0 mm in length L, 20.0 mm in width W, and 1.6 mm in height. The memory mounting portion 965 in which the memory elements are mounted has a length L1 of 12 mm and a width W1 of 18 mm. As shown in FIG. 14B, the separator 965 has a maximum height H of 0.7 mm, and as described in the various embodiments of the present invention, the ultra-thin semiconductor package 1000 according to the present invention has a thickness of 0.58 mm, and thus the external lead. In consideration of the above, the maximum height of the separator 965 may be applied to the memory mounting portion 965 of the memory card 960 without exceeding 0.7 mm. Therefore, it is possible to increase the capacity of the memory card more than twice while achieving miniaturization of the memory card.

Meanwhile, the semiconductor package thinning technology according to the present invention can be applied to a package device using only one semiconductor integrated circuit chip. 15 and 16 illustrate such an example. The package of FIG. 15 corresponds to the package of FIG. 8 and the package of FIG. 16 corresponds to the package of FIG. 10.

As shown in FIG. 15, the semiconductor package 550 includes only one semiconductor integrated circuit chip 120, and the chip attaching portion 572a of the die pad 572 to which the semiconductor integrated circuit chip 120 is attached is formed. Although the thickness is thinner than the edge portion 572b, the thickness of the chip attachment portion 572a is preferably about 30-50% of the thickness of the edge portion 572b. The die pad edge 572b is the same thickness as the lid 516. The edge portion 572b protrudes toward the chip 120 rather than the chip attachment portion 572a, and the die pad is downset to realize a vertically symmetrical structure around the lead 516. For example, when the thickness of the chip 120 is 120 µm, the thickness of the adhesive 122 is 20 µm, and the thickness of the lead 516 is 100 µm, the thickness of the chip attachment portion 572a is 40 µm. The thickness of the upper and lower package molded bodies 580 is the same at 185 µm. Thus, the overall thickness of the package 550 is 470 μm and the die pad downset is 40 μm.

Meanwhile, as in the package 650 embodiment of FIG. 16, when the die pad edge portion 672b protrudes downward from the chip attaching portion 672a, that is, when the die pad edge portion 672b protrudes to the opposite side of the semiconductor chip 120, the die pad is used. (672) The upper surface of the lead 670 is aligned with the upper surface of the lead 670 to form a package molded body 680 by asymmetrical molding. In this embodiment, a semiconductor chip 120 is attached through the adhesive 122 on top of the die pad 672 face. For example, when the thickness of the chip 120 is 120 μm, the thickness of the adhesive 122 is 20 μm, the thickness of the lead 670 is 100 μm, and the thickness of the chip attachment portion 672a is 40 μm, the lead ( 670, the thickness of the molded body 680 is 285 μm, and the thickness of the molded body 680 under the lid 670 is 85 μm. However, the distance from the active surface of the semiconductor chip 120 to the top surface of the molded body 680 and the distance from the bottom surface of the chip attachment portion 672b to the bottom surface of the molded body 680 are the same, thereby realizing a vertically symmetrical structure.

Thus, applying the thinning technology of the present invention can realize an ultra-thin package device having a thickness of 0.5mm or less.

As described above through some embodiments, the ultra-thin semiconductor package according to the present invention has various effects and advantages as follows.

The ultra-thin semiconductor package of the present invention can realize a thickness of 0.7 mm or less, for example, 0.58 mm or 0.47 mm. In addition, despite the extremely thin thickness, the semiconductor package has excellent physical reliability and easy process management.

That is, since the ultra-thin semiconductor package of the present invention reduces the thickness of the die pad to realize the thinning of the semiconductor package, it is not affected by the process reliability or the package reliability in terms of the package manufacturing process or the finished package structure. In addition, the method of reducing the thickness of the die pad can use the existing lead frame manufacturing apparatus and process as it is, no additional investment is required.

In addition, the ultra-thin semiconductor package of the present invention can prevent incomplete molding through downset processing of the die pad or asymmetrical molding of the package molded body.

In addition, the ultra-thin semiconductor package of the present invention can stably implement the support function of the die pad by the tie bar by partially removing only the chip attachment portion of the die pad except for the edge portion and the tie bar of the die pad.

In addition, the ultra-thin semiconductor package of the present invention can use the divided die pad to reduce the area occupied by the die pad in the package molded body, thereby preventing the reliability degradation due to the difference in thermal expansion coefficient between the die pad and the remaining components.

In addition, the ultra-thin semiconductor package of the present invention is not limited to the type and number of semiconductor integrated circuit chips, and the type of adhesive layer for attaching the semiconductor integrated circuit chips to the die pad is not limited. In addition, by adopting a reverse bonding method instead of a typical wire bonding method, the height of the wire can be greatly reduced.

In the present specification and drawings, several preferred embodiments of the present invention have been disclosed, and although specific terms are used, these are merely used in a general sense to easily describe the technical content of the present invention and to help the readers understand the present invention. It is not intended to limit the scope of the invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

Claims (52)

Ultra-thin semiconductor package device, A semiconductor chip in which a plurality of electrode pads are formed; A molded body forming a body of a package element and encapsulating the semiconductor chip; A lead frame having a die pad on which the semiconductor chip is mounted, a plurality of leads disposed around the die pad apart from the die pad, a tie bar connected to the die pad and disposed around the die pad; A bonding wire included in the molded body and electrically connecting the plurality of electrode pads and the plurality of leads, The die pad includes a chip attaching portion to which a semiconductor chip is attached and an edge portion existing around the die pad, and each of the plurality of leads includes an inner lead included in the molded body and bonded inside the molded body and outside the molded body. Equipped with an external lead integrally, The chip attachment portion of the die pad has a first thickness, the inner lead has a second thickness, and the first thickness is smaller than the second thickness. Ultra-thin semiconductor package device. The ultra-thin semiconductor package device of claim 1, wherein the first thickness is in a range of 30 to 50% of the second thickness. The ultra-thin semiconductor package device of claim 1, wherein the chip attaching portion has a thickness equal to that of the edge portion. The ultra-thin semiconductor package device of claim 1, further comprising two semiconductor integrated circuit chips each attached to both sides of the die pad chip attaching part. The ultra-thin semiconductor package device according to claim 1, wherein the die pad is disposed below the lead by a predetermined distance with respect to the molded body thickness direction. The ultra-thin semiconductor package device of claim 1, wherein the bonding wire is connected by a ball formed on the lead surface and a stitch formed on an electrode pad of the semiconductor chip. The ultra-thin semiconductor package device according to claim 6, wherein a metal bump is formed on an electrode pad of the semiconductor chip, and the stitch is formed on the metal bump. The ultra-thin semiconductor package device of claim 1, wherein thicknesses of upper and lower moldings are different from each other around the lead. The ultra-thin semiconductor package device of claim 5, wherein the tie bar has a thickness equal to that of the lead. The ultra-thin semiconductor package device of claim 1, wherein a thickness of the tie bar is equal to a thickness of the die pad edge portion. The ultra-thin semiconductor package device of claim 1, wherein the die pad edge portion protrudes from both sides of the chip attaching portion, and a thickness of the edge portion is equal to a thickness of a lead. The ultra-thin semiconductor package device of claim 1, wherein the die pad is divided into two or more parts and includes a first die pad and a second die pad. The ultra-thin semiconductor package device of claim 12, wherein each of the first die pad and the second die pad has a chip attaching portion and an edge portion. The ultra-thin semiconductor package device of claim 1, wherein the semiconductor chip is bonded to a chip attaching part of the die pad by an adhesive. The ultra-thin semiconductor package device of claim 1, wherein the lead frame is made of an iron-nickel alloy or a copper alloy, and the bonding wire is a gold wire. The ultra-thin semiconductor package device of claim 1, wherein the semiconductor chip is a memory device, and the adhesive is a film adhesive tape including an epoxy-based resin. Ultra-thin semiconductor package device, A first semiconductor chip and a second semiconductor chip in which a plurality of electrode pads are formed; A molded body forming a body of a package element and encapsulating the semiconductor chip; A lead frame having a die pad on which the semiconductor chip is mounted, a plurality of leads disposed around the die pad apart from the die pad, a tie bar connected to the die pad and disposed around the die pad; A bonding wire included in the molded body and electrically connecting the plurality of electrode pads and the plurality of leads, The die pad includes a chip attaching portion to which a semiconductor chip is attached and an edge portion existing around the die pad, and each of the plurality of leads includes an inner lead included in the molded body and bonded inside the molded body and outside the molded body. Equipped with an external lead integrally, The chip attachment portion of the die pad has a first thickness, the inner lead has a second thickness, the first thickness is smaller than the second thickness, and the edge portion of the die pad has a thickness that is the second thickness of the inner lead. The edge portion protrudes in one direction relative to the chip attachment portion, wherein the first semiconductor chip is attached to the top surface of the die pad chip attachment portion and the second semiconductor chip is attached to the bottom surface of the die pad chip attachment portion. Characterized Ultra-thin semiconductor package device. 18. The ultra-thin semiconductor package device according to claim 17, wherein the protruding direction of the edge portion is in the direction of the first semiconductor chip. 19. The ultra-thin semiconductor package device according to claim 18, wherein the molded body has different thicknesses above and below the lead. 18. The ultra-thin semiconductor package device according to claim 17, wherein the protruding direction of the edge portion is in the direction of the second semiconductor chip. 21. The ultra-thin semiconductor package device according to claim 20, wherein the die pad is disposed below the lead in a thickness direction of the molded body by a predetermined distance. The ultra-thin semiconductor package device of claim 17, wherein the bonding wire connected to the semiconductor chip in the protruding direction of the edge portion is shorter than the bonding wire connected to the semiconductor chip in the opposite protruding direction. 18. The ultra-thin semiconductor package device according to claim 17, wherein the bonding wire is connected by a ball formed on the lead surface and a stitch formed on an electrode pad of the semiconductor chip. 24. The ultra-thin semiconductor package device according to claim 23, wherein a metal bump is formed on an electrode pad of the semiconductor chip, and the stitch is formed on the metal bump. 18. The ultra-thin semiconductor package device of claim 17, wherein the die pad is divided into two or more and includes a first die pad and a second die pad. The ultra-thin semiconductor package device of claim 25, wherein each of the first die pad and the second die pad has a chip attachment portion and an edge portion. The ultra-thin semiconductor package device of claim 17, wherein the semiconductor chip is a memory device, and the adhesive is a film adhesive tape including an epoxy-based resin. 18. The ultra-thin semiconductor package device according to claim 17, wherein the molded body has a thickness of about 580 μm, the edge portion has a thickness of 100 μm, and the chip attachment portion has a thickness of 40 μm. 18. The ultra-thin semiconductor package device according to claim 17, wherein the semiconductor chip is bonded to a die pad chip attaching portion by an adhesive, and the adhesive is an adhesive attached to a bottom surface of the semiconductor chip in a wafer state. As a method of manufacturing an ultra-thin semiconductor package device, Preparing a lead frame having a die pad, a tie bar supporting the die pad and connected to the die pad, and having a plurality of leads disposed around the die pad, the lead pad being formed around the die pad; Defining a chip attachment portion and an integral edge portion around the die pad; Etching the chip attachment portion to form a predetermined thickness thinner than the lead; A die bonding step of attaching a semiconductor chip to the etched chip attaching part; A wire bonding step of electrically connecting the semiconductor chip with a lead; Molding a portion of the semiconductor chip, a bonding wire, and a lead to form a package molding body; Ultra-thin semiconductor package device manufacturing method comprising a. 31. The method of claim 30, wherein the predetermined thickness of the chip attachment portion is in the range of 30-50% of the lead thickness. 31. The method of claim 30, wherein the die pad edge and the tie bar have the same thickness as the chip attaching portion. 31. The method of claim 30, wherein the die pad edge and the tie bar have the same thickness as the lead. 34. The method of claim 33, wherein the edge portions protrude to both sides with respect to the chip attaching portion. 34. The method of claim 33, wherein the edge portion protrudes to one side of the chip attaching portion. 36. The method of claim 35, wherein the die pad is disposed below the lead by a predetermined distance with respect to the molded body thickness direction. 31. The method of claim 30, wherein the molded body has a thickness different from above and below the lead. 31. The method of claim 30, further comprising: preparing a wafer having a plurality of semiconductor chips and having an active surface; Attaching an adhesive layer to an underside of the wafer and attaching an ultraviolet tape to the adhesive layer; Irradiating the ultraviolet tape with ultraviolet rays to remove the adhesive force between the adhesive layer and the ultraviolet tape; Cutting the wafer into a plurality of semiconductor chip units; Completely separating the cut semiconductor chip from the ultraviolet tape in a wafer state, and further comprising separating the semiconductor chip with the adhesive layer attached to a bottom surface of the semiconductor chip, The die bonding step is a step of bonding the semiconductor chip having the adhesive layer attached on the bottom surface to the die pad chip attachment portion. Ultra-thin semiconductor package device manufacturing method characterized in that. 39. The semiconductor chip of claim 30 or 38, wherein the semiconductor chip comprises a first semiconductor chip attached to an upper surface of a chip attaching portion and a second semiconductor chip attached to a lower surface of the chip attaching portion, wherein the die bonding step comprises the first semiconductor chip. And a second die bonding step of attaching the first die bonding step and the second die bonding step of attaching the second semiconductor chip. 39. The semiconductor chip of claim 30 or 38, wherein the semiconductor chip comprises a first semiconductor chip attached to an upper surface of a chip attaching part and a second semiconductor chip attached to a lower surface of the chip attaching part, wherein the wi-bonding step comprises the first semiconductor chip. And a second wire bonding step of electrically connecting the second wire to the lead and a second wire bonding step of electrically connecting the second semiconductor chip to the lead. 41. The method of claim 30 or 40, wherein the bonding wire is connected by a ball formed on the lead surface and a stitch formed on an electrode pad of the semiconductor chip. . 36. The method of claim 35, wherein a length of the bonding wire connected to the semiconductor chip in the protruding direction of the edge portion and the length of the bonding wire connected to the semiconductor chip opposite to the protruding direction are different from each other. 37. The method of claim 36, wherein the semiconductor chip is symmetrical with respect to the semiconductor chip. The method of claim 38, wherein the wafer preparation step, Attaching an ultraviolet tape to the active surface of the wafer, Polishing the opposite surface of the active surface of the wafer; Irradiating ultraviolet rays onto the ultraviolet tape attached to the active surface; And removing the ultraviolet tape from the active surface. The method of claim 30 or 38, wherein the forming of the package molding body comprises injecting molten resin in a temperature range of 170 to 175 ° C. 39. The method of claim 30 or 38, wherein the adhesive comprises an epoxy-based resin. 47. The method of claim 46, wherein the adhesive further comprises a hardener, and the hardener is an amine. 48. The method of claim 46 or 47, wherein the adhesive further comprises a coupling agent, wherein the binder is silane. 39. The method of claim 30 or 38, wherein the amount etched in the chip attachment etching step is determined by the pressure and the application time of the etchant. An electronic device comprising a semiconductor package element, The semiconductor package device has a thickness of a package molding body of 0.7 mm or less, The semiconductor package device, A semiconductor chip in which a plurality of electrode pads are formed; A molded body forming a body of a package element and encapsulating the semiconductor chip; A lead frame having a die pad on which the semiconductor chip is mounted, a plurality of leads disposed around the die pad apart from the die pad, a tie bar connected to the die pad and disposed around the die pad; A bonding wire included in the molded body and electrically connecting the plurality of electrode pads and the plurality of leads, The die pad includes a chip attaching portion to which a semiconductor chip is attached and an edge portion existing around the die pad. Each of the plurality of leads includes an inner lead included in the molded body and bonded outside of the molded body and the molded body. Equipped with an external lead integrally, The chip attachment portion of the die pad has a first thickness, the inner lead has a second thickness, and the first thickness is smaller than the second thickness. Electronics. An electronic device comprising a semiconductor package element, The semiconductor package device has a thickness of a package molding body of 0.7 mm or less, The semiconductor package device, A first semiconductor chip and a second semiconductor chip in which a plurality of electrode pads are formed; A molded body forming a body of a package element and encapsulating the semiconductor chip; A lead frame having a die pad on which the semiconductor chip is mounted, a plurality of leads disposed around the die pad apart from the die pad, a tie bar connected to the die pad and disposed around the die pad; A bonding wire included in the molded body and electrically connecting the plurality of electrode pads and the plurality of leads, The die pad includes a chip attaching portion to which a semiconductor chip is attached and an edge portion existing around the die pad, and each of the plurality of leads includes an inner lead included in the molded body and bonded inside the molded body and outside the molded body. Equipped with an external lead integrally, The chip attachment portion of the die pad has a first thickness, the inner lead has a second thickness, the first thickness is smaller than the second thickness, and the edge portion of the die pad has a thickness that is the second thickness of the inner lead. The edge portion protrudes in one direction relative to the chip attachment portion, wherein the first semiconductor chip is attached to the top surface of the die pad chip attachment portion and the second semiconductor chip is attached to the bottom surface of the die pad chip attachment portion. Characterized Electronics. 52. The method of claim 50 or 51, wherein the electronic device is a memory card.