KR20020071280A - Apparatus and method for controlling pll to receive quick paging message in mobile communication terminal - Google Patents

Abstract

PURPOSE: A PLL(Phase Locked Loop) control apparatus for receiving a quick paging message in a mobile communication terminal and a method thereof are provided to detect the quick paging message in a conventional mobile communication terminal and write PLL data for controlling a PLL in the PLL using a CS(Chip Select) signal and a data bus. CONSTITUTION: A control unit(701) has a CS port, data bus lines, and a PLL enable GPIO(General Purpose Input Output) port. A PLL(703) has a clock port connected to the CS port, a data port connected to one among the data bus lines, and a latch enable port connected to the PLL enable GPIO port.

Description

Apparatus and method for controlling phase-locked loop for receiving quick paging message of mobile communication terminal {APPARATUS AND METHOD FOR CONTROLLING PLL TO RECEIVE QUICK PAGING MESSAGE IN MOBILE COMMUNICATION TERMINAL}

The present invention relates to a mobile communication system, and more particularly, to an apparatus and method for controlling a phase locked loop for receiving a quick paging message of a mobile communication terminal in a mobile communication system for transmitting a quick paging message.

In general, in a code division multiple access (CDMA) mobile communication system, for example, an IS-95A mobile communication system, a mobile station (MS) receives a paging message from a base station (BS). Only when present, it wakes up from the idle sleep state and transitions to a slotted mode for monitoring a paging channel to receive a paging message from the base station. If there is a paging message of its own, the terminal generates an alert and informs the user.

However, the conventional terminal must re-acquisition the paging channel in idle sleep state to receive a paging message in slot mode. However, the conventional terminal has a high power consumption of the terminal, such as the time required for reacquisition of the paging channel and the time required for receiving a message. Therefore, in the IMT-2000 system, which is a third generation mobile communication system, quick paging has been adopted to ensure that the waiting time of the terminal is longer than that of the conventional mobile communication system.

Quick paging refers to a terminal through a forward quick paging channel (FQPCH), which is a new channel in addition to the existing paging channel before paging the base station whether there is a paging message for a specific terminal. will be. The message transmitted to the terminal through the quick paging channel is transmitted as a 1-bit message that does not perform interleaving and encoding, and the terminal transmits the quick paging at a designated location. ) Monitor the channel. That is, the terminal receives the 1-bit message of the quick paging channel without deinterleaving and decoding in the slot of the allocated time to determine whether to monitor the paging channel or not. will be. The quick paging message is repeatedly transmitted twice within an 80msec slot, i.e., at a interval of 40msec, in order to increase the reliability thereof, and the transmission rate is selected to be 9600bps or 4800bps.

Here, the 1-bit message of the quick paging channel is modulated using an on-off keying (OOK) method. The on-off keying method does not transmit any signal when there is no signal when there is a signal. Reason for using the on-off keying method without using binary-phase shift keying (BPSK) modulation. Since the BPSK modulation scheme has a low probability of generating '1' and transmits a signal having power to send data of '0', it acts as a factor to reduce energy of another channel, thereby reducing the overall performance of the system. While on-off keying schemes do not transmit any signal when "0", they do not affect the energy of other channels.

Therefore, one of the factors that determine the reception performance of quick paging is how accurately demodulate a signal transmitted using the on-off keying modulation scheme. The demodulation process, that is, an algorithm for determining two bit messages, will be described with reference to FIG. 1.

1 is a diagram illustrating a general quick paging channel determination algorithm.

First, if the terminal detects '0' when demodulating the first bit (step 111), the terminal immediately transitions to the idle sleep state without demodulating the second bit (step 113) and demodulates the first bit. When it is detected as '1' or ' Erasure ', the second bit is demodulated (step 115) to determine whether to transition to the idle sleep state or to decode a paging channel. In this case, the loss is a bit that occurs when the channel, that is, the fast quick paging channel state is estimated and is severely distorted, and means '1' regardless of the demodulation result of the quick-paging symbol. . If it is determined that the first bit is '1' or 'Erasure', the terminal monitors the following paging channel (step 117).

Since the quick paging is performed for a short time, the quick paging channel must be quickly reacquired in order to receive the quick paging message in the sleep state. The reacquisition is accomplished by a phase locked loop. Therefore, although the locking operation of the phase locked loop must be fast, a quick paging message can be received.

However, in the conventional mobile communication terminal, the phase locked loop data write method for controlling the phase locked loop uses a serial interface using a clock, data, and latch enable between the GPIO (General Purpose Input Output) of the modem and the PLL data. Is done. Write method is "Clock High Write-Data 1Bit Write-Clock Low Write-....." As shown in Table 1 below, the GPIO modem register is composed of one register in which five GPIOs used for other purposes other than the three PLL clocks, data, and PLL enable are bundled together.

Bit number 7 6 5 4 3 2 One 0 other GPIO other GPIO other GPIO PLL CLOCK PLL DATA PLL EN other GPIO other GPIO

Therefore, in order to write without affecting the current state of the other five GPIOs, it is necessary to check the GPIO status, take a mask, and write to the PLL GPIO. This delay affects the write time. To solve this, you can move other GPIOs to different registers, but this can't be done because there are not enough GPIOs. Or, by making a dedicated GPIO register for the phase-locked loop or adding a serial interface hardware for the phase-locked loop to the modem, there is a problem in that a terminal using an existing chip cannot detect quick paging.

Accordingly, an object of the present invention is to provide an apparatus and method for controlling a phase synchronization loop for receiving a quick paging message of a mobile communication terminal capable of detecting a quick paging message in an existing mobile communication terminal.

Another object of the present invention is to provide a phase synchronous loop control apparatus and method for writing phase synchronous loop data for controlling a phase synchronous loop to a phase synchronous loop using a chip select signal and a data bus.

The apparatus of the present invention for achieving the above objects; A phase locked loop control device for receiving a quick paging message of a mobile communication terminal, comprising: a control unit having a chip selector terminal, data bus lines, and a phase locked loop enable general purpose input / output (GPIO) terminal; And a phase synchronization loop having a clock terminal, a data terminal connected to one of the data bus lines, and a latch enable terminal connected to the phase synchronization loop enable general purpose input / output terminal.

The method of the present invention for achieving the above objects; A control unit having a chip selector terminal, data bus lines, and phase-locked loop general purpose input / output (GPIO) terminals; a clock terminal connected to the chip selector terminal; a data terminal connected to one of the data bus lines; Phase synchronous loop enable A general phase synchronous loop control method for receiving a quick paging message for a mobile communication terminal having a phase synchronous loop having a latch enable terminal connected to an input / output terminal. And turning on the temperature compensated crystal oscillator, enabling the chip selector terminal after the crystal oscillator is turned on, and controlling data for controlling the phase-locked loop by enabling the chip selector terminal. Writing to a memory allocated to the terminal; After bit features a yirueojim the control data stored in the memory according to the clock output from the chip selector terminals with a process of outputting to the data terminal of the phase-locked loop with said data bus line to a line.

1 is a diagram illustrating a general quick paging channel determination algorithm.

2 is a diagram illustrating a quick paging message offline demodulation timing diagram according to an embodiment of the present invention.

3 is a timing diagram illustrating a process of receiving an RF part offline quick paging message of FIG. 2;

4 shows an RF part tunic block;

5 illustrates a phase locked loop data structure.

6 is a timing diagram for quick paging according to an embodiment of the present invention.

7 is a diagram illustrating a connection relationship between a modem and a phase locked loop generator according to an exemplary embodiment of the present invention.

8 is a diagram illustrating a phase locked loop control method for receiving a quick paging message of a mobile communication terminal according to an embodiment of the present invention.

9 is a view showing experimental results of a general phase-locked loop control device.

10 is a view showing the experimental results in the phase-locked loop control apparatus according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

2 is a diagram illustrating a quick paging message offline demodulation timing diagram.

As illustrated in FIG. 2, a time point of turning on / off a temperature compensation crystal oscillator (TCXO) is performed when entering the idle sleep state and when exiting the idle sleep state. In order to match the Psuedorandom Noise (PN) state, the 26.67ms boundary is always used. In addition, one slot of the quick paging message is 80ms, and only when the quick paging symbol is transmitted as '1' 201, the temperature compensated crystal oscillator is operated out of the idle sleep state. The time interval 211 is a warm-up time for the temperature compensated crystal oscillator to perform an operation, and the time interval 213 is a transition state in which the temperature compensated crystal oscillator returns to the idle sleep state after the operation ends. As a warm down time, the temperature compensated crystal oscillator performs an effective operation only in the actual time interval 215. Two bit messages are input to one slot of the quick paging message, and only one bit message indicates '1', so that the temperature compensated crystal oscillator transitions back to the idle sleep state. That is, the sleep command 203 is generated because the paging channel does not need to be decoded as a result of the quick paging message detection. The re-acquisition process is performed off-line after storing the input in the RF part in a buffer.

Here, a process of receiving an offline quick paging message of the RF part will be described with reference to FIG. 3.

3 is a timing diagram illustrating a process of receiving an RF part offline quick paging message of FIG. 2. 3 illustrates an operation of the RF part in a timing diagram from an on point to an off point in order to receive a symbol of a quick paging message. First, when the temperature compensated crystal oscillator is turned on, its Warm Up time is 2ms, and the temperature compensated crystal oscillator operation is reported to the controller to generate CHIP * 8. Then, the RF part in the idle sleep state, that is, the receiver is turned on (311), and takes 2ms as a preparation time for the RF part to operate normally, thereby causing the receiver to transition to the standby state f. Then, the controller applies data to the phased loop lock (PLL) through the RF_tuning process 313 to control the phase locked loop to be locked. The time taken for the phase-locked loop to fully transition to the locked state is about 500u sec, and the intermediate frequency (IF) is about 1.5ms. At the same time, the gain is adjusted to allow the auto gain controller (AGC) to stabilize with a wide bandwidth (315). Here, the loop gain constant 73us is used. Further, in order to allow the automatic gain controller to stabilize with a narrow bandwidth, it uses a higher value, i.e., 392 u sec, than the case where the loop gain constant is stabilized to the wide bandwidth (317). As such, when the RF part for quick paging completes the preparation operation for the reception operation, quick paging symbol buffering is performed (319). That is, buffering the interval of the interval caution in which the quick paging symbol of the quick paging message is inserted. If the quick paging message is 4800 bps, 672 chips (546us) are stored, and if 2400k bps, 800 chip (650us) is stored. Save it. When the quick paging symbol buffering ends, the control unit turns off the power of the RF part so that the RF part transitions to the idle sleep state, and the time required is about 4 ms (321).

Here, the RF tuning process will be described with reference to FIG. 4.

4 is a diagram illustrating an RF part tuning block.

First, a dual phase locked loop (Dual PLL) is used for the RF tuning. That is, the dual phase synchronization loop is used to synchronize the radio frequency (RF) and the intermediate frequency (IF) of the RF part with the current frequency. The controller 100 transmits a command to the dual phase synchronization loop 102 to transition to the radio frequency and the intermediate frequency in order to synchronize synchronization with a frequency used as a radio frequency and an intermediate frequency. Here, the command transmitted by the controller 100 to the dual phase locked loop 102 includes three signals, that is, a clock CLK signal, a data DATA signal, and an LE signal. ) Transmits the command to the dual phase locked loop 100 a set number of times, for example, four times. The data signal structure of the command will be described below with reference to FIG. 5.

As such, when the dual phase locked loop 102 undergoes a lock process to transition to the radio frequency and the intermediate frequency according to the command of the controller 100, an RF voltage oscillator (VCO) 106 and an IF are performed. The voltage controlled oscillator 108 is to be oscillated at a radio frequency and an intermediate frequency, respectively.

5 is a diagram illustrating a phase locked loop data structure.

As described above with reference to FIG. 4, the speed of the lock process of the dual phase synchronization loop 102 depends on the clock speed of a clock signal of the command transmitted from the controller 100 to the dual phase synchronization loop 102. However, since the command transmitted from the controller 100 to the dual phase locked loop 102 is generated as current software data, the dual phase locked loop 102 receives the software generated command. The lock process takes a long time. This is because the reference clock of the controller 100 for generating the command uses a temperature compensated crystal oscillator in an idle sleep state. The frequency of the temperature compensated crystal oscillator is about 32.768KHz, and the time required to transmit the command is about 5.5ms, and thus the time required for RF tuning and the command to receive the quick paging symbol. There is a problem in that a quick paging symbol reception time is prolonged by adding time, that is, 5.5 ms. Thus, the time required for the controller 100 to transmit a command to the dual phase locked loop 102 should be minimized.

Thus, in an embodiment of the present invention, the control unit 100 does not generate the command transmitted to the dual phase lock loop 102 in hardware, but in software, and in hardware, a chip selector. Connect only the CS terminal and the data bus line to the phase locked loop 102.

The connection between the CS terminal, the data bus line and the phase synchronization loop will be described with reference to FIG.

In FIG. 7, a clock terminal of the phase locked loop 703 according to the present invention is connected to a chip selector terminal of the controller 701. The data terminal of the phase locked loop 703 is connected to any one of the data bus lines of the controller 701. In FIG. 7, the first (Data [0]) line of the data bus line is connected. This connects only one line to implement a serial interface. In addition, a latch enable terminal of the phase locked loop 703 is connected to a GPIO (PLL EN) terminal of the controller 701.

For example, the reference clock of the controller 100 is saved during the transmission of the command, and the reference clock is stopped when the command is transmitted to the dual phase synchronization loop 102. Here, for example, the reference clock uses 27 MHz or 10 MHz. This will be described in detail with reference to FIG. 6.

6 is a timing diagram for quick paging according to an embodiment of the present invention.

When the control unit 100 receives a signal for starting quick paging using the warmup_interrupt signal, the controller 100 operates a temperature compensated crystal oscillator, which is a reference clock of the terminal. Then, the temperature compensation crystal oscillator takes about 2m sec from warm up to normal operation, and after this time is given a Sleep / high signal so that the receiving end, i.e., the RF part starts to operate. do. At the same time, the reference clock of the controller 100 is operated and the dual phase locked loop 102 is loaded with data indicating a command, that is, a command to transition to a radio frequency and an intermediate frequency. After the command is loaded into the dual phase lock loop 102, the reference clock generation of the controller 100 is stopped. That is, it is possible to eliminate the terminal current consumed by configuring the data to be transmitted to the dual phase lock loop 102 in hardware to shorten the time required for data transmission.

8 is a diagram illustrating a phase locked loop control method for receiving a quick paging message of a mobile communication terminal according to an embodiment of the present invention. A description with reference to FIG. 8 is as follows.

First, in step 801, the controller 701 of the mobile terminal transitions to the sleep state. In the sleep state, the controller 701 periodically checks whether the quick paging test time is performed to perform the quick paging test at a predetermined time period. During the quick paging test time, the control unit 701 turns on the temperature compensated crystal oscillator in step 805, and proceeds to step 807 to enable the chip selector CS terminal. By enabling the chip selector terminal, the control data for controlling the phase-locked loop 703 is written in the memory region allocated to the chip selector terminal among the memory regions of the controller 701. The written data is output to the data terminal of the phase locked loop 703 through one of the data bus lines in accordance with the clock provided to the chip selector in step 809. Since the clock output from the chip selector terminal is about 100 times faster than the clock output from the GPIO (PLL Clock) terminal, the PLL control data can be written as fast as that. For example, the clock speed output through the GPIO (PLL Clock) terminal is 25KHz and the clock speed output through the CS terminal is 2.5MHz.

Experimental results according to the speed of the clock outputted through the GPIO (PLL Clock) terminal and the clock outputted through the CS terminal are shown in FIGS. 9 and 10, respectively.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention operates only a low frequency oscillator in an idle sleep state when receiving a quick paging message to minimize sleep current consumption, and also implements a command for receiving a quick paging message in hardware. It has the advantage of minimizing the sleep current consumption by reducing the time due to the delay. Therefore, the terminal standby time is minimized by minimizing the terminal current consumption.

Claims (2)

A phase locked loop control device for receiving a quick paging message of a mobile communication terminal, A control unit having a chip selector terminal and data bus lines and a phase locked loop enable general purpose input / output (GPIO) terminal; And a phase synchronizing loop having a clock terminal connected to the chip selector terminal, a data terminal connected to one of the data bus lines, and a latch enable terminal connected to the phase synchronization loop enable general purpose input / output terminal. Said device. A control unit having a chip selector terminal, data bus lines, and phase-locked loop general purpose input / output (GPIO) terminals; a clock terminal connected to the chip selector terminal; a data terminal connected to one of the data bus lines; A phase synchronous loop enable method comprising: a phase synchronous loop control method for receiving a quick paging message of a mobile communication terminal having a phase synchronous loop having a latch enable terminal connected to a general purpose input / output terminal; The process of turning on the temperature compensated crystal oscillator when the time for the quick paging test in the sleep state Enabling the chip selector terminal after the crystal oscillator is turned on; Writing control data for controlling the phase-locked loop to the memory allocated to the chip selector terminal by enabling the chip selector terminal; And after the control data is written, outputting control data stored in the memory to one of the data bus lines to the data terminal of the phase locked loop in accordance with a clock output from the chip selector terminal. .