KR20020061352A - Process-independent phase locked loop circuit capable of reducing locking time and locking control method thereof - Google Patents

Abstract

PURPOSE: A phase locked loop(PLL) circuit and locking control method therefor is provided to generate an output having an accurate frequency together with reducing a locking time independent of manufacturing process and temperature effects. CONSTITUTION: A PLL circuit includes a phase frequency detector(31) for detecting a phase difference by comparing a phase of feedback signal with that of a reference signal, an electron pump(32) for pumping electrons in response to the output signals from the phase frequency detector(31), a loop filter(15) for filtering the output signals from the electron pump(32), a voltage control oscillator(VCO)(34) for varying the frequency of the feedback signals in response to the output signals from the loop filter(15), a register(35) for storing the digital signals, a digital-to-analog(DA) converter(36), a lock detector(37) for determining by receiving the output signals from the phase frequency detector(31) whether or not the feedback signals are locked with the reference signals and an analog-to-digital(AD) converter(38). The DA converter(36) controls the voltage level of the output signals from the loop filter(15) by converting the digital signals stored in the register(35). The AD converter(38) supplies the digital signals by converting the output signals from the loop filter(15) into the digital signals, which is activated when the lock detector(37) outputs a signal representing a status of locking.

Description

Process-independent phase locked loop circuit capable of reducing locking time and locking control method regardless of the manufacturing process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly, to a phase locked loop circuit capable of generating an output having an accurate frequency while reducing a lock time irrespective of the manufacturing process and temperature. It is about a method.

The phase locked loop circuit compares a phase of a signal fed back from a voltage controlled oscillator (VCO) and synchronizes the phase thereof, and is used in various applications such as a communication system. Recently, with the development of semiconductor technology, a phase locked loop circuit is implemented as a semiconductor integrated circuit.

A conventional conventional phase-locked loop circuit includes a phase frequency detector (PFD) 11 and a phase frequency detector 11 for comparing phases of a reference signal fin and a feedback signal fout as shown in FIG. 1. Charge pump 13 for pumping charge in response to the output signals Φi and Φo of the loop filter, and a loop filter 15 for filtering the output signal po of the charge pump 13. And a voltage controlled oscillator (VCO) 17 which varies the frequency of the feedback signal fout in response to the output signal of the loop filter 15, that is, the control voltage lo.

However, the phase locked loop circuit shown in FIG. 1 has a disadvantage in that it takes a long time to be locked, and a phase locked loop circuit as shown in FIG. 2 is used to reduce the lock time. The phase-locked loop circuit shown in FIG. 2 converts a register 18 that stores an externally applied digital signal ds and a digital signal ds stored in the register 18 into an analog signal to convert the loop filter 19 into an analog signal. A DA converter (Digital to Analog Converter) for adjusting the voltage level of the output signal lo is further provided.

However, while the phase locked loop circuit shown in FIG. 2 has an advantage of short lock time, it is difficult to apply an accurate value because the user needs to predict the digital signal ds directly from the outside. In other words, since the voltage controlled oscillator 17 is highly influenced by the manufacturing process and temperature, it is difficult for the user to accurately predict the digital signal ds value.

Accordingly, the present invention has been made in an effort to provide a phase locked loop circuit capable of generating an output having an accurate frequency while reducing lock time irrespective of the manufacturing process and temperature.

Another object of the present invention is to provide a locking control method of a phase locked loop circuit capable of generating an output having an accurate frequency while reducing the lock time irrespective of the manufacturing process and the influence of temperature.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional phase locked loop circuit.

2 is a block diagram of another conventional phase locked loop circuit.

3 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention.

The phase locked loop circuit according to the present invention for achieving the above technical problem is characterized by comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a resistor, a DA converter, a lock detector, and an AD converter.

The phase frequency detector detects a phase difference by comparing a phase of a reference signal and a feedback signal, and the charge pump pumps charge in response to output signals of the phase frequency detector. The loop filter filters the output signal of the charge pump, and the voltage controlled oscillator varies the frequency of the feedback signal in response to the output signal of the loop filter.

The register stores a digital signal, and the DA converter converts the digital signal stored in the register into an analog signal to adjust the voltage level of the output signal of the loop filter. The lock detector receives the output signals of the phase frequency detector to determine whether the reference signal and the feedback signal are locked, and the AD converter is activated when the lock detector outputs a signal indicating that the lock detector is locked. A digital signal is converted to provide the converted signal as the digital signal.

According to a preferred embodiment, the initial value of the digital signal stored in the register is applied externally. The DA converter is initially activated at power on and deactivated after a predetermined time, and the AD converter is deactivated during activation of the DA converter. The DA converter is also deactivated during activation of the AD converter.

According to another aspect of the present invention, there is provided a locking control method of a phase locked loop circuit including a phase frequency detector detecting a phase difference by comparing a phase of a reference signal and a feedback signal, and responding to output signals of the phase frequency detector. Locking of a phase locked loop circuit including a charge pump for pumping charge, a loop filter for filtering an output signal of the charge pump, and a voltage controlled oscillator for varying a frequency of the feedback signal in response to an output signal of the loop filter. A control method comprising: applying and storing an initial value of a digital signal from an external source; converting the digital signal into an analog signal to adjust a voltage level of an output signal of the loop filter; an output signal of the phase frequency detector Determining whether to lock the reference signal and the feedback signal And when the reference signal and the feedback signal are locked, digitally converting the output signal of the loop filter and providing the converted signal as the digital signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram of a phase locked loop circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, a phase locked loop circuit according to a preferred embodiment of the present invention includes a phase frequency detector 31, a charge pump 32, a loop filter 33, a voltage controlled oscillator 34, and a resistor 35. And a DA converter 36, a lock detector 37, and an AD converter 38.

The phase frequency detector 31 detects the phase difference by comparing the phase of the reference signal fin and the feedback signal fout, and the charge pump 32 is connected to the output signals Φ i and Φ o of the phase frequency detector 31. In response to pumping charge. The loop filter 33 composed of the capacitors C1 and C2 and the resistor R filters the output signal po of the charge pump 32, and the voltage controlled oscillator 34 outputs the output signal of the loop filter 33. In response to lo, the frequency of the feedback signal fout is varied.

The register 35 stores the digital signal ds output from the AD converter 38, and the DA converter 36 converts the output signal rs of the register into an analog signal to output the signal of the loop filter 33. Adjust the voltage level at (lo). The initial value int of the digital signal stored in the register 35 is externally applied by the user.

The lock detector 37 receives the output signals phi i and phi o of the phase frequency detector 31 to determine whether the reference signal fin and the feedback signal fout are locked, and the AD converter 38 determines the lock detector. It is activated when the signal det (37) is locked and receives the output signal lo of the loop filter 33 and digitally converted to provide the converted signal as a digital signal ds.

Meanwhile, the DA converter 36 is initially configured to be activated at power on and deactivated after a predetermined time, and the AD converter 38 is configured to be deactivated during the activation of the DA converter 36. The DA converter 36 is also configured to be deactivated during the activation of the AD converter 38.

Hereinafter, a locking control method of a phase locked loop circuit according to the present invention will be described with reference to FIG. 3.

First, when the user applies an initial value (int) of the digital signal from the outside, it is stored in the register 35. When the power is initially turned on, the voltage level of the output signal lo of the loop filter 33 is 0 volts. After that, the DA converter 36 is activated and the DA converter 36 is operated according to the initial value int stored in the register 35 so that the voltage level of the output signal lo of the loop filter 33 is appropriately adjusted. At this time, the AD converter 38 is deactivated while the DA converter 36 is operating. After a certain time, the DA converter 36 is deactivated, and thus the phase locked loop circuit is normally operated.

After the phase locked loop circuit operates normally, the lock detector 37 receives the output signals Φ i and Φ o of the phase frequency detector 31 to determine whether the reference signal fin and the feedback signal fout are locked. do. When the signal det indicating that the reference signal fin and the feedback signal fout are locked is output from the lock detector 37, the AD converter 38 is activated to receive the output signal lo of the loop filter 33 and receive the digital signal. Convert. The digitally converted signal is provided to and stored in the register 35 as a digital signal ds.

After a certain time, the AD converter 38 is deactivated again. At this time, since the phase locked loop circuit is locked, the voltage level of the output signal lo of the loop filter 33 is not changed. Therefore, even if the AD converter 38 is activated, the value of the digital signal ds provided to the register 35 remains unchanged.

As described above, the value of the digital signal ds finally stored in the register 35 is a value reflecting the influence of the manufacturing process and the temperature of the voltage controlled oscillator 17 as compared with the initial value int applied from the outside. More precise values. Also, the time for which the DA converter 36 and the AD converter 38 operate is generally short.

Therefore, in the phase-locked loop circuit and the locking control method according to the present invention described above, an output having an accurate frequency can be generated while the locking time can be reduced regardless of the manufacturing process and the influence of temperature.

The best embodiment has been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the phase-locked loop circuit and the locking control method thereof according to the present invention can generate an output having an accurate frequency while reducing the lock time regardless of the manufacturing process and the influence of temperature.

Claims (6)

A phase frequency detector for detecting a phase difference by comparing phases of a reference signal and a feedback signal; A charge pump pumping charge in response to output signals of the phase frequency detector; A loop filter for filtering the output signal of the charge pump; A voltage controlled oscillator for varying a frequency of the feedback signal in response to an output signal of the loop filter; A register for storing a digital signal; A DA to digital converter converting the digital signal stored in the register into an analog signal to adjust a voltage level of the output signal of the loop filter; A lock detector configured to receive output signals of the phase frequency detector to determine whether the reference signal and the feedback signal are locked; And And an AD converter (Analog to Digital Converter) which is activated when the lock detector outputs the locked signal and digitally converts the output signal of the loop filter to provide the converted signal as the digital signal. Loop circuit. The phase locked loop circuit of claim 1, wherein an initial value of the digital signal stored in the register is externally applied. 2. The phase-lock loop of claim 1, wherein the DA converter is initially activated at power on and deactivated after a predetermined time. 4. The phase locked loop circuit of claim 3, wherein the AD converter is deactivated during activation of the DA converter. The phase locked loop circuit of claim 1, wherein the DA converter is deactivated during activation of the AD converter. A phase frequency detector for detecting a phase difference by comparing a phase of a reference signal and a feedback signal, a charge pump pumping charge in response to the output signals of the phase frequency detector, a loop filter filtering the output signal of the charge pump, and the A locking control method for a phase locked loop circuit having a voltage controlled oscillator for varying a frequency of the feedback signal in response to an output signal of a loop filter, Storing an external initial value of a digital signal; Adjusting the voltage level of the output signal of the loop filter by converting the digital signal into an analog signal; Determining whether the reference signal and the feedback signal are locked by receiving output signals of the phase frequency detector; And when the reference signal and the feedback signal are locked, digitally converting the output signal of the loop filter and providing the converted signal as the digital signal.