KR20020061062A - Method for forming sti layer of the semiconductor device - Google Patents

Method for forming sti layer of the semiconductor device Download PDF

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Publication number
KR20020061062A
KR20020061062A KR1020010001842A KR20010001842A KR20020061062A KR 20020061062 A KR20020061062 A KR 20020061062A KR 1020010001842 A KR1020010001842 A KR 1020010001842A KR 20010001842 A KR20010001842 A KR 20010001842A KR 20020061062 A KR20020061062 A KR 20020061062A
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South Korea
Prior art keywords
trench
insulating film
substrate
gap fill
insulation film
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KR1020010001842A
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Korean (ko)
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임근식
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동부전자 주식회사
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Priority to KR1020010001842A priority Critical patent/KR20020061062A/en
Publication of KR20020061062A publication Critical patent/KR20020061062A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

PURPOSE: A method for manufacturing a trench device isolation film of a semiconductor device is provided to improve insulation between device isolation film and improve separation quality by using overhang having lower step coverage. CONSTITUTION: An insulation film pattern defining the trench region a pad oxide film are successively formed on the substrate(10). The trench is formed by etching the substrate exposed by an insulation pattern. A gap fill insulation film is deposited on the substrate forming the trench. The upper part of the trench is closed and filled with the air by the gap fill insulation film due to the over hang deposition occurred on the upper corner of the trench. The gap fill insulation film is deposited on the insulation film pattern and is polished by a CMP process until the insulation film pattern(30') is exposed. Then, the device insulation film comprising the air(60) and the polished gap fill insulation film(50') is formed within the substrate.

Description

반도체장치의 트렌치 소자분리막 제조방법{METHOD FOR FORMING STI LAYER OF THE SEMICONDUCTOR DEVICE}METHODS FOR FORMING STI LAYER OF THE SEMICONDUCTOR DEVICE

본 발명은 반도체 제조방법에 관한 것으로서, 특히 반도체장치의 소자간 분리를 위한 STI(Shallow Trench Isolation) 공정시 트렌치구조의 소자분리막의 절연특성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method, and more particularly, to a technique capable of improving insulation characteristics of a device isolation film having a trench structure during a shallow trench isolation (STI) process for device isolation between semiconductor devices.

최근, 반도체장치의 제조기술의 발달과 메모리소자의 응용분야가 확장되어 감에 따라 대용량의 메모리소자에 대한 연구 및 개발이 급속도로 발전되고 있다.이러한 메모리소자의 집적도 증가에 따른 미세공정기술을 기본으로 한 메모리셀 연구에 의해 추진되어 오고 있다. 메모리소자의 미세화 기술에 있어서, 소자를 집적화하기 위하여 소자 사이를 분리하는 소자분리막의 축소 기술이 중요한 항목중의 하나로 대두되었다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, research and development of large-capacity memory devices have been rapidly developed. It has been promoted by research on memory cells. In the technology of miniaturization of memory devices, in order to integrate devices, a technology of reducing device isolation layers that separate devices is emerging as one of important items.

종래의 소자분리기술로는 반도체기판상에 두꺼운 산화막을 선택적으로 성장시켜 소자분리막을 형성하는 로커스(LOCal Oxidation of Silicon: 이하 LOCOS라 함) 기술이 있었는데, 이 기술은 소자분리막의 측면확산 및 분리막을 원하지 않는 부분에 산화막이 형성되는 것에 의해 소자분리막의 폭을 감소시키는데 한계가 있었다. 그래서, 소자설계치수가 서브미크론(submicron) 이하로 줄어드는 대용량의 메모리소자에 있어서는 LOCOS 기술의 적용이 불가능하기 때문에 새로운 소자분리 기술이 필요하게 되었다.Conventional device isolation techniques include LOCal Oxidation of Silicon (LOCOS), which selectively grows thick oxide films on semiconductor substrates to form device isolation films. There was a limit to reducing the width of the device isolation film by forming an oxide film in an unwanted portion. Therefore, the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less, so a new device isolation technology is required.

이에 등장한 트렌치 구조의 소자분리 기술은 반도체기판에 식각 공정으로 트렌치를 형성하고 트렌치를 절연물질로 매립함으로써 LOCOS에 비해 소자분리영역의 축소가 가능해졌다.The trench isolation device isolation technology allows a device isolation region to be reduced in comparison with LOCOS by forming a trench in an semiconductor substrate through an etching process and filling the trench with an insulating material.

최근에는 트렌치 구조의 소자분리 기술이 발전된 STI(Shallow Trench Isolation) 공정이 자주 사용되는데, 이 공정은 반도체기판에 일정 깊이를 갖는 트렌치를 형성하고서 이 트렌치내에 절연물질을 매립한 후에 평탄화 공정으로서 화학적기계적연마(Chemical Mechanical Polishing)로 트렌치에만 절연막이 남도록 식각하는 것이다.Recently, the shallow trench isolation (STI) process, which is an advanced device isolation technology in trench structures, is frequently used. This process forms a trench having a certain depth in a semiconductor substrate, and fills an insulating material in the trench, and then chemically mechanically processes it. Chemical mechanical polishing is used to etch the insulating film only in the trench.

그런데, 반도체 소자의 디자인 룰이 미세해지면서 이에 따른 STI 공정에서의트렌치 에스펙트 비율(aspect ratio)도 커지게 된다. 이에, 종래 기술에서는 트렌치 내부를 갭필용 절연막으로서 산화막으로 매립할 때 주로 갭필(gap-fill) 특성이 좋은 HDP-CVD(High Density Plasma Chemical Vapor Deposition)법을 이용하게 된다. 근데, HDP-CVD법에 의한 트렌치에 산화막 갭필 공정은 증착(deposition)과 건식(dry etch)공정이 동시에 이루어지면서 점진적으로 막이 증착되기 때문에 갭필 특성이 좋아진다. 이러한 HDP-CVD법에 의한 갭필 공정은 생산성이 다른 공정에 비해 낮고 장비 또한 식각 기능을 갖추어야하기 때문에 장비의 구조가 복잡하면서 매우 고가이다.However, as the design rule of the semiconductor device becomes finer, the trench aspect ratio in the STI process also increases. Therefore, in the prior art, when filling the trench inside with an oxide film as an insulating film for gap fill, a high density plasma chemical deposition (HDP-CVD) method having a good gap fill property is mainly used. However, the oxide gap gap fill process in the trench by the HDP-CVD method has a good gap fill characteristic because a film is gradually deposited while the deposition and dry etch processes are performed at the same time. Since the gap fill process by the HDP-CVD method has low productivity compared to other processes and the equipment must also have an etching function, the structure of the equipment is complicated and very expensive.

그럼에도 불구하고 트렌치의 갭필 공정시 증착 및 식각공정을 동시에 진행하는 HDP-CVD 방법을 사용하는 이유는 보이드(void) 또는 균열(seam)이 일어나지 않고 갭필 특성을 향상시키기 위함이다. 만약 트렌치에 갭필된 막에 보이드 또는 균열이 발생하게 되면, 화학적기계적 연마시 보이드 또는 균열이 발생된 부분으로 화학용액이 침투하게 되고 결국, 소자분리막의 수율을 저하시키는 문제점이 있었다.Nevertheless, the reason for using the HDP-CVD method for simultaneously performing the deposition and etching processes in the gap fill process of the trench is to improve the gap fill characteristics without voids or cracks. If voids or cracks are generated in the gap-filled film in the trench, the chemical solution penetrates into the voids or cracks generated during chemical mechanical polishing, resulting in a decrease in yield of the device isolation film.

본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 기판에 트렌치를 형성하고 절연막으로 트렌치를 갭필하되, 스텝 커버리지(step coverage)가 낮은 오버행(overhang) 현상을 이용하여 트렌치 내부를 제외한 트렌치 상부 및 기판 표면에만 절연막을 증착함으로써 트렌치의 내부 일부가 공기로 채워진 소자분리막을 통해 소자간 절연 및 분리특성을 향상시킬 수 있는 반도체장치의 트렌치 소자분리막 제조방법을 제공하고자 한다.An object of the present invention is to form a trench in the substrate and gap fill the trench with an insulating film in order to solve this problem of the prior art, but using the overhang phenomenon of low step coverage (overhang), except for the trench upper portion And a method of manufacturing a trench device isolation film for a semiconductor device capable of improving insulation and isolation characteristics between devices through device isolation films in which a portion of the inside of the trench is filled with air by depositing an insulating film only on a substrate surface.

이러한 목적을 달성하기 위하여 본 발명은 반도체기판에 소자간 분리를 위한 트렌치 구조의 소자분리막을 제조함에 있어서, 기판에 트렌치 영역을 정의하는 절연막 패턴을 형성하는 단계와, 절연막 패턴에 의해 드러난 기판을 식각하여 기판내에 소정 깊이의 트렌치를 형성하는 단계와, 트렌치가 형성된 기판에 화학기상증착법으로 갭필 절연막을 증착하되, 트렌치 상부 모서리부분에서 오버행이 이루어지도록 증착하여 트렌치의 내부를 공기로 채우고 트렌치 상부 및 절연막 패턴 표면을 갭필 절연막으로 덮어지게 하는 단계와, 절연막 패턴표면이 드러나도록 갭필 절연막을 평탄화하여 기판의 트렌치내에 공기 및 절연막으로 이루어진 소자분리막을 형성하는 단계와, 절연막 패턴을 제거하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming an isolation layer having a trench structure for isolation between devices on a semiconductor substrate, forming an insulating layer pattern defining a trench region on the substrate, and etching the substrate exposed by the insulating layer pattern. Forming a trench of a predetermined depth in the substrate, and depositing a gapfill insulating film on the substrate on which the trench is formed by chemical vapor deposition, and depositing an overhang at an upper corner of the trench to fill the inside of the trench with air, Covering the patterned surface with a gapfill insulating film, planarizing the gapfill insulating film to expose the insulating film pattern surface, forming a device isolation film made of air and an insulating film in the trench of the substrate, and removing the insulating film pattern.

도 1 내지 도 5는 본 발명의 일 실시예에 따른 반도체장치의 트렌치 소자분리막 제조 방법을 설명하기 위한 공정 순서도이다.1 to 5 are flowcharts illustrating a method of manufacturing a trench isolation layer in a semiconductor device according to an embodiment of the present invention.

＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

10 : 반도체기판 20 : 패드 산화막10 semiconductor substrate 20 pad oxide film

30 : 절연막 패턴 40 : 트렌치30 insulating film pattern 40 trench

50 : 갭필 절연막 52 : 오버행50 gap fill insulating film 52 overhang

60 : 공기 ISO : 소자분리막60: air ISO: device separator

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 5는 본 발명의 일 실시예에 따른 반도체장치의 트렌치 소자분리막 제조 방법을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 일실시예의 제조 방법은 다음과 같다.1 to 5 are flowcharts illustrating a method of manufacturing a trench isolation layer of a semiconductor device according to an embodiment of the present invention. Referring to this, a manufacturing method of an embodiment of the present invention is as follows.

도 1에 도시된 바와 같이, 반도체기판으로서 실리콘기판(10) 상부에 트렌치 영역을 정의하는 절연막 패턴(30)을 형성한다. 이때, 절연막 패턴(30)은 갭필용 절연막과 식각 선택성이 있는 물질로 하되, 주로 질화막을 사용한다. 그리고, 절연막 패턴(30)을 형성하기 전에, 기판(20)과 절연막 패턴(30) 사이에서 스트레스 및 트렌치 모서리 식각을 방지하는 패드 산화막(20)을 추가한다. 즉, 이 제조 공정은 기판(10) 상부에 패드 산화막 및 절연막을 순차 적층한다. 그리고, 트렌치 마스크를 이용한 사진 및 건식 식각 공정을 진행하여 적층된 절연막 및 패드 산화막(30,20)을 패터닝한다.As shown in FIG. 1, an insulating film pattern 30 defining a trench region is formed on the silicon substrate 10 as a semiconductor substrate. At this time, the insulating film pattern 30 is made of a material having an etching selectivity and the gap-fill insulating film, mainly using a nitride film. Before forming the insulating film pattern 30, a pad oxide film 20 is added between the substrate 20 and the insulating film pattern 30 to prevent stress and trench edge etching. That is, in this manufacturing process, the pad oxide film and the insulating film are sequentially stacked on the substrate 10. Then, the photolithography and the dry etching process using the trench mask are performed to pattern the stacked insulating films and the pad oxide films 30 and 20.

그리고, 상기 절연막 패턴(30)에 의해 드러난 기판(10)을 소정 깊이로 식각하여 트렌치(40)를 형성한다. 이때, 트렌치(40)의 깊이는 적용 소자의 디자인 룰에 따라 차이가 있으며 본 실시예에서는 약 2000Å∼4000Å으로 한다.In addition, the trench 10 is formed by etching the substrate 10 exposed by the insulating layer pattern 30 to a predetermined depth. At this time, the depth of the trench 40 is different depending on the design rules of the application element, and in this embodiment, it is about 2000 kPa to 4000 kPa.

도 2에 도시된 바와 같이, 트렌치(40)가 형성된 기판에 화학기상증착법(Chemical Vapor Deposition)으로 갭필 절연막(50)을 증착한다. 이때, 갭필 절연막(50)은 산화물질로 증착하되, 증착 비율을 높여서 트렌치 상부 모서리부분에서 오버행(52)이 이루어지도록 한다. 예를 들면, 상기 증착 공정은 원료 가스로서 SiH4또는 SHi2Cl2및 N2O 가스를 흘리고 챔버의 증착 온도를 600℃이상으로 하며 압력을 2Torr이하로 하는데, 갭필 절연막(50)이 증착될 때 막의 스텝 커버리지(step coverage)가 저하되어 트렌치 상부의 모서리 부분에서 오버행(50)이 이루어지도록 증착 가스의 플로우 비율(flow rate)을 높이거나, 증착 온도 또는 압력을 높이는 것이 바람직하다.As shown in FIG. 2, a gap fill insulating film 50 is deposited on the substrate on which the trench 40 is formed by chemical vapor deposition. At this time, the gap fill insulating film 50 is deposited in an oxide material, so that the overhang 52 is formed at the upper edge portion of the trench by increasing the deposition rate. For example, the deposition process flows SiH 4 or SHi 2 Cl 2 and N 2 O gas as the source gas, the deposition temperature of the chamber is 600 ° C. or more, and the pressure is 2 Torr or less. When the step coverage of the film is lowered, it is desirable to increase the flow rate of the deposition gas or to increase the deposition temperature or pressure so that the overhang 50 is formed at the corner portion of the upper portion of the trench.

이러한 증착 공정을 계속 진행하여 도 3 및 도 4에 도시된 바와 같이, 트렌치(40) 상부 모서리 부분에서 발생된 오버행 증착에 의해 트렌치의 내부가 공기(60)로 채워지면서 트렌치 상부는 갭필 절연막(50)에 의해 막혀진다. 그리고, 절연막 패턴(30) 상부에는 소정 두께의 갭필 절연막(50)이 증착된다.3 and 4, the inside of the trench is filled with air 60 by the overhang deposition generated in the upper corner portion of the trench 40, and the upper portion of the trench is filled with the gap fill insulating film 50. Blocked by). A gap fill insulating film 50 of a predetermined thickness is deposited on the insulating film pattern 30.

그 다음, 도 5에 도시된 바와 같이 상기 결과물에 증착된 갭필 절연막(50)을 평탄화 공정으로서 CMP로 절연막 패턴(30) 표면이 드러날 때까지 연마한다. 이로 인해, 절연막 패턴(30') 상부의 갭필 절연막(50)이 모두 제거되고, 기판의 트렌치내에는 절연 상수가 1인 공기(60)와 표면이 연마된 갭필 절연막(50')으로 이루어진 소자분리막(ISO)이 형성된다. 이때, 도면 부호 30'은 CMP 공정시 연마된 절연막 패턴을 나타낸 것이다.Next, as shown in FIG. 5, the gap fill insulating film 50 deposited on the resultant is polished until the surface of the insulating film pattern 30 is exposed by CMP as a planarization process. As a result, all of the gap fill insulating film 50 on the insulating film pattern 30 'is removed, and the device isolation film including air 60 having an insulating constant of 1 and a gap-filled insulating film 50' polished on the surface of the substrate trench. (ISO) is formed. At this time, reference numeral 30 'represents an insulating film pattern polished during the CMP process.

그리고나서, 도면에 도시하지는 않았지만 절연막 패턴(30') 및 패드 산화막(20)을 제거하여 본 발명의 소자분리 공정을 완료한다. 이때, 절연막 패턴(30')인 질화막은 인산용액을 이용하여 제거하고, 패드 산화막(20)은 세정공정으로 제거한다.Then, although not shown in the drawing, the insulating film pattern 30 'and the pad oxide film 20 are removed to complete the device isolation process of the present invention. At this time, the nitride film, which is the insulating film pattern 30 ', is removed using a phosphoric acid solution, and the pad oxide film 20 is removed by a cleaning process.

그러므로, 본 발명의 트렌치 구조의 소자분리막 제조방법은 트렌치 내부에 공기를 채워넣고 트렌치 상부만을 화학적기상증착법(CVD)에 의한 갭필 절연막으로 매립함으로써 소자분리막의 절연 특성을 높일 수 있다.Therefore, in the method of manufacturing a device isolation film having a trench structure according to the present invention, the insulating property of the device isolation film can be improved by filling air in the trench and filling only the upper portion of the trench with a gap fill insulating film by chemical vapor deposition (CVD).

이상 설명한 바와 같이, 본 발명의 트렌치구조의 소자분리막은 스텝 커버리지가 나쁜 오버행 현상을 이용하여 트렌치 내부에는 절연상수가 1인 공기가 채워지고 트렌치 상부에만 갭필 절연막이 채워져 형성된 것으로써 소자간 절연특성이 향상된다.As described above, the device isolation film of the trench structure of the present invention is formed by filling the inside of the trench with an insulating constant of 1 and filling the gap fill insulating layer only in the trench by using an overhang phenomenon with poor step coverage. Is improved.

따라서, 본 발명은 종래 기술과 같이 고가의 HDP-CVD 장비를 이용하지 않는 대신에 일반 CVD 장비를 이용하여 절연특성이 높은 소자분리막을 형성할 수 있어소자의 생산성을 높일 수 있다.Therefore, the present invention can form a device isolation film having high insulation characteristics by using general CVD equipment instead of using expensive HDP-CVD equipment as in the prior art, thereby increasing device productivity.

한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

Claims (2)

반도체기판에 소자간 분리를 위한 트렌치 구조의 소자분리막을 제조함에 있어서,In manufacturing a device isolation film of a trench structure for separation between devices on a semiconductor substrate, 상기 기판에 트렌치 영역을 정의하는 절연막 패턴을 형성하는 단계;Forming an insulating layer pattern defining a trench region in the substrate; 상기 절연막 패턴에 의해 드러난 기판을 식각하여 상기 기판내에 소정 깊이의 트렌치를 형성하는 단계;Etching a substrate exposed by the insulating film pattern to form a trench having a predetermined depth in the substrate; 상기 트렌치가 형성된 기판에 화학기상증착법으로 갭필 절연막을 증착하되, 상기 트렌치 상부 모서리부분에서 오버행이 이루어지도록 증착하여 상기 트렌치의 내부를 공기로 채우고 상기 트렌치 상부 및 절연막 패턴 표면을 갭필 절연막으로 덮어지게 하는 단계;Depositing a gapfill insulating film on the substrate on which the trench is formed by chemical vapor deposition, and depositing an overhang at an upper corner of the trench to fill the inside of the trench with air and covering the trench upper surface and the insulating film pattern surface with a gapfill insulating film step; 상기 절연막 패턴표면이 드러나도록 상기 갭필 절연막을 평탄화하여 상기 기판의 트렌치내에 공기 및 절연막으로 이루어진 소자분리막을 형성하는 단계; 및Planarizing the gap fill insulating film to expose the insulating film pattern surface to form an isolation layer formed of air and an insulating film in a trench of the substrate; And 상기 절연막 패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 트렌치 소자분리막 제조방법.And removing the insulating film pattern. 제 1항에 있어서, 상기 갭필 절연막의 증착 공정은 증착 대상의 원료 가스의 플로우 비율을 높이거나, 증착 온도 또는 압력을 높이는 것을 특징으로 하는 반도체장치의 트렌치 소자분리막 제조방법.The method of claim 1, wherein the deposition process of the gap fill insulating film increases a flow rate of a source gas to be deposited, or increases a deposition temperature or a pressure.
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KR100856614B1 (en) * 2006-12-11 2008-09-03 동부일렉트로닉스 주식회사 Method for forming sti in semiconductor device and its structure
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KR100856614B1 (en) * 2006-12-11 2008-09-03 동부일렉트로닉스 주식회사 Method for forming sti in semiconductor device and its structure
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