KR20020060007A - Image data processing apparatus - Google Patents

Abstract

PURPOSE: A device for processing image data is provided to process high frequency image signals as well as low frequency image signals, and to process analog and digital image signals having various formats. CONSTITUTION: A first signal processing part samples image signals inputted through an input port in compliance with a first sampling clock pattern, and converts the sampled image signals into first digital signals. A second signal processing part samples image signals inputted through the input port in compliance with a second sampling clock pattern set differently from the first sampling clock pattern, and converts the sampled image signals into second digital signals. A signal mixing part mixes the first and second digital signals, to output generated image data. A main controller(30) controls the first and second signal processing parts to be operated at a dual mode for sampling inputted image signals, if the inputted image signals are over a set reference frequency. And the main controller controls one of the first and second signal processing parts to be operated at a single mode for sampling inputted image signals, if the inputted image signals are under a set reference frequency.

Description

Image data processing apparatus

The present invention relates to an image data processing apparatus, and more particularly, to an image data processing apparatus applied to a high resolution display device operating at a high frequency.

BACKGROUND ART Research has been continued for displaying images with more clear image quality in display apparatuses that input and display image signals from televisions, videos, and computers.

Such high resolution display devices include UXGA (Ultra eXtended Graphics Array), W-UXGA and QXGA, and these high resolution display devices operate at a high frequency exceeding 200 MHz.

However, the image data processing apparatus, which is applied to a display device and includes an analog digital converter (ADC) and an IC, has a frequency of up to 150 MHz as a sampling clock.

1 is a block diagram of a conventional image data processing apparatus.

As shown in the drawing, the conventional image data processing apparatus has a video synchronization separator 1 for separating horizontal and vertical syncs, and locks the input horizontal syncs, and the number of clocks and phase information divided from the main processor 7. PLL (3) for receiving the clock and generating the clock, ADC (Analog Digital Converter) (2) for sampling the input video signal to the clock output from the PLL (3), and the image converted digitally from the ADC (2) A data catcher (4) for extracting a signal to the PLL clock, a course controller (5) for determining the total number of horizontals with the data output from the data catcher and the PLL clock, and a fine for determining the exact sampling position of the screen to adjust the phase. The main controller 7 which receives the data input from the control unit 6, the course control unit and the fine control unit and transmits the number of clocks and the phase to the PLL, and the data and the clock output from the data catch unit It is composed of a signal combining unit 8 which generates and outputs the image.

However, such a conventional image data processing apparatus does not include a digital video interface for directly inputting a digital video signal from an external device, and thus can process only an image input through analog.

In addition, since there is only one ADC that samples an analog video signal and converts it into a digital signal, it is necessary to sample all of the signals input by one ADC.

However, since the operating frequency of the ADC has a limit, when the image data processing apparatus is applied to a high resolution display device, there is a problem that the display device cannot operate at the sampling frequency required by the display device.

Accordingly, an object of the present invention is to provide an image data processing apparatus capable of processing not only a low frequency video signal but also a high frequency video signal.

Another object of the present invention is to provide an image data processing apparatus capable of processing analog and digital video signals of various formats.

1 is a block diagram of a conventional image data processing apparatus.

2 is a block diagram of an image data processing apparatus according to a first embodiment of the present invention.

3A is a waveform diagram in which the first ADC 12 and the second ADC 13 sample the input signal in the dual mode, and FIG. 3B is a waveform diagram in which the first ADC 12 samples the input signal in the single mode.

4 is a block diagram of an image data processing apparatus according to a second embodiment of the present invention.

5 is a block diagram of the signal synthesis unit of FIGS. 2 and 4.

* Explanation of symbols for main parts of the drawings

11, 31: Video synchronization separator 12, 32: First analog-to-digital converter

13, 33: 1PLL 14, 34: 2nd analog-to-digital converter

15, 35: 2PLL 36: 1DVI decoder

37: 2nd DVI decoder 38: 1st multiplexer

39: second multiplexer 40: third multiplexer

41: fourth multiplexer 24, 44: first data extracting unit

25, 45: second data extraction section 26, 46: first course control section

27, 47: first fine control unit 28, 48: second coarse control unit

29, 49: second fine control unit 10, 30: main controller

20, 51: signal synthesis unit

In order to achieve the above object, an image data processing apparatus of a display apparatus, comprising: a first signal processor for sampling an image signal input through an input port according to a first sampling clock pattern and converting the image signal into a first digital signal; A second signal processor configured to sample an image signal input through an input port and convert the image signal into a second digital signal according to a second sampling clock pattern different from the first sampling clock pattern; and the first digital signal and the second digital signal. And a signal synthesizer configured to output image data generated by synthesizing the signals.

In order to achieve the above object, an image data processing apparatus of a display apparatus, comprising: a first digital signal processing unit for extracting and decoding processing at a first interval set for a digital video signal input through an input port; A second digital signal processor configured to extract and decode a digital image signal input through an input port at a second interval that is staggered from the first interval; and output from the first digital signal processor and the second digital signal processor. And a signal synthesizer configured to output image data generated by synthesizing a signal.

The image data processing apparatus includes: a first signal processor configured to sample an image signal input through an input port according to a first sampling clock pattern and convert the image signal into a first digital signal; And a second signal processor configured to sample the image signal input through the input port and convert the image signal into a second digital signal according to a second sampling clock pattern intersected with the first sampling clock pattern. It is preferable to output image data generated by further synthesizing the signals output from the signal processor and the second signal processor.

An image data processing apparatus according to preferred embodiments of the present invention having such a configuration will be described in detail with reference to the drawings.

First embodiment

2 is a block diagram of an image data processing apparatus according to a first embodiment of the present invention.

As shown, the image data processing apparatus according to the first embodiment of the present invention includes an image synchronization separator 11, a first analog / digital converter 12, a first PLL 13, and a second analog / digital converter ( 14) the second PLL 15, the first data extracting unit 24, the second data extracting unit 25, the first coarse control unit 26, the first fine control unit 27, and the second coarse control unit 28; And a second fine control unit 29, a main controller 10, and a signal synthesizing unit 20.

The image synchronization separator 11 inputs an image signal through an input port, separates the horizontal and vertical synchronization signals H_SYNC and V_SYNC, and separates the horizontal synchronization signal H_SYNC into a first phase-locked loop (PLL). 12) and to the second PLL 15.

The first PLL 13 generates a clock locked to the horizontal synchronization signal of the input signal based on the number of horizontal clocks and the phase information applied from the main controller 10 and outputs the clock to the first ADC 13.

The first ADC 13 inputs an image signal from an external device through an input port, and converts the image signal into a digital signal by the clock of the first PLL 12.

The second PLL unit 14 generates a clock locked to the horizontal synchronous signal H_SYNC of the input signal in the opposite phase of the first PLL unit 12 based on the number of horizontal clocks applied from the main controller 10 and the phase information. To the second ADC 15.

The second ADC 15 inputs an image signal through an input port, samples the clock of the second PLL unit 14, and converts the image signal into a digital signal.

The first data extracting unit 24 extracts the first data output from the first ADC 12 into the clock of the first PLL 13 to extract the first course control unit 26, the first fine control unit 27, and the signal synthesis unit. It applies to the part 20.

The second data extracting unit 25 extracts the second data output from the second ADC 14 to the clock of the second PLL 15, and the second course control unit 28, the second fine control unit 29, and the signal synthesis unit. It applies to the part 20.

The first coarse controller 26 determines the number of horizontal effective screens of the first data input by the first data extractor 24 and outputs the total horizontal clock counts to the main controller 10.

The first fine control unit 27 finds the correct sampling position of the first data and outputs it to the main controller 10.

Similarly, the second course controller 28 determines the number of horizontal effective screens of the second data input from the second data extractor 25 and outputs the total number of clocks to the main controller 10.

Then, the second fine control unit 29 finds the correct sampling position of the second data and outputs it to the main controller 10.

The main controller 10 is a course data of the first data and the second data from the first course control unit 26, the first fine control unit 27, the second course control unit 28 and the second fine control unit 29, respectively. And fine information is input, and the number of clocks and phase information are transmitted to the first PLL 13 and the second PLL 15.

The signal synthesizer 20 synthesizes the signals output from the first data extractor and the second digital extractor to generate and output desired image data.

The following describes the operation of the image data processing apparatus according to the first embodiment of the present invention having such a configuration.

The main controller 10 according to the input image signal, the image processing apparatus in either one of the single mode (single mode) or the dual mode (dual mode) to sample the input signal to one ADC To operate.

In the dual mode, when data of a frequency higher than a preset frequency band is input into the main controller 10, the frequency bandwidth of the input signal is high, so that the entire horizontal data cannot be sampled by one ADC. Both ADCs (12 and 13) are in the mode of sampling data.

On the other hand, the single mode is to control only one of the first and second ADCs 12 and 13 to operate when data of a frequency lower than a frequency band preset in the main controller 10 is input.

In the dual mode, the main controller 10 applies the number of clocks corresponding to half of the total number of horizontal lines of the first line to the first PLL 13 and the second PLL 15. The second PLL 15 generates and outputs a clock having a pattern in a phase opposite to that of the input clock.

Then, in the dual mode, the first and second ADCs 12 and 14 sample the input signal as shown in FIG. 3A, and in the single mode, only the first ADC 12 samples the input signal as shown in FIG. 3B.

The first data extractor 24 and the second data extractor 25 extract the first data and the second data output from the first ADC 12 and the second ADC 14, respectively.

The first coarse control unit 26 and the second coarse control unit 28 respectively input the first data and the second data from the first data extractor 24 and the second data extractor 25. The number of horizontal effective screens for the data and the second data is determined, and the total horizontal clock number is output to the main controller 10.

The first fine control unit 27 and the second fine control unit 29 find the correct sampling positions of the first data and the second data, respectively, and output them to the main controller 10.

The main controller 10 inputs the course data and the fine information of the first data and the second data to transfer the number of clocks and the phase information to the first PLL 13 and the second PLL 15.

Second embodiment

4 is a block diagram of an image data processing apparatus according to a second embodiment of the present invention.

As shown, the image data processing apparatus according to the second embodiment of the present invention includes an image synchronization separator 31, a first analog / digital converter 32, a first PLL 33, and a second analog / digital converter ( 34), second PLL 35, first DVI decoder 36, second DVI decoder 37, first multiplexer 38, second multiplexer 39, third multiplexer 40, fourth multiplexer 41 The first data extractor 44, the second data extractor 45, the first coarse control unit 46, the first fine control unit 47, the second coarse control unit 48, and the second fine control unit 49. , A main controller 30 and a signal synthesizing unit 51.

Here, the image synchronization separator 31, the first PLC 32, the first ADC 33, the second PLL 34, the second ADC 35, the first course controller 46, and the first fine controller 47 The second course control unit 48, the second fine control unit 49, and the main controller 30 include the image synchronization separating unit 11, the first PLL 12, the first ADC 13, and the second PLL unit of the first embodiment. 14, the same configuration as the second ADC 15, the first course control unit 26, the first fine control unit 27, the second course control unit 28, the second fine control unit 29 and the main controller 10 In order to simplify description as an element, the detailed description is abbreviate | omitted.

The first and second digital video interface (DVI) decoders 36 and 37 decode the input signal when the digital video signal is input.

The first multiplexer 38 multiplexes the data of the first ADC 32 and the data of the first DVI decoder 36, and the second multiplexer 39 includes the clock of the first ADC 32 and the first DVI decoder 36. Multiplex the clock.

The first multiplexer 38 and the second multiplexer 39 are multiplexed according to the clock and the data of the first ADC 32, the first PLL 33, and the first DVI decoder 36.

The third multiplexer 41 multiplexes the data of the second ADC 34 and the data of the second DVI decoder 37, and the fourth multiplexer 42 includes the clock of the second ADC 34 and the second DVI decoder 37. Multiplex the clock.

In the third multiplexer 41 and the fourth multiplexer 42, the data and the clock of the second ADC 34, the second PLL 35, and the second DVI decoder 37 are multiplexed according to the input mode.

The first data extracting unit 44 extracts the data of the first multiplexer 38 into the clock of the second multiplexer 39 and applies it to the first course control unit 46 and the first fine control unit 47.

The second data extracting unit 45 extracts the data of the third multiplexer 41 into the clock of the fourth multiplexer 42 and applies it to the second course control unit 48 and the second fine control unit 49.

The following describes the operation of the image data processing apparatus according to the second embodiment of the present invention having such a configuration.

The image data processing apparatus according to the second embodiment of the present invention may input an analog video signal or a digital video signal.

First, when an analog image signal is input, the main controller 30 according to the frequency of the input image signal, the single mode (single mode) to sample the input signal with one ADC or dual mode (sampling with two ADCs ( dual mode) controls the image processing apparatus to operate in one of two modes.

In the dual mode, the first and second ADCs 32 and 34 sample the clocks input from the first PLL 33 and the second PLL 35, respectively. However, in the single mode, only the first ADC 32 samples to the clock input from the first PLL 33.

The digital data sampled and output from the first ADC 32 and the clock of the first PLL 33 are output to the first multiplexer 38 and the second multiplexer 39, respectively.

In addition, the digital data sampled by the second ADC 34 and the clock of the second PLL 35 are output to the second multiplexer 39 and the fourth multiplexer 40, respectively.

Meanwhile, when the digital video signal is input through the digital interface input port, the main controller 30 decodes the input signal into one DVI decoder according to the frequency of the input digital video signal. The image processing apparatus is controlled to operate in any one of dual modes for decoding by two DVI decoders.

In the dual mode, the first DVI decoder 36 and the second DVI decoder 37 decode the first data and the clock and the second data and the clock, respectively. However, in the single mode, only the first DVI decoder 36 decodes the first data and the clock.

The first data and the clock decoded by the first DVI decoder 36 are applied to the first multiplexer 38 and the second multiplexer 39, respectively.

The second data and the clock decoded by the second DVI decoder 37 are applied to the third multiplexer 41 and the fourth multiplexer 42, respectively.

The first data extracting unit 44 extracts the data of the first multiplexer 38 into the clock of the second multiplexer 39 and applies it to the first course control unit 46 and the first fine control unit 47.

The second data extracting unit 45 extracts the data of the third multiplexer 41 into the clock of the fourth multiplexer 42 and applies it to the second course control unit 48 and the second fine control unit 49.

The first coarse controller 46 and the second coarse controller 48 input the first data and the second data from the first data extractor 44 and the second data extractor 45, respectively. The number of horizontal effective screens for the data and the second data is determined, and the total horizontal clock number is output to the main controller 30.

The first fine control unit 47 and the second fine control unit 49 find the correct sampling positions of the first data and the second data, respectively, and output them to the main controller 30.

The main controller 30 inputs the course data and the fine information of the first data and the second data to transfer the number of clocks and the phase information to the first PLL 33 and the second PLL 35.

5 is a block diagram of the signal synthesis unit of FIGS. 2 and 4.

Since the phase of the sampling clock is inverted in the dual mode, the signal synthesis unit 51 controls the case where the start position is shifted and the position of the data can be changed, and is then multiplexed differently based on the serial mode and the dual mode. After the data is extracted with the clock of the fifth multiplexer, post-processing is performed for the display device to be used.

On the other hand, since it is convenient to process the clock bandwidth in dual mode internally, it divides the clock in single mode and uses it as a system clock.

That is, in the post processor 57, the data path is always used in the parallel mode, and is controlled at a frequency 1/2 times the PLL clock of the original video signal.

The present invention is not limited to the above-described embodiments, and of course, modifications may be made by those skilled in the art without departing from the spirit of the present invention. Therefore, the scope of the claims in the present invention will not be defined within the scope of the detailed description, but will be limited to the claims below.

According to such an image data processing apparatus, an ADC having a limited frequency band can be used to process an input signal having a high bandwidth and a digital input signal.

Claims (14)

In the image data processing apparatus of the display device, A first signal processor configured to sample an image signal input through an input port according to a first sampling clock pattern and convert the image signal into a first digital signal; A second signal processor configured to sample an image signal input through an input port according to a second sampling clock pattern different from the first sampling clock pattern and convert the image signal into a second digital signal; and And a signal synthesizing unit configured to output the image data generated by synthesizing the first digital signal and the second digital signal. The method of claim 1, When an image signal of a predetermined reference frequency or more is input, the first signal processor and the second signal processor control to operate in a dual mode for sampling the input image signal. And a main controller for controlling one of the first signal processing unit and the second signal processing unit to operate in a single mode for sampling the input image signal. The method of claim 1, The first signal processing unit A first PLL unit configured to receive a number of clocks and phase information according to a phase input from the main controller to generate and output a clock of a predetermined pattern locked to a horizontal synchronous signal of an input signal; And a first analog / digital converter for sampling the video signal inputted to the clock inputted from the first PLL unit. The second signal processor A second PLC unit configured to receive the number of clocks and the phase information according to the phase input from the main controller and to lock the horizontal synchronization signal of the input signal and to generate and output a clock having a phase opposite to the clock pattern output from the first PLL unit; ; And a second analog / digital converter for sampling the video signal input to the clock input from the second PLL unit. The method of claim 3, wherein A first data extracting unit extracting first data output from the first analog digital converter into a clock output from the first PLL unit; And a second data extracting unit extracting second data output from the second analog digital converter into a clock output from the second PLL unit. The method of claim 4, wherein A first course controller configured to determine the number of horizontal effective screens of the first data output from the first data extractor and to apply a horizontal total clock number to the main controller; A first wave control unit for finding an accurate sampling position of the first data output from the first data extraction unit and applying the same to the main controller; A second course controller configured to determine the number of horizontal effective screens of the second data output from the second data extractor and to apply a horizontal total clock number to the main controller; and And a second fine control unit which finds an accurate sampling position of the second data output from the second data extracting unit and applies it to the main controller. The method of claim 1, And the signal synthesizing unit receives a clock from the first PLL, operates in the input clock in the dual mode, and divides and inputs the clock in the single mode. In the image data processing apparatus of the display device, A first digital signal processor configured to extract and decode a digital image signal input through an input port at a first interval set; A second digital signal processor configured to extract and decode a digital image signal input through an input port at a second interval that is staggered from the first interval; and And a signal synthesizing unit configured to output the image data generated by synthesizing the signals output from the first digital signal processing unit and the second digital signal processing unit. The method of claim 7, wherein When a digital video signal having a predetermined reference interval or more is input, the first digital signal processing unit and the second digital signal processing unit are controlled to operate in a dual mode for decoding the input digital image signal, and the digital image signal having a predetermined reference interval or less And a main controller configured to control one of the first digital signal processor and the second digital signal processor to operate in a single mode for decoding the input digital video signal. The method of claim 7, wherein A first signal processor configured to sample an image signal input through an input port according to a first sampling clock pattern and convert the image signal into a first digital signal; And a second signal processor configured to sample the image signal input through the input port and convert the image signal into a second digital signal according to a second sampling clock pattern intersected with the first sampling clock pattern. And the signal synthesizing unit outputs image data generated by further synthesizing the signals output from the first signal processing unit and the second signal processing unit. The method of claim 9, The main controller controls the first signal processor and the second signal processor to operate in a dual mode for sampling the input video signal when an image signal of a predetermined reference frequency is input, and inputs a video signal below the set reference frequency. And the first signal processing unit or the second signal processing unit controls to operate in the single mode for sampling the input image signal. The method of claim 9, The first signal processing unit A first PLL unit configured to receive the number of clocks and the phase information according to the image signal input from the main controller to generate and output a clock of a predetermined pattern locked to the horizontal synchronization signal of the input signal; And a first analog / digital converter for sampling the video signal inputted to the clock inputted from the first PLL unit. The second signal processor A second PLL that receives the number of clocks and phase information according to the image signal input from the main controller and is locked to the horizontal synchronization signal of the input signal and generates and outputs a clock having a phase opposite to the clock pattern output from the first PLL unit part; And a second analog / digital converter for sampling the video signal input to the clock input from the second PLL unit. The method of claim 11, A first multiplexer multiplexing data of the first signal processor and the first digital signal processor; A second multiplexer multiplexing each clock of the first signal processor and the first digital signal processor; A first data extractor configured to extract data of the first multiplexer into a clock of the second multiplexer; A third multiplexer which multiplexes data of the second signal processor and the second digital signal processor; A fourth multiplexer multiplexing each clock of the second signal processor and the second digital signal processor; and And a second data extractor configured to extract data of the third multiplexer into a clock of the fourth multiplexer. The method of claim 12, A first coarse controller which determines the number of horizontal effective screens of the first data output from the first data extractor and applies the horizontal total clock number to the main controller; A first coarse controller that finds an accurate sampling position of the first data output from the first data extractor and applies the same to the main controller; A second coarse controller which determines the number of horizontal effective screens of the second data output from the second data extractor and applies the horizontal total clock number to the main controller; and And a second coarse controller which finds an accurate sampling position of the second data output from the second data extracting unit and applies the second coarse controller to the main controller. The method of claim 7, wherein And the signal synthesizing unit receives a clock from the second multiplexer, operates in the input clock in the dual mode, and divides and inputs the clock in the single mode.