KR20020058911A - Method for chip design using standard cell grouping - Google Patents

Abstract

PURPOSE: A method for efficiently designing a chip through grouping by using a standard cell is provided to reduce the time for designing a chip, to efficiently use chip area, and to solve the timing problem during chip designing by an adopting grouping with a standard cell. CONSTITUTION: A circuit to design is divided into various function blocks. The function blocks are expressed by a program. The data in the register transfer level are converted into the data in the gate level through the synthesis of definite logic gates. The data expressed in the gate level are simulated logically. The data are grouped depending on the approximation of the functions or the necessity of timing margin. The grouped data are moduled. The grouped modules are automatically arrange-routed. Logic and timing simulation is performed with the data files. Automatic arrange-routing is performed with the rest of the data.

Description

Method for chip design using standard cell grouping}

The present invention relates to a method for designing an integrated circuit using a standard cell, and more particularly, to a chip design method for stabilizing timing while reducing chip area and chip design time by grouping standard cells according to a use.

Generally, application specific integrated circuit (ASIC) design refers to designing a chip that a designer wants using hardware description language.

Conventionally, in the design of the ASIC chip has been designed by the method shown in FIG.

1 illustrates a conventional method for designing an ASIC chip. In the conventional chip design method, a register transfer level design is performed by first dividing a circuit to be designed into several functional blocks and expressing these functional blocks by a program. Performing step 1; converting the register transfer level data represented by the program into gate level data through synthesis of more specific logic gates; and performing logic simulation on the data represented by the gate level. Three steps, four steps for performing hardware programming with the verified data, and five steps for performing logic and timing simulation with the completed hardware program and the resulting data file.

The detailed design process for each stage is as follows.

In the first step, in order to design the hardware desired by the user, the function and form of the hardware are described using a hardware description language, which is called the design of the register transfer level (10). The logical validity of the hardware data is verified (11).

In step 2, the register transfer level code is sent to a synthesizing tool (e.g., sysnopsys) (20), and converted into logic-level logic circuit data (20) through synthesis of the logic gates.

The gate level logic circuit is more specific than the register transfer level.

When synthesizing the data of the register transfer level into the logic circuit data, and in actual implementation of the chip, a model for the wiring (metal line-1 / 2/3) to be connected to each other between the gates inside the chip, is defined in the allowable area. The wiring model calculated by the number of gates is used (21).

The reason for converting to the gate level by using the wiring model (target library wire model) in the above-described method is to design a chip. Until the chip design is completed, the actual length of the wiring, its resistance value, and its capacitance value are completed. Because you can't get.

In step 3, the data 30 synthesized at the gate level (eg, gate-netlist) is simulated and verified in terms of function and timing (31).

In the fourth step, the actual data is implemented with the verified data, and the device corresponding to the gate level data (eg CMOS, TR) is called out from the physical library to generate a desired chip. (40).

The four step process is called a placement-routing process, and in the case of automatic placement by a computer, it is called an auto batch-routing process.

In the above step 5, a specific device (for example, CMOS and TR) and wiring used for a circuit designed by a user are arranged on a chip through a batch-routing process, and thus the circuit length, resistance value, capacitance value, and the like are required for circuit analysis. All data is calculated.

This data is then used to generate new data to verify the user-designed circuitry. This is called a standard delay format (SDF) file.

In step 5, the user-designed circuit is simulated again from the logic circuit verification step 21 using the SDF file.

At the end of every verification, the designed chip is optimized (50), and the timing is due to some timing critical critical paths (resistance, capacitance values, etc.) for the metal (METAL) -1/2/3 extracted after batch-routing. The lack of margin does not transmit the desired data at the desired time, which means that the data is broken).

Looking at the process of the conventional ASIC chip design can be seen the following problems.

First, in the design of the chip, until the end of the final batch-routing step, the power or timing, such as the resistance or capacitance of the metal-1 / 2/3 that connects the cells that make up the chip, is affected. The exact values are not known. Therefore, programming work performed at the register transfer level or the gate level had to be designed with a large margin in chip design, which resulted in a fatal increase in chip design.

Second, when simulating with the SDF data generated after the final stage of chip design, batch-routing, if critical error occurs in timing due to critical path, it should be corrected. When it occurs at the register transfer level or the gate level, it wastes enormous time because it has to discard existing data and work from scratch.

Third, at the physical level that implements the gate-level data into a real device, cells that are advantageous in area should be gathered on a chip, such as a data path for processing data. Consideration should be given to placement. However, conventionally, in designing the data path, in order to reduce the area on the chip, a user may artificially make a smaller cell without using a standard cell having a large margin. As such, if the user artificially created and used this, the auto batch-routing supported by the chip design tool could not be performed. In addition, a method in which a person directly assigns the arrangement of cells to cells such as a data path has a fatal disadvantage that the area of the chip is efficient, the timing and speed of the entire chip are good, but the time is very long. In the case of using a program tool, that is, an auto batch-routing tool, it takes less time but uses more chip area, supports only standard cells, and deteriorates the speed and timing of the chip.

The present invention is proposed to solve the problems of the prior art as described above, by adopting a grouping technique using a standard cell, while reducing the time required for chip design, efficiently use the chip area, and occurs during chip design An efficient chip design method is implemented through grouping using a standard cell to solve the timing problem.

1 is a flow chart illustrating a conventional AIZ design procedure.

2A illustrates one embodiment of a conventional cell arrangement.

2B illustrates an embodiment of a cell arrangement in accordance with the present invention.

Figure 3 shows an embodiment using a standard cell according to the present invention.

In order to achieve the above object, the chip design method of the present invention includes a first step of designing a register transfer level, dividing a circuit to be designed into a plurality of functional blocks and expressing these functional blocks as a program; A second step of converting data of a register transfer level represented as the program into gate level data through synthesis of more specific logic gates; Performing a logic simulation on the data represented by the gate level; A fourth step of hardware programming with the verified data; A fifth step of grouping and modularizing a block having a similar function to the physical library or requiring a timing margin; A sixth step of auto batch-routing only for the grouped module; A seventh step of performing logic and timing simulation with the generated data file only in the grouped module; And an eighth step of auto batch-routing with the remaining data after auto batch-routing in the sixth step.

Hereinafter, a preferred embodiment of a method for efficiently designing a chip through grouping using a standard cell according to the present invention will be described in detail for each step.

The first step is to divide the circuit to be designed by the user into a plurality of functional blocks, and to describe each functional block. The first stage is commonly referred to as the register transfer level, which uses a rather abstract representation of the function of the functional blocks.

In the second step, contents described in the first step are expressed by using AND, NOT, OR, NAND, NOR gate, etc., which can be commonly seen after description of each functional block at the register transfer level.

In other words, functional blocks that have been abstractly described at the register transfer level appear to be transformed as commonly seen logic circuits.

In the third step, logic simulation is performed to determine whether the logics implemented at the gate level are designed as the designer intended.

In the fourth step, the physical level chip is implemented with the logic-validated gate level data. In the physical library, the gate level data (AND, NOT, OR, NAND, NOR, etc.) is implemented. ) And the device (CMOS, TR) matching the chip is imported.

If there is an inverter at the gate level, the physical library takes one PMOS and NMOS and configures the inverter at the gate level.

In the fifth step, one module (Grouping) to group the functional blocks, such as timers, interrupts, UART, etc. that have the same function at the gate level, or need timing margins in the physical library as one group ( module)

Only the module performs auto batch-routing in the sixth step, performs timing simulation and logic verification, and the remaining blocks are auto batch-routed again in the eighth step.

In the fifth step, since only timing functions that are important for timing margin are placed separately at the physical level, simulation does not need to test all of the functional blocks that are not sensitive to timing unnecessarily, thus reducing the time required for simulation in designing a chip. It can greatly reduce.

2B shows the result of grouping through the above process.

Figure 2a shows a design by the conventional AIZ design method, it can be seen that the remaining functional blocks, except for the repetitive MAC (ROM) cells (ROM) and RAM (RAM) are spread throughout the chip.

In this case, timing-sensitive cells and non-timing-sensitive cells are mixed on one chip, and the chip space is inefficiently used for auto batch-routing.

Figure 2a shows the arrangement arranged by grouping according to the present invention.

By optimizing and modularizing cells with the same function or cells that are sensitive to timing, there are fewer errors in real chip implementation.

In addition, by grouping using a standard cell, auto batch-routing can be used, thus saving a lot of time in chip design.

In addition, it can be seen that in the batch-routing step, timing problems caused by scattering of cells disposed on a chip can be solved.

3 is a diagram illustrating a method for creating and applying a new standard cell having a specific function in advance using a standard cell to a cell repeatedly used according to an embodiment of the present invention.

3 shows a case of designing an adder, which shows that the design time is reduced in designing the adder by making and carrying a frequently used carry into a standard cell in advance.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

According to the present invention, in the conventional chip design, the timing margin is needed for grouping using standard cells, so that auto batch-routing can be performed. By testing, the time required for chip design can be greatly reduced, and the cost of chip design can be lowered by reducing the design area by grouping cells with repetitive shapes such as data paths.

Claims (2)

A first step of designing a register transfer level, dividing a circuit to be designed into a plurality of functional blocks and expressing these functional blocks as a program; A second step of converting data of a register transfer level represented as the program into gate level data through synthesis of more specific logic gates; Performing a logic simulation on the data represented by the gate level; A fourth step of hardware programming with the verified data; A fifth step of grouping and modularizing a cell having the same function in the physical library, having a repetitive shape, or requiring a timing margin; A sixth step of auto batch-routing only for the grouped module; Step 7 of performing logic and timing simulation with the data file generated at this time only for the grouped module. And an eighth step of performing auto batch-routing with the remaining data after the auto batch-routing in the sixth step. The method of claim 1, The fifth step, A method of efficiently designing a chip through grouping using a standard cell, characterized in that grouping using a standard cell.