KR20020057307A - SRAM Compatible Memory For Complete Hiding of The Refresh Operation Using a DRAM Cache Memory - Google Patents

Abstract

PURPOSE: An SRAM compatible memory for hiding a refresh operation using a DRAM cache memory is provided to use a DRAM cell as a data storage medium and hide a refresh operation. CONSTITUTION: An SRAM compatible memory includes 64 memory banks:0-63 and 64 bank access circuits(100-163). Each bank access circuits(100-163) receives outer addresses(AD(0:16)), a read command signal(RD), and a write command signal(WD). Each memory bank: 0-63 includes DRAM memory cells arranged on 16K rows and 32 columns. Each memory bank: 0-63 is coupled to an input/output bus mediation portion(171). Input/output data(DIN/DQ) are transmitted from the memory banks: 0-63 through the input/output bus mediation portion(171). The DRAM memory cells perform refresh operations within a predetermined refresh period in order to store data. In addition, the SRAM compatible memory includes a DRAM cache memory(173), a cache access circuit(175), an access selection circuit(177), a flag memory(179), a tag memory(181), a comparator(183), and a bank mediator(185).

Description

SRAM Compatible Memory For Complete Hiding of The Refresh Operation Using a DRAM Cache Memory}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an SRAM compatible memory that completely hides refreshes externally while using a DRAM (DRAM) cell as a data storage medium.

Generally, random access memory (RAM) in a semiconductor memory device is classified into static random access memory (SRAM) and DRAM. In a typical SRAM, a unit memory cell for storing one bit of information is implemented by four transistors forming a latch structure and two transistors serving as transfer gates. That is, since the conventional SRAM stores data in unit memory cells of a latch structure, a refresh operation for preserving data is not performed externally. And, compared to DRAM, SRAM has the advantages of fast operating speed and low power consumption.

However, since the SRAM unit memory cell is implemented with six transistors, the area memory for layout is larger than that of the DRAM unit memory cell implemented with one transistor and one capacitor. That is, the wafer area of the SRAM required to manufacture the memory devices having the same capacity is about 6 to 10 times the wafer area of the DRAM.

In order to overcome the drawbacks of DRAM and SRAM as described above, efforts have been made to implement a so-called SRAM compatible memory that uses a DRAM cell to hide refresh externally. One such effort is described in US Patent (Patent Number: 5,999,474), filed and filed with US Patent Office by Wingyu Leung et al. In the US Patent (Patent Number: 5,999,474), an SRAM compatible memory is implemented as a memory bank of a plurality of DRAMs and an SRAM cache memory, and a refresh operation is hidden from the outside.

However, according to the US Patent (Patent Number: 5,999,474), an SRAM having the same capacity as one DRAM memory bank is required in the memory. Therefore, it is difficult to implement a highly integrated SRAM compatible memory.

An object of the present invention for solving the problems of the prior art as described above is to provide an SRAM compatible memory using a DRAM cache memory as an SRAM compatible memory to hide the refresh.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating an SRAM compatible memory according to an embodiment of the present invention.

FIG. 2 is a block diagram conceptually illustrating a structure of a memory bank, a DRAM cache memory, a tag memory, and a flag memory in the SRAM compatible memory of FIG. 1.

3 is a diagram illustrating a method of reading an SRAM compatible memory of FIG. 1.

FIG. 4 is a diagram illustrating a writing method of the SRAM compatible memory of FIG. 1.

FIG. 5 is a diagram illustrating an example of the memory bank and the bank access circuit shown in FIG. 1.

One aspect of the present invention for achieving the technical problem of the present invention as described above relates to an SRAM compatible memory. The SRAM compatible memory of the present invention includes a plurality of memory banks and a controller. Each of the plurality of memory banks includes a plurality of DRAM memory cells arranged in rows and columns. Each of the DRAM memory cells performs a refresh within a predetermined refresh period to preserve the stored data. The controller accesses the DRAM memory cells and performs a refresh operation without delay. The controller controls each of the memory banks to independently perform a refresh operation when there is no access request from the outside, and controls to refresh all of the DRAM memory cells within a predetermined refresh period. The controller corresponds to DRAM memory cells of each memory bank, and includes a DRAM cache memory having cache memory cells having the same configuration as that of the DRAM memory cell. Each of the cache memory cells maps data for the most recently addressed DRAM memory cell among the corresponding memory cells.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

According to the present invention, an SRAM compatible memory that is compatible with SRAM while using DRAM memory cells is designed. In the present specification, for convenience of description, a memory that is compatible with SRAM while using DRAM memory cells is referred to as an SRAM compatible memory. The SRAM compatible memory described by way of example herein consists of 64 memory banks, each of which operates independently. Therefore, in different memory banks, reads, writes, and refreshes can be performed in parallel at the same time. A mechanism is provided that allows a refresh drive request to be sent to multiple memory banks simultaneously.

The memory banks that receive the refresh request signal perform a refresh cycle only when the access command is not pending. Each memory bank has its own refresh address counter built therein to provide a refresh address.

In this specification, the DRAM cache memory has the same configuration as each memory bank.

1 is a block diagram illustrating an SRAM compatible memory according to an embodiment of the present invention. The SRAM compatible memory of the present invention includes 64 memory banks 0 to 63 and 64 bank access circuits 100 to 163 corresponding thereto. Each bank access circuit 100 to 163 directly or externally receives an external address AD [0:16], a read command signal RD and a write command signal WD that require access to the corresponding memory banks 0 to 63. FIG. Receive indirectly. Each of the memory banks 0 to 63 included in an embodiment of the present invention includes DRAM memory cells (not shown) arranged in 16K rows and 32 columns, and the input / output bus arbiter 171 is provided. Is commonly coupled to. That is, the input / output data DIN / DQ is transmitted to / from the memory banks 0 to 63 through the input / output bus arbiter 171. Each of the DRAM memory cells needs to be refreshed within a predetermined refresh period in order to preserve stored data. Although not described in detail herein, the input / output bus arbiter 171 may be implemented to read data to a part of the memory banks 0 to 63 and perform a write operation to the other part. The implementation of such an input / output bus arbiter 171 is obvious to those skilled in the art.

In addition, the SRAM compatible memory of the present invention includes a DRAM cache memory 173, a cache access circuit 175, an access select circuit 177, a flag memory 179, a tag memory 181, a comparator 183 and a bank arbitration. Group 185.

The SRAM compatible memory of the present invention is driven in response to the following signals: external addresses AD [0:16], read command signal RD, write command signal WD, and the like. As a signal input externally to drive the SRAM compatible memory of the present invention, it can be seen that signals for controlling the refresh of each memory bank 0 to 63 are not used.

The upper ones AD [14:19] of the external addresses AD [0:19] are input to the bank arbiter 185. Bank arbiter 185 is coupled in parallel to memory banks 0-63. The bank arbiter 185 specifies one or two or more of the memory banks 0 to 63 in response to the upper addresses AD [14:19]. The lower addresses AD [0:13] of the external addresses AD [0:19] are input to the bank access circuits 100 to 163. The memory cells in each memory bank 0 to 63 are designated by the combination of the lower addresses AD [0:13]. As a result, a memory bank and a row of memory cells are designated by the combination of the upper addresses AD [14:19] and the lower addresses AD [0:13]. In addition, the bank arbiter 185 generates an operation control signal CONT for controlling the access state of the designated memory banks 0 to 63.

Each memory bank 0 to 63 is associated with bank access circuits 100 to 163 which are independently driven. This is to enable a multi-bank parallel operation in which a plurality of memory banks 0 to 63 are simultaneously accessed. That is, 32 data can be input and output at the same time. In this embodiment, since the read bus DB [0:31] and the write bus DA [0:31] are built in, respectively, data is written in one memory bank and read in another memory bank. The operation can be performed.

In the present specification, the remaining circuit elements except for memory banks 0 to 63 may be included in the controller 1000. The controller 1000 performs refresh on DRAM memory cells without a delay for the refresh operation. The controller 1000 controls the refresh operation when the memory bank does not have an access request from the outside, and refreshes all DRAM memory cells within a predetermined refresh period. In addition, the controller 1000 controls the refresh of the DRAM memory cells not to collide with the access of the DRAM memory cells.

2 is a block diagram conceptually illustrating a structure of memory banks 0 to 63, a DRAM cache memory 173, a tag memory 181, and a flag memory 179 in an SRAM compatible memory according to an embodiment of the present invention. to be.

The DRAM cache memory 173 includes cache memory cells (not shown) arranged in 16K rows and 32 columns, similarly to the memory banks 0 to 63. The cache memory cells included in the cache DRAM cache memory 173 have the same structure as a DRAM memory cell having one transistor and one capacitor as a unit structure. The tag memory 181 records addresses of memory banks 0 to 63 provided with data mapped to the DRAM cache memory 173. That is, in the first row of the tag memory 181, the six-bit bank address of the memory banks 0 to 63 associated with the data recorded in the first row of the DRAM cache memory 181 (for example, in the case of the memory bank 4). Stores 000100). The flag memory 179 stores the valid display bit V and the modified display bit M. As shown in FIG. The valid indication bit V indicates that the data of the associated DRAM cache memory 173 is valid. That is, the valid display bit V indicates that the data stored in the DRAM cache memory 173 of the address that is externally accessed is valid data that has previously been mapped data of any of the memory banks 0 to 63. If the valid display bit V is not set, the data stored in the DRAM cache memory 173 of the externally accessed address indicates that the data has not been previously accessed. The modification indication bit M indicates that data of the DRAM cache memory 173 and data of the memory banks 0 to 63 indicated by the tag memory 181 are different from each other. If the modified indication bit M is set, it indicates that data stored in the DRAM cache memory 173 and data stored in the memory bank indicated by the tag memory 181 are different from each other.

When the access to the SRAM compatible memory is started, the lower address AD [0:13] among the external addresses AD [0:19] is assigned to the tag memory 181, the flag memory 179, and the bank access circuit 100. ~ 163). By the lower address AD [0:13], the rows of the memory banks 0 to 63 to be accessed are designated. The upper address AD [14:19] is received by the bank arbiter 185 and specifies which memory bank is accessed. In the tag memory 181, the address of the memory bank stored in the specific row is read out to the comparator 183 by the lower address AD [0:13]. The flag memory 179 provides the access selector 177 and the bank arbiter 185 with information on whether the data in the row of the DRAM cache memory 173 being accessed is valid data or converted data. The comparator 183 compares the upper address AD [14:19] input to the bank arbiter 185 with the address of the memory bank read out from the tag memory 181.

Referring back to FIG. 1, the access selector 177 responds to the read / write command signal RD / WD and the hit signal VHIT so that the current access is performed by the read hit HIT and the write hit HIT. ), A read miss (MISS) or a write miss (MISS) is determined. Although not described in detail herein, the read / write command signals RD / WD are signals generated by a combination of control signals (not shown) input from the outside.

Here, the hit HIT refers to a case in which data of an externally accessed address exists in the DRAM cache memory 173. In this case, the memory banks 0 to 63 are not accessed, and the DRAM cache memory 173 is accessed. The MISS refers to a case in which data of an externally accessed address does not exist in the DRAM cache memory 173. In this case, data is not accessed from the DRAM cache memory 173, but memory banks 0 to 63 are accessed.

When the comparator 183 detects a match, the comparator 183 detects a read or write hit HIT and activates the hit signal VHIT. If the comparator 183 detects a mismatch, it detects that there is a read or write miss and deactivates the hit signal VHIT. The hit signal VHIT is provided to the bank arbiter 185 and the access selector circuit 177.

In the SRAM compatible memory of the present invention, a write-back policy is applied. The write-back policy is described by four possible read and write processing methods: read hit (HIT), read miss (MISS), write hit (HIT), write miss (MISS). Subsequently, the write-back policy of the SRAM compatible memory of the present invention is described in detail.

3 is a diagram illustrating a method of reading an SRAM compatible memory of the present invention. Referring to FIG. 3, first, an external address AD [0:19] and a read command are input (S301). Then, the tag memory 181 and the flag memory 179 are accessed (S303). The data accessed in the tag memory 181 is compared with the upper address AD [14:19] that designates a specific memory bank, and a hit / miss is determined (S305). If the current access is a read hit access, the data stored in the DRAM cache memory 173 is mapped from a designated memory bank. Therefore, data of the DRAM cache memory 173 is accessed (S307). Data stored in the DRAM cache memory 173 is transmitted to the input / output bus arbiter 171 and outputted (S309). Since memory banks 0 to 63 are not accessed during read hit access, all memory banks 0 to 63 can be refreshed.

If the access currently in progress is a read miss access, the DRAM cache memory 173 does not store data corresponding to the addressed memory banks, rows and columns. Subsequently, it is determined whether or not the deformation display bit M is set in the row and column associated with the flag memory 179 (S311). If the modified indication bit M is set, the access selector circuit 177 controls the data of the DRAM cache memory 173 to indicate a miss to be written to the associated memory bank. Then, the modification display bit M is released (S313). Only when the modification indication bit M is set, this write-back operation is performed. At the same time, data of the rows and columns of the memory bank corresponding to the currently input address are written to the DRAM cache memory 173 (S315). Data stored in the designated memory bank is transmitted to the input / output bus arbiter 171 and outputted (S317). If the modified indication bit M is not set, since the data stored in the DRAM cache memory 173 coincides with the data stored in the specific memory bank, the write back operation is not performed. Even during read miss access, the remaining memory banks to which read access or write back is not progressed may be refreshed.

4 is a diagram illustrating a writing method of an SRAM compatible memory of the present invention. Referring to FIG. 4, first, an external address AD [0:19] and a write command are input (S401). Then, the tag memory 181 and the flag memory 179 are accessed (S403). The data accessed in the tag memory 181 is compared with the upper address AD [14:19] that designates a specific memory bank, and a hit / miss is determined (S405). If the current access is a write hit access, the data to be written is written to the DRAM cache memory 173 instead of the addressed memory bank. That is, data previously written to the DRAM cache memory 173 is overwritten by newly input data (S407). In the flag memory 179, the modified display bit M corresponding to the addressed row and section is written (S409). Since the memory banks 0 to 63 are not accessed during the write hit access, all the memory banks 0 to 63 can be refreshed.

If the access currently in progress is a write miss access, the DRAM cache memory 173 does not store data corresponding to the addressed memory bank, row and column. Subsequently, it is determined whether or not the deformation display bit M is set in the row and column associated with the flag memory 179 (S411). If the modified indication bit M is set, the access selector circuit 177 controls the data of the DRAM cache memory 173 to indicate a miss to be written to the associated memory bank. Then, the modified display bit M is released (S413). Only when the modification indication bit M is set, this write-back operation is performed. At the same time, data of the rows and columns of the memory bank corresponding to the currently designated address are written to the DRAM cache memory 173 (S415). If the modified indication bit M is not set, since the data stored in the DRAM cache memory 173 matches the data stored in the designated memory bank, the write back operation is not performed. Even during write miss access, the remaining memory banks in which no write access or write back proceeds can be refreshed.

When the valid display bit V is not generated in the flag memory 179, it indicates that data recorded in the DRAM cache memory 173 is invalid. Therefore, when the valid display bit V is not generated in the flag memory 179, the rows and columns of the memory bank designated by the current address are accessed regardless of whether the access currently in progress is a hit or a miss. The data is mapped to the DRAM cache memory 173.

On the other hand, while the refresh is being performed on the DRAM cache memory 173, the access currently being processed is recognized as a miss access, and the accesses to the memory banks 0 to 63 are performed.

FIG. 5 is a diagram illustrating an example of one of the memory banks 0 to 63 and the bank access circuits 100 to 163 illustrated in FIG. 1. In this specification, memory bank 0 and bank access circuit 100 are representatively shown. In addition, for convenience of description, the memory cell array 501, the sense amplifier 503, and the word line driver 505 are included in the memory bank 0, and the remaining control circuits are included in the bank access circuit 100. .

As described above, the bank access circuit 100 includes circuits for controlling the refresh of the bank memory 0. Examples of circuits for controlling the refresh are the refresh request signal generator 509, the refresh address counter 517, and the refresh drive circuit 521. The refresh request signal generator 509 receives the bank select signal XBAK0 and the operation control signal CONT, and generates a refresh request signal REREFQ. The bank select signal XBAK0 is a signal provided from the bank arbiter 185 (see FIG. 1) and is a signal specifying memory bank 0. FIG. The operation control signal CONT is also a signal provided from the bank arbiter 185 and includes information on the access state of the memory bank 0 designated by the bank select signal XBAK0. That is, the operation control signal CONT indicates whether the access state of the memory bank 0 is read access or write access. When the refresh request signal REFREQ is activated, the memory bank 0 may be refreshed. In the embodiment described herein, the refresh can be performed when the bank select signal XBAK0 designating the memory bank 0 is not activated. In addition, even when the bank selection signal XBAK0 is activated, refreshing can be performed when no read or write access is in progress.

When the refresh request signal REFREQ is activated, the refresh drive circuit 521 generates a refresh drive signal XREF that transitions every predetermined period. In other words, the refresh driving circuit 521 controls refreshing of the DRAM memory cells in the memory bank 0 every predetermined refresh period. In addition, the refresh driving circuit 521 controls to suspend the refresh while the access is performed to the DRAM memory cell in the corresponding memory bank. The refresh address counter 517 generates the refresh addresses RA [0:13] that change sequentially in response to the transition of the refresh drive signal XREF.

In addition, 515 selectively transmits an external address AD [0:13] and a refresh address RA [0:13] to the row decoder 513. That is, when the refresh request signal REFREQ is activated, The master 515 selects the refresh address RA [0:13] and sends it to the row decoder 513. The row decoder 513 decodes the transmitted address and transmits the decoded address to the word line driver 505 of the memory bank 0. On the other hand, the column decoder 511 decodes the external address AD [0: 4] to drive the sense amplifier 503 of the memory bank 0.

In the case of the SRAM compatible memory of the present invention, assuming that the refresh condition of the memory bank becomes the worst, it is as follows. First, data written in the DRAM cache memory 173 is data mapped to the same memory bank, for example, memory bank 0, in which the modified indication bit M is written in the flag memory 179 in all of the data. . If a read miss access is continuously generated during one refresh period, all data stored in the DRAM cache memory 173 is written to the memory bank 0. Therefore, memory bank 0 cannot perform refresh in one cycle. Subsequently, read miss access proceeds again to the memory bank 0 during the next refresh cycle. Then, the refresh does not proceed even during the next refresh cycle. In this case, however, the modified display bit M is not generated in the flag memory 179. Thus, subsequent accesses do not access memory bank 0. Therefore, refresh for memory bank 0 is possible in this interval.

In conclusion, if the memory cells of the DRAMs embedded in the memory banks 0 to 63 can hold data for two or more times the refresh period, the SRAM compatible memory of the present invention can be normally driven. That is, when the refresh cycle is set to be 1/2 or less of the time that the memory cells of the DRAM embedded in the memory banks 0 to 63 can hold data, the SRAM compatible memory of the present invention can be normally driven.

According to the present invention, the refresh, which is a weak point of the conventional DRAM, is controlled using the DRAM cache memory, so that the refresh is substantially performed in the DRAM bank, but data access is possible without being limited externally.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. For example, in the embodiment described herein, the DRAM cache memory has been described as having the same configuration as each memory bank. However, it is apparent to those skilled in the art that the DRAM cache memory may have a smaller capacity than each memory bank, and may be designed such that the mapping is performed only for addresses that are primarily accessed. In addition, in this specification, an example in which the tag memory and the DRAM cache memory are separated and embedded is illustrated. However, the tag memory and the DRAM cache memory may use one memory such as a CAM (Contents Access Memory). Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the SRAM compatible memory of the present invention, a DRAM cache memory is used instead of the existing SRAM cache memory. Instead of the memory bank in which the refresh is performed, data is accessed from the DRAM cache memory. Therefore, while the refresh is performed internally as in the conventional DRAM, externally, the same data access time as the SRAM can be guaranteed. Therefore, according to the SRAM compatible memory of the present invention, high integration can be easily implemented, and chip size can be significantly reduced.

Claims (17)

For SRAM compatible memory, A plurality of memory banks including a plurality of DRAM memory cells arranged in a row and a column, each of the DRAM memory cells performing a refresh within a predetermined refresh period to preserve stored data; A controller for accessing the DRAM memory cells and performing a refresh without a delay for a refresh operation, wherein the memory bank controls a refresh operation when there is no access request from the outside, and the DRAM memory cells within a predetermined refresh period. And the control unit for controlling to refresh the whole, The control unit A DRAM cache memory corresponding to DRAM memory cells of respective memory banks, the cache memory cells having cache memory cells having the same configuration as the DRAM memory cell, wherein each of the cache memory cells is the most recently addressed DRAM among the corresponding memory cells; And said DRAM cache memory for mapping data for memory cells. The method of claim 1, wherein the control unit And SRAM compatible circuits for controlling to perform the refresh operation independently in each memory bank. According to claim 1, Further equipped with a bus arbiter, The memory banks are coupled in parallel with the bus arbiter, And data read from at least one of the memory banks is provided to the bus arbiter and mapped to the DRAM cache memory. According to claim 1, And a tag (TAG) memory for recording an address of the memory bank in which data mapped to the DRAM cache memory is provided. The method of claim 4, wherein And a flag (FLAG) memory for storing information on whether the data stored in the DRAM cache memory is valid data and whether the data is modified. The method of claim 4, wherein Further comprising a bank arbiter in which the memory banks are coupled in parallel, The bank arbiter In response to an external address, controlling to select at least one of the memory banks. The method of claim 4, wherein And a comparator for comparing an address of a memory bank currently specified with an address of a memory bank of data mapped to the DRAM cache memory. The method of claim 2, wherein the bank access circuit is And a refresh driving circuit which controls refreshing of the DRAM memory cells in the corresponding memory banks at predetermined refresh cycles. The method of claim 8, wherein the refresh driving circuit And while the access is performed to the DRAM memory cell in the corresponding memory bank, controlling to suspend the refresh for the memory cell in the corresponding memory bank. The memory of claim 1, wherein the SRAM compatible memory comprises: If the access command is generated while the DRAM cache memory is being refreshed, the memory bank is accessed. The method according to any one of claims 1 to 9, wherein the refresh period is SRAM compatible memory, characterized in that less than half of the time that the memory cell can retain data without refreshing. The method according to any one of claims 1 to 9, And the DRAM cache memory has the same configuration as that of each of the memory banks. For SRAM compatible memory, A plurality of memory banks comprising a plurality of DRAM memory cells arranged in a row and a column, each of the memory cells performing refresh within a predetermined refresh period to preserve data; A controller for refreshing the DRAM memory cells, wherein the refresh of the DRAM memory cells is controlled so as not to collide with an access of the memory cells, the controller including a DRAM cache memory; The DRAM cache memory Each of the memory banks corresponds to DRAM memory cells, each of which has cache memory cells having the same configuration as that of the DRAM memory cell, wherein each of the cache memory cells corresponds to the most recently addressed DRAM memory cell among the corresponding DRAM memory cells. SRAM compatible memory, characterized in that for mapping data for. The method of claim 13, And a tag (TAG) memory for recording an address of the memory bank in which data mapped to the DRAM cache memory is provided. The method of claim 14, And a comparator for comparing an address of a currently designated memory bank with an address of a memory bank of data previously mapped to the DRAM cache memory. The method according to any one of claims 13 to 15, And the DRAM cache memory has the same configuration as that of each of the memory banks. The method according to any one of claims 13 to 15, And the DRAM cache memory has the same configuration as that of each of the memory banks.