KR20020052471A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20020052471A KR20020052471A KR1020000081760A KR20000081760A KR20020052471A KR 20020052471 A KR20020052471 A KR 20020052471A KR 1020000081760 A KR1020000081760 A KR 1020000081760A KR 20000081760 A KR20000081760 A KR 20000081760A KR 20020052471 A KR20020052471 A KR 20020052471A
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- gate electrode
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- spacer
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004140 cleaning Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract 1
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000003749 cleanliness Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 선택적 에피택셜 성장(selective epitaxial growth : SEG)방법을 적용하여 소오스/드레인영역을 형성하는 공정 시 게이트전극 상부에 노출되는 면적을 증가시킨 후 전세정공정을 실시하여 SEG방법으로 형성되는 SEG막의 특성을 안정화시켜 소자의 동작 특성 및 신뢰성을 향상시키는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, after increasing the area exposed on the gate electrode in the process of forming a source / drain region by applying a selective epitaxial growth (SEG) method. The present invention relates to a method for manufacturing a semiconductor device, which performs a pre-cleaning step to stabilize the characteristics of the SEG film formed by the SEG method, thereby improving the operating characteristics and reliability of the device.
일반적으로, P형 또는 N형 반도체기판에 N 또는 P형 불순물로 형성되는 PN접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다.In general, a PN junction formed of an N or P-type impurity on a P-type or N-type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region.
따라서, 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면확산에 의한 쇼트채널이펙트를 방지하기 위하여 접합 깊이를 얕게 형성해야 한다.Therefore, in the semiconductor device having a reduced channel width, the junction depth must be shallow in order to prevent short channel effects due to side diffusion from the diffusion region.
이하, 종래기술에 따른 반도체소자의 제조방법에 대하여 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described.
먼저, 반도체기판의 원하는 부분에 원하는 불순물의 종류를 이온주입하여 웰과 트랜지스터의 채널 부분 및 소자분리 영역의 아래 부분에 원하는 형태로 불순물이 존재하도록 한다.First, a desired type of impurity is implanted into a desired portion of the semiconductor substrate so that impurities exist in a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region.
다음, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상에 소자분리절연막을 형성하고, 전체표면 상부에 게이트절연막을 형성한 다음, 다결정실리콘층과 마스크절연막을 형성한다.Next, a device isolation insulating film is formed on a portion of the semiconductor substrate, which is intended as a device isolation region, a gate insulating film is formed over the entire surface, and then a polysilicon layer and a mask insulating film are formed.
다음, 게이트 전극 마스크를 사용하여 마스크절연막, 다결정실리콘층 및 게이트절연막을 순차적으로 식각하여 마스크절연막패턴, 게이트 전극 및 게이트절연막패턴의 적층구조를 형성한다.Next, the mask insulating film, the polysilicon layer and the gate insulating film are sequentially etched using the gate electrode mask to form a stacked structure of the mask insulating film pattern, the gate electrode and the gate insulating film pattern.
그 다음, 상기 적층구조 측벽에 절연막 스페이서를 형성한다.Next, insulating film spacers are formed on the sidewalls of the stacked structure.
다음, 상기 구조를 전세정하여 활성영역 표면의 불순물을 제거한다.Next, the structure is pre-cleaned to remove impurities on the surface of the active region.
그리고, 상기 노출된 반도체기판의 활성영역에 SEG막을 성장시킨다.Then, a SEG film is grown in the active region of the exposed semiconductor substrate.
다음, 상기 SEG막에 이온주입공정을 실시하여 소오스/드레인 영역을 형성한다.Next, an ion implantation process is performed on the SEG film to form source / drain regions.
그 다음, 상기 이온주입공정으로 주입된 도펀트를 활성화시키기 위하여 열처리공정을 실시하면 상기 도펀트들이 상기 반도체기판 내로 약간 확산되어 엘리베이티드 소오스/드레인이 형성되게 된다.Then, when the heat treatment process is performed to activate the dopant implanted in the ion implantation process, the dopants are slightly diffused into the semiconductor substrate to form an elevated source / drain.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, SEG방법을 이용한 엘리베이티드 소오스/드레인영역을 적용하는 경우 전세정공정의 불안정성에 의해 SEG막의 성장속도가 불균일하기 때문에 공정의 신뢰성을 확보하기 어려운 문제점이 있다.As described above, the method of manufacturing a semiconductor device according to the related art is difficult to secure process reliability because the growth speed of the SEG film is uneven due to the instability of the pre-cleaning process when the elevation source / drain region using the SEG method is applied. There is this.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 시스템 IC 로직 소자의 제조공정에서 SEG방법을 적용하여 소오스/드레인영역을 형성하는 공정 시 게이트전극 측벽의 질화막 스페이서를 소정 두께 제거하여 게이트전극 상부에 노출되는 면적을 증가시킨 후 NH4OH용액과 HF용액을 이용한 전세정공정을 실시함으로써 SEG방법으로 형성되는 SEG막의 특성을 안정화시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the nitride film spacers on the sidewalls of the gate electrode are removed by a predetermined thickness during the process of forming the source / drain regions by applying the SEG method in the manufacturing process of the system IC logic device. It is an object of the present invention to provide a method for manufacturing a semiconductor device which stabilizes the characteristics of the SEG film formed by the SEG method by increasing the area exposed to the NH 4 OH solution and HF solution.
도 1 내지 도 4 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도.1 to 4 is a cross-sectional view of the process by the method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 소자분리막11: semiconductor substrate 13: device isolation film
15 : 게이트절연막패턴 17 : 게이트전극15 gate insulating film pattern 17 gate electrode
19 : 제1산화막패턴 20 : 제2산화막패턴19: first oxide film pattern 20: second oxide film pattern
21 : 제1질화막 스페이서 22 : 제2질화막 스페이서21: first nitride film spacer 22: second nitride film spacer
23 : SEG막23: SEG film
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판에 활성영역을 정의하는 소자분리막을 형성하는 공정과,Forming a device isolation film defining an active region on the semiconductor substrate;
상기 반도체기판 상부에 게이트절연막과 게이트전극을 형성하는 공정과,Forming a gate insulating film and a gate electrode on the semiconductor substrate;
전체표면 상부에 소정 두께의 산화막과 질화막을 형성하는 공정과,Forming an oxide film and a nitride film of a predetermined thickness on the entire surface;
상기 질화막과 산화막을 전면식각하여 제1질화막 스페이서와 상기 게이트전극 측벽 및 제1질화막 스페이서의 하부에 제1산화막패턴을 형성하는 공정과,Forming a first oxide pattern on the first nitride layer spacer, the sidewall of the gate electrode, and the first nitride layer spacer by etching the entire surface of the nitride layer and the oxide layer;
상기 제1질화막 스페이서를 습식식각방법으로 소정 두께 제거하여 상기 제1산화막패턴을 노출시키는 제2질화막 스페이서를 형성하는 공정과,Removing a predetermined thickness of the first nitride film spacer by a wet etching method to form a second nitride film spacer exposing the first oxide film pattern;
상기 구조를 NH4OH용액과 HF용액으로 전세정하여 상기 제1산화막패턴을 소정 두께 제거하여 게이트전극의 측벽과 상기 제2질화막 스페이서의 상부 및 하부 가장자리를 소정 두께 노출시키는 제2산화막패턴을 형성하는 공정과,The structure is pre-washed with NH 4 OH solution and HF solution to remove the first oxide pattern by a predetermined thickness to form a second oxide pattern that exposes the sidewall of the gate electrode and the upper and lower edges of the second nitride spacer by a predetermined thickness. Fair,
상기 노출된 게이트전극의 상부 및 측벽과 반도체기판의 활성영역에 SEG막을 성장시켜 게이트전극 상부의 표면적을 증가시키는 것을 특징으로 한다.The surface area of the gate electrode may be increased by growing an SEG film on the exposed and upper sidewalls of the gate electrode and the active region of the semiconductor substrate.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 활성영역을 정의하는 소자분리막(13)을 형성한다.First, an isolation layer 13 defining an active region is formed on the semiconductor substrate 11.
다음, 전체표면 상부에 게이트절연막과 게이트전극용 도전층을 순차적으로 형성하고, 게이트전극 마스크를 식각마스크로 상기 게이트전극용 도전층과 게이트절연막을 식각하여 게이트전극(17)과 게이트절연막패턴(15)을 형성한다.Next, the gate insulating layer and the gate electrode conductive layer are sequentially formed on the entire surface, and the gate electrode 17 and the gate insulating layer pattern 15 are etched by etching the gate electrode conductive layer and the gate insulating layer using a gate electrode mask as an etch mask. ).
다음, 전체표면 상부에 산화막과 질화막을 순차적으로 형성한다. 이때, 상기 산화막은 TEOS막으로 형성되고, 상기 질화막은 800 ∼ 1000Å 두께로 형성하되, 일반적으로 형성되는 두께보다 300 ∼ 500Å 두껍게 형성한다.Next, an oxide film and a nitride film are sequentially formed on the entire surface. In this case, the oxide film is formed of a TEOS film, the nitride film is formed to a thickness of 800 ~ 1000 Å, 300 ~ 500 Å thicker than the thickness generally formed.
그 다음, 상기 산화막과 질화막을 전면식각공정으로 제거하여 제1산화막패턴(19)과 제1질화막 스페이서(21)를 형성한다. 이때, 상기 제1산화막패턴(19)은 상기 게이트전극(15) 측벽 및 반도체기판(11)의 활성영역에 'L'자형으로 형성되고, 상기 제1질화막 스페이서(21)는 상기 제1산화막패턴(19) 상에 형성된다. (도 1 참조)Thereafter, the oxide film and the nitride film are removed by an entire surface etching process to form the first oxide film pattern 19 and the first nitride film spacer 21. In this case, the first oxide layer pattern 19 is formed in an 'L' shape on the sidewall of the gate electrode 15 and the active region of the semiconductor substrate 11, and the first nitride layer spacer 21 is formed in the first oxide layer pattern. It is formed on (19). (See Figure 1)
다음, 상기 제1질화막 스페이서(21)를 건식 또는 습식식각공정으로 소정 두께 제거하여 상기 제1산화막패턴(19)을 일부 노출시키는 제2질화막 스페이서(22)를 형성한다.Next, the first nitride layer spacer 21 is removed by a dry or wet etching process to form a second nitride layer spacer 22 partially exposing the first oxide layer pattern 19.
이때, 상기 습식식각공정을 실시하는 경우 인산을 식각용액으로 이용하여 상기 제1질화막 스페이서(21)를 300 ∼ 500Å 식각하여 상기 제1산화막패턴(19)의 상부 및 하부 가장자리를 일부 노출시킨다. (도 2 참조)In this case, when the wet etching process is performed, the first nitride layer spacer 21 is etched by 300 to 500 Å using phosphoric acid as an etching solution to partially expose the upper and lower edges of the first oxide layer pattern 19. (See Figure 2)
다음, 상기 구조를 NH4OH용액과 HF용액을 이용하여 전세정공정을 실시한다.Next, the structure is subjected to a pre-cleaning step using NH 4 OH solution and HF solution.
상기 전세정공정은 다음과 같은 방법으로 실시된다.The pre-cleaning step is carried out in the following manner.
먼저, 상기 NH4OH용액을 이용한 전세정공정은 NH4OH : H2O2: H2O가 1 : 4 : 20의 농도를 갖는 NH4OH용액을 이용하여 70 ∼ 100。의 온도에서 10 ∼50분간 실시한다. 상기 NH4OH용액을 이용한 전세정공정 시 케미칼 산화막(chemical oxide layer)이 5 ∼ 15Å 두께 형성되고, 상기 제1산화막패턴(19)이 200 ∼ 300Å 정도 식각된다.First, the NH 4 OH solution was chartered information processes using NH 4 OH: H 2 O 2: H 2 O 1: 4 at a temperature of from 70 to 100. The use of NH 4 OH solution having a concentration of 20 10 Carry out for 50 minutes. In the pre-cleaning process using the NH 4 OH solution, a chemical oxide layer is formed to have a thickness of 5 to 15 GPa, and the first oxide layer pattern 19 is etched to about 200 to 300 GPa.
다음, 상기 HF용액을 이용한 전세정공정은 HF : H2O가 1 : 100의 농도를 갖는 HF용액을 이용하여 1분간 실시한다. 이때, 상기 케미칼 산화막이 제거되고, 상기 제1산화막패턴(19)이 60 ∼ 70Å 정도 식각되어 상기 게이트전극(17)의 측벽과 상기 제2질화막 스페이서(22)의 하부 가장자리를 일부 노출시키는 제2산화막패턴(20)이 형성된다. 또한, 상기 HF용액을 이용한 전세정공정으로 상기 게이트전극과 활성영역의 표면에 존재하던 불순물을 완전히 제거할 수 있으며, 수소로 패시베이션하여 후속 SEG공정을 용이하게 한다. (도 3 참조)Next, the pre-cleaning step using the HF solution is carried out for 1 minute using HF solution having a concentration of 1: 100 HF: H 2 O. In this case, the chemical oxide layer is removed, and the first oxide layer pattern 19 is etched by about 60 to 70Å to expose a sidewall of the gate electrode 17 and a lower edge of the second nitride layer spacer 22. The oxide film pattern 20 is formed. In addition, the pre-clean process using the HF solution can completely remove the impurities present on the surface of the gate electrode and the active region, and passivation with hydrogen to facilitate the subsequent SEG process. (See Figure 3)
그 다음, 상기 노출되는 게이트전극(17)의 표면과 활성영역의 표면에 SEG막(23)을 성장시킨다. 이때, 상기 SEG막(23)의 가장자리인 ⓧ부분, 즉 SEG막(23)의 두께가 얇게 형성되는 퍼??(facet)이 상기 제2질화막 스페이서(22) 하부에 형성되므로 후속 소오스/드레인영역을 형성하기 위한 이온주입공정을 균일하게 실시할 수 있다. 또한, 상기 게이트전극(17)의 노출되는 면적을 넓힐 수 있기 때문에 후속 살리사이드공정 후 게이트전극(17)의 저항을 낮출 수 있다. (도 4 참조)Next, the SEG film 23 is grown on the surface of the exposed gate electrode 17 and the surface of the active region. At this time, a thin portion, which is an edge of the SEG film 23, that is, a facet having a thin thickness of the SEG film 23 is formed under the second nitride film spacer 22, so that subsequent source / drain regions are formed. The ion implantation process for forming a film can be performed uniformly. In addition, since the exposed area of the gate electrode 17 can be increased, the resistance of the gate electrode 17 can be lowered after the subsequent salicide process. (See Figure 4)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, SEG방법을 이용하여 엘리베이티드 소오스/드레인영역을 형성하는 공정에서 게이트전극 측벽의 질화막 스페이서를 습식식각공정으로 소정 두께 제거하여 게이트전극 상부의 노출 면적을 증가시킨 후 전세정공정으로 상기 노출된 게이트전극의 표면의 청정도를 높임으로써 후속 SEG공정으로 형성되는 SEG막의 특성을 안정하게 하여 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of fabricating a semiconductor device according to the present invention, in the process of forming an elevated source / drain region by using the SEG method, the nitride spacer of the sidewall of the gate electrode is removed by a wet etching process to remove a predetermined thickness from the upper portion of the gate electrode. By increasing the exposed area of the substrate, the cleanliness of the surface of the exposed gate electrode is increased by the pre-cleaning process to stabilize the characteristics of the SEG film formed by the subsequent SEG process, thereby improving the operating characteristics and reliability of the device.
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| KR100555573B1 (en) * | 2004-09-10 | 2006-03-03 | 삼성전자주식회사 | Semiconductor device having a extended junction by seg layer and method of fabrication the same |
| KR101025740B1 (en) * | 2003-12-19 | 2011-04-04 | 주식회사 하이닉스반도체 | Method for fabricating transistor having deposited junction |
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| KR101025740B1 (en) * | 2003-12-19 | 2011-04-04 | 주식회사 하이닉스반도체 | Method for fabricating transistor having deposited junction |
| KR100555573B1 (en) * | 2004-09-10 | 2006-03-03 | 삼성전자주식회사 | Semiconductor device having a extended junction by seg layer and method of fabrication the same |
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